CN107683522A - 使用闪光灯进行芯片的非接触转移和焊接的设备和方法 - Google Patents

使用闪光灯进行芯片的非接触转移和焊接的设备和方法 Download PDF

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Publication number
CN107683522A
CN107683522A CN201680031100.8A CN201680031100A CN107683522A CN 107683522 A CN107683522 A CN 107683522A CN 201680031100 A CN201680031100 A CN 201680031100A CN 107683522 A CN107683522 A CN 107683522A
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chip
substrate
carrier
light pulse
light
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CN107683522B (zh
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罗布·雅各布·亨德里克斯
丹·安东·万登恩德
埃德斯格·康斯坦特·彼得·斯米茨
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Nederlandse Organisatie voor Toegepast Natuurwetenschappelijk Onderzoek TNO
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Nederlandse Organisatie voor Toegepast Natuurwetenschappelijk Onderzoek TNO
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Abstract

在闪光灯(5)和基底(3)之间设置芯片载体(8)。芯片(1a)在芯片载体(8)的面向基底(3)的一侧上被附接到芯片载体(8)。在芯片(1a)和基底(3)之间设置焊料材料(2)。闪光灯(5)产生用于加热芯片(1a)的光脉冲(6)。芯片(1a)的加热使得芯片(1a)从芯片载体(8)朝向基底(3)脱离,以朝向基底(3)非接触地转移。焊料材料(2)通过与经加热的芯片(1a)接触而至少部分地熔融,用于将芯片(1a)附接到基底(3)。可以在闪光灯(5)和芯片(1a)之间设置掩蔽装置(7),掩蔽装置(7)包括被配置成使光脉冲(6)的光(6a)选择性地通过到达芯片(1a)的掩蔽图案(7a)。可以如下将具有(例如由不同的尺寸(表面积和/或厚度)、热容量、吸收率、传导率、焊料接合的数目和/或尺寸引起的)不同加热特性的多个芯片同时从芯片载体(8)转移到基底(3)并且焊接到基底(3),使用掩蔽装置(7),通过掩蔽装置(7)的光脉冲(6)在不同区域中造成不同光强度,从而用不同光强度加热芯片,用于至少部分地补偿所述不同加热特性,以减少由于光脉冲(6)的加热而导致的芯片之间的温度差距。

Description

使用闪光灯进行芯片的非接触转移和焊接的设备和方法
技术领域和背景技术
本公开内容涉及焊接,特别地涉及用于将芯片焊接到基底上的设备和方法。
原则上,可以将简单柔性***例如具有晶体管或光电子装置的逻辑功能完全印刷在基底(例如箔或刚性板)上。然而,对于更复杂的***,需要开发其中印刷电路***与硅基集成电路或本文称为芯片部件或简称为“芯片”的表面安装器件(SMD)部件组合的混合***。为了使器件功能化,通常具有不同尺寸的多个芯片部件可能需要互连到基底上的电路迹线,例如印刷或蚀刻的铜电路。这可以例如使用炉回流焊接、导电粘合剂接合或面朝上(face-up)芯片集成来实现。然而,这些过程被认为是耗时的和/或与具有低分解温度的低成本聚酯箔不兼容的。特别是对于焊接过程,通常使用的聚合物基底倾向于在高于150℃的热负荷下劣化和变形。
例如,回流焊接通常可以用于互连刚性基底例如FR4或陶瓷上的厚芯片。然而,回流焊接与低成本柔性箔和卷对卷(R2R)处理兼容性差,因为它需要将整个板维持在通常高于200℃的焊料的液相线温度以上持续较长保持时间。这通常导致使用通常具有多个回路的大的线上炉的耗时过程。长的保温时间也可能导致柔性箔自身的变形或劣化或其有机表面涂层或粘合剂的劣化。认为不可能通过使用工业标准的无铅合金将常规焊料炉回流在低成本的聚酯箔例如聚对苯二甲酸乙二醇酯(PET)上,因为PET具有远低于这些焊料的液相线温度(>200℃)的约120℃至150℃的最高处理温度。
作为替选,例如可以在相当的焊接时间下使用红外(IR)加热。例如,可以使用红外激光点来依次加热每个焊接连接。然而,在激光点焊接时,小的光点区域可能需要对每个部件的光点的精确定位。此外,在R2R过程中应用这种技术是有挑战性的,因为激光点需要对准移动的基底上的多个芯片。此外,该过程可能是耗时的。因此,这些方法中的一些可能仍然基于定期不断的被迫停止。
作为另一替选,可以使用通过闪光灯的高能量光脉冲进行的大面积照射。例如,Van denEnde等在Electronic Materials Letters第10卷第6期(2014)第1175-1183页的文章中描述了用于柔性电子***的柔性箔上的薄芯片的大面积光子闪光焊接。有利地,当加热脉冲的时间刻度足够短以避免柔性聚合物基底的扩散加热时,可以在高于箔的最高处理温度的温度下焊接部件。然而,如果(箔)基底和/或部件对光的吸收不同,则会导致选择性加热。此外,电子装置通常由多个芯片部件组成。这可能导致不同部件的加热性能的进一步差异,这使得温度和焊接过程难以控制。
因此,仍然需要改进芯片到基底的焊接,例如更快、更可靠、与柔性箔基底、卷对卷处理以及不同的芯片和/或基底兼容。
发明内容
本公开内容的一个方面可以实施为用于将芯片焊接到基底的方法。该方法包括在闪光灯和基底之间设置芯片载体。芯片在芯片载体的面向基底的一侧上被附接到芯片载体。可以在芯片和基底之间设置有焊料材料。例如,焊料材料可以在芯片的下侧或两者上设置在要放置芯片的基底上。用闪光灯产生光脉冲来加热芯片。芯片的加热使芯片从芯片载体朝向基底脱离。此外,焊料材料通过与经加热的芯片接触而至少部分地熔融,用于在焊料材料再固化之后将芯片附接到基底。
有利地,光脉冲可以用于从载体基底脱离芯片和加热芯片以进行焊接。例如,对芯片的加热可以通过载体和/或芯片与载体之间的牺牲粘合剂层的部分分解而使芯片从基底脱离。此外,通过加热的分解可以引起可以增加芯片冲量的快速的气体形成,从而将芯片朝向基底发射。发现来自闪光灯的光脉冲在这方面是特别有利的,因为它可以在相对大的面积上传送具有均匀的强度并且具有相对长的脉冲长度例如在毫秒量级的高能量光脉冲。另外,掩蔽装置可以用于对来自闪光灯的光进行图案化,例如以照射仅芯片的位置并且使载体和基底的其余部分不受影响。
可以将闪光灯诱导转移与例如激光诱导转移进行对比,在激光诱导转移中芯片可能倾向于在空中翻转,因为在较大的面积上更难以产生均匀的光强度。例如,当在芯片的一侧的光强度较高时,在该特定点处可能较早发生分层。与例如在拾取和放置装置中使用的机械臂相比,使用芯片的光诱导转移与焊接的组合的生产能力可以更高。
当使用对于高能量闪光灯为典型的相对长的毫秒脉冲时,芯片也可以在脱离之后在载体和目标基底之间的空中的同时被连续加热。如果芯片不接触诸如基底的散热器,则在空中时可以相对较快地加热芯片,并且可以达到相对较高的温度。通过调节脉冲的强度,它可以适应于转移的不同阶段,例如在空中的转移期间具有较小强度以防止过热。光调节可以例如通过掩蔽装置和/或闪光灯的控制来实现。可替选地或另外地,通过在芯片位于基底上(其中焊料材料在芯片和基底之间)的同时将光脉冲投射到芯片上,芯片可以被加热并且使焊料材料至少部分熔融,用于将芯片附接到基底。
本方法也可以用于特别是使用单个光脉冲使多个芯片一次同时转移。然而,当转移不同的芯片时,芯片可以具有例如由不同尺寸(表面积和/或厚度)、热容量、吸收率、传导率、焊料接合的数目和/或尺寸等引起的不同加热特性。不同加热特性会使得难以均匀地控制转移和焊接。为了缓解这个问题,可以在闪光灯和芯片之间设置掩蔽装置,从而在通过掩蔽装置的光脉冲的不同区域中造成不同的光强度。因此不同的芯片可以用来自(单个)光脉冲的不同的光强度加热。
使用不同光强度例如每单位面积的功率或能量可以至少部分地补偿芯片的不同加热特性,以减少由于通过光脉冲加热而导致的芯片之间的温度差距。不同的芯片可以例如在相对小的温度范围内达到预定温度,用于以受控制的方式熔融与芯片接触的焊料材料。将理解,本技术具有闪光灯曝光的优点,例如由于脉冲持续时间和强度能够相对较快地曝光多个部件的大面积、与柔性箔和卷对卷处理兼容。此外,通过使用掩蔽装置,例如由于改进了对不同芯片的加热的控制,该技术可以是可靠的。掩蔽装置也可以用来防止基底例如在芯片之间的地方曝光。这可以防止对基底的损坏。
通过经由掩蔽装置的掩蔽图案向芯片同时透射单个脉冲,多个芯片可以在不同强度下曝光。例如,掩蔽图案包括选择性衰减冲击掩模的脉冲的不同区域的滤光器区域。因此,可以实现最高至光脉冲的原始强度的范围内的不同强度。例如,第一强度可以被设置在比第二强度低或高百分之十至百分之九十之间。掩蔽装置可以具有横跨其表面的可变透射或反射,以衰减或以其他方式选择性地使一部分光通过到达芯片。例如,掩蔽图案可以具有可变的透射系数、反射系数和/或吸收系数。
掩蔽装置可以基于反射和/或透射,并且可以包括例如固定掩蔽图案或可变掩蔽图案。例如,可变掩蔽图案可以通过数字镜、LCD或其他可调光学装置的电子控制来实现。可变掩蔽图案可以通过例如可以根据控制信号切换其透射系数的像素网格形成。可变光强度例如可以通过将多个像素设置为相同的特定透射系数或通过使用具有不同透射系数组合的像素的组合来实现。
因此,可以获得适用于不同芯片的焊接的不同光强度。例如,每脉冲传送到芯片的总能量可以被调到例如由其尺寸和/或材料组成确定的芯片的热容量。例如,当芯片相对薄时,其可以通过每表面积相同的能量或光强度比相对厚的芯片被更快地加热。具有较大表面积的芯片可以接收来自脉冲的更多光,但是它也可以经由较大的接触面积更快地冷却。为了计算所需的光强度,芯片的热容量也可以相对于其接收光的表面积被归一化。
掩蔽装置和芯片载体可以例如在芯片所附接的不同区域具有不同透射特性的单个箔中是单独的或集成的。另外,通过使用透明芯片载体,芯片可以被通过芯片载体透射的光脉冲加热。掩蔽装置可以被放置在闪光灯和芯片之间,例如用于至少部分地阻挡部分光脉冲直接照射芯片周围的基底或用于根据一个或更多个芯片的加热特性来衰减脉冲。掩蔽装置也可以被集成为芯片载体的部分,例如作为保持芯片的柔性箔上的图案。
本公开内容的方面还可以实施为用于将芯片焊接到基底的设备。该设备包括被配置成确定基底的位置的基底处理器。载体处理器被配置成确定芯片载体的位置,其中芯片在芯片载体的面向基底的一侧上附接至芯片载体。对准装置和控制器被配置成将附接到芯片载体的芯片参考芯片在基底上的目标位置对准。闪光灯被配置成产生用于加热芯片的光脉冲。该设备可以例如用于执行本文描述的方法,反之亦然。因此,芯片的加热可以使芯片从芯片载体朝向基底脱离,其中芯片和基底之间的焊料材料通过与经加热的芯片接触而至少部分地熔融,用于将芯片附接到基底。
另外的方面可以实施为包括掩蔽装置的设备,该掩蔽装置被设置在闪光灯和芯片之间并且被配置成在通过掩蔽装置的光脉冲的不同区域中造成不同的光强度,以用不同的光强度加热具有不同加热特性的芯片。例如,控制器可以用于根据本文描述的方法来控制该设备的一个或更多个部分。因此,该设备可以被控制,使得不同光强度可以至少部分地补偿芯片的不同加热特性,以减少由于通过光脉冲加热而导致的芯片之间的温度差距。
掩蔽装置可以例如包括具有不同滤光器区域的掩蔽图案。例如,具有不同光学特性的两个、三个或更多个滤光器区域可以被设置用于选择性地加热具有不同光强度的两个或更多个芯片,同时至少部分地阻挡以其他方式辐照芯片之间的基底的光。例如,不同的滤光器区域可以具有不同的透射系数、反射系数和/或吸收系数。光可以例如经由通过掩模透射或通过从掩模反射来到达芯片。掩蔽图案区域可以例如通过闪光灯和掩模之间的可选的照明光学装置均匀照射。该设备还可以包括可选的投射光学装置以将掩蔽图案成像到芯片上。可替选地,可以将掩模放置在靠近基底的位置和/或使用相对准直的光束来投射掩模的图案而不需要另外的光学装置。投射的图案可以包括例如三个或更多个不同的光强度,即用于两个不同芯片的至少两个不同的强度以及用于周围的基底的第三强度。
芯片定位装置可以被配置成确定芯片例如相对于基底和/或掩蔽装置的位置。例如,芯片定位装置可以通过将芯片放置在预定位置或以其他方式已知的位置来确定位置。可替选地或另外地,芯片传感器例如相机可以用于检测和确定芯片的位置。芯片的尺寸也可以与位置同时确定或通过传感器检测例如使用相机来确定。因此,由掩蔽图案确定的光的位置和强度可以根据芯片的位置和尺寸来控制。控制器可以使芯片的位置与投射的掩蔽图案的强度同步。例如,控制器可以根据芯片的相应尺寸来控制掩模滤光器区域的透射系数。例如,通过为用于相对较小尺寸的芯片的一部分光脉冲设置相对较低的光强度,芯片可以被加热到与由相对较高的光强度照射的相对较大的芯片相同的温度。
例如,芯片可以在被光脉冲照射之前通过芯片供应单元例如拾取和放置装置设置在基底上,其中焊料材料在芯片和基底之间。可替选地,可以通过照射芯片载体箔来放置芯片,芯片载体箔将芯片脱离在基底上方同时加热芯片以进行焊接。通过另外使用掩蔽装置,具有不同加热特性例如不同尺寸的芯片可以从载体非接触地转移到目标基底。掩蔽装置和芯片载体可以是单独的装置或集成为单个件,例如包括在柔性箔内。芯片载体和/或掩蔽装置可以与基底同步移动,以将芯片放置在预期位置,同时保持基底例如在卷对卷过程中移动。可替选地或另外地,当光被施加到芯片上时,基底处理器可以减慢或停止基底的移动。
该设备可以包括在芯片被放置在基底上之前将焊料材料施加到基底和/或芯片上的焊料供应单元,其中焊料材料在基底和芯片之间。例如,可以使用刮刀涂覆装置和/或模印装置来施加焊料材料,例如将焊料凸块施加到要放置芯片的基底上的传导迹线。该设备可以包括迹线施加单元,例如印刷装置以在施加焊料材料之前将传导迹线施加到基底。可替选地或另外地,也可以将已经形成的迹线提供给基底。
附图说明
从以下描述、所附权利要求和附图中,本公开内容的设备、***和方法的这些特征和其他特征、方面和优点将变得更好理解,在附图中:
图1A和图1B示意性地示出了用于将芯片焊接到基底上的步骤;
图2A和图2B示意性地示出了包括掩模的另外的实施方案;
图3A和图3B示意性地示出其中芯片载体和掩模被集成的实施方案;
图4A和图4B示出了用于一次焊接多个不同芯片的步骤;
图5A和图5B示意性地示出了用可调掩模加热芯片;
图6A和图6B示意性地示出了使用卷对卷过程将芯片焊接到基底上的阶段的实施方案。
具体实施方式
在一些情况下,可以省略对公知的装置和方法的详细描述,以免使本***和方法的描述不清楚。用于描述特定实施方案的术语不旨在限制本发明。如本文所使用的,除非上下文另外明确指出,否则没有明确数量词修饰的形式也旨在包括复数形式。术语“和/或”包括一个或更多个相关所列术语的任何和所有组合。将理解,术语“包括”和/或“包含”表示所述特征的存在,但不排除存在或添加一个或更多个其他特征。还将理解,当方法的特定步骤被称为在另一步骤之后时,除非另外说明,否则其可以直接跟随所述另一步骤或者可以在执行特定步骤之前执行一个或更多个中间步骤。同样将理解,当描述结构或部件之间的连接时,除非另外说明,否则可以直接地或通过中间结构或部件来建立该连接。
示例性实施方案的描述旨在结合被认为是整个书面说明书的一部分的附图来阅读。在附图中,为了清楚起见,***、部件、层和区域的绝对尺寸和相对尺寸可能被放大。可以参照本发明的可能理想化的实施方案和中间结构的示意图和/或截面图来描述实施方案。在说明书和附图中,相同的附图标记始终指代相同的元件。相对术语以及其派生词应被解释为指代如下所述的或如在讨论的附图中所示的取向。这些相对术语是为了便于描述,并不要求***以特定取向构造或操作,除非另有说明。
图1A和图1B示意性地示出了用于芯片1a到基底3的转移和焊接的实施方案。
根据一个方面,该附图示出了用于将芯片1a焊接到基底3的方法。在闪光灯5和基底3之间设置芯片载体8。将芯片1a在芯片载体8的面向基底3的一侧上附接到芯片载体8。在芯片1a和基底3之间设置焊料材料2。闪光灯5产生用于加热芯片1a的光脉冲6。芯片1a的加热使得芯片1a从芯片载体8朝向基底3脱离。焊料材料2通过与经加热的芯片1a接触而至少部分地熔融,用于将芯片1a附接到基底3。
根据另一方面或另外的方面,该附图还示出了用于将芯片1a焊接到基底3的设备的部分。例如,该设备包括被配置成确定基底3的位置的基底处理器4。在所示的实施方案中,基底处理器4包括在卷对卷过程中处理例如柔性基底的辊。多种类型的基底处理器也是可能的,例如保持基底的分开的片或板的平台。此外,该设备可以包括被配置成确定芯片载体8的位置的载体处理器18,其中芯片1a在芯片载体8的面向基底3的一侧上附接至芯片载体8。在所示实施方案中,载体处理器18包括例如在卷对卷过程中处理载体基底8的辊。该设备优选地包括对准装置和控制器(未示出)。这些可以被配置成将附接至芯片载体8的芯片1a相对于芯片1a在基底3上的目标位置3t例如基底表面上的电传导迹线对准。例如,载体基底8和目标基底3被对准以同步移动,其中芯片1a被保持在迹线3t上方。
在一个实施方案中,芯片载体8包括对光脉冲6透明的载体基底,其中芯片1a被通过芯片载体8透射的光脉冲6加热。在另外的实施方案中,芯片载体8包括透明聚合物膜或具有牺牲粘合剂层的透明玻璃基底。例如,芯片载体8包括其上通常放置硅晶片的所谓“标准化(蓝色)透明聚合物膜”。这意味着原则上这些切割晶片的制造商不必改变其处理。也可以使用其他芯片载体基底,例如所谓的“紫粘合带”。优选地,使用厚度小于50微米的薄(例如硅)芯片来促进从顶部到底部的热传输以便焊接。
在一个实施方案中,光脉冲6的光6a使得芯片载体8和芯片1a之间的粘合材料8a分解,从而使芯片1a从芯片载体8脱离。粘合材料可以是芯片载体8的部分或在芯片和载体之间形成单独的粘合剂层。在一个实施方案中,芯片1a至少部分地通过和/或沿着朝向基底3的重力方向转移。可替选地或另外地,从芯片载体8的脱离可以使芯片1a具有朝向基底3的初始速度。例如,粘合材料8a的分解使朝向基底3发射芯片1a的气体形成。例如,快速的气体形成可以为芯片1a提供初始冲量。
在一个实施方案中,芯片1a在距基底3至少50微米优选地至少100微米的距离Z处附接到芯片载体8。在更近的距离处,芯片可能在被转移之前开始偶然地接触基底3。在另一或另外的实施方案中,芯片1a在距基底3最多1毫米优选地最多500微米的距离Z处。在更远的距离处,对芯片的定位的控制可能劣化。例如,芯片与目标基底(包括任何传导迹线和/或焊料凸块)之间的间隙为125微米。这可以提供约10微米的对准精度。例如,基底3包括具有12微米厚的铜迹线和焊料凸块的聚酰亚胺。根据对芯片定位所需的控制量,其他距离也是可能的。可以在基底3和基底8的相向表面之间测量距离Z,可替选地在(最厚的)芯片的面向表面与基底3上的接触点之间(包括其间的任何焊料材料)测量距离Z。在后一种情况下,距离Z是芯片可以在载体和目标基底之间行进的距离的量度。
在一个实施方案中,在芯片1a在芯片载体8和基底3之间的距离Z上行进(未示出)的同时,光脉冲6的透射光6a继续照射芯片1a。在另一或另外的实施方案中,在芯片1a位于基底3上(图1B)的同时,光脉冲6的透射光6a继续照射芯片1a。在另一或另外的实施方案中,根据时间对冲击芯片1a的光的强度Ia进行调节。例如,光强度Ia在芯片从芯片载体8脱离的时刻比芯片1a在芯片载体8和基底3之间行进的时间期间高,并且其中光强度Ia在行进之后当芯片接触基底3上的焊料材料2时增加。在另一或另外的实施方案中,光6a的光强度在芯片从芯片载体8脱离的时刻比芯片1a在芯片载体8和基底3之间行进的时间期间高。在另一或另外的实施方案中,光6a的光强度在芯片接触焊料材料2的时刻比芯片1a在芯片载体8和基底3之间行进的时间期间高。在另一或另外的实施方案中,光6a的光强度在芯片从芯片载体8脱离的时刻比芯片接触基底3上的焊料材料2的时刻高。例如,光调节由闪光灯5和/或闪光灯和基底之间的掩蔽装置造成。
优选地,使用例如由(脉冲)氙闪光灯产生的毫秒级光脉冲6。典型的脉冲可以传送例如在0.5ms至10ms之间的脉冲时间内的1J/cm2至20J/cm2之间的总能量。例如,可以使用例如具有2ms的脉冲长度和10J/cm2的脉冲强度的氙闪光灯或其他高强度闪光灯。也称为闪光管的闪光灯通常包括电弧灯,电弧灯被配置成产生用于短持续时间的强烈的(非相干的)光,例如具有500微秒至20毫秒之间的脉冲长度的光脉冲。也可以是更短或更长的脉冲。例如闪光管由一定长度的任意端具有电极并充满气体的玻璃管制成,当被触发时,该气体电离并传导高压脉冲以产生光。例如,可以使用氙闪光灯以产生足以照射芯片表面的高光强度并且例如通过经由芯片传导的热使与芯片接触的焊料材料至少部分地熔融。
图2A和图2B示意性地示出了另外的实施方案,其中掩蔽装置7被设置在闪光灯5和芯片1a之间。掩蔽装置7可以至少部分地阻挡光脉冲6的部分直接照射芯片周围的基底3和/或芯片载体8。在一个实施方案中,掩蔽装置7包括设置在闪光灯5和芯片1a之间的掩蔽图案7a、7c。例如,掩蔽图案7a、7c被配置成使光脉冲6的光6a选择性地通过到达芯片1a,并且阻挡未冲击芯片1a的其他光到达基底3。例如,在一个实施方案中,高强度脉冲氙闪光灯与(光刻)掩模组合使用,以对冲击芯片的光脉冲进行图案化。在另一或另外的实施方案中,芯片载体8和/或掩蔽装置7被包括在柔性箔中,例如针对芯片所附接的不同区域具有可变的透射率。
图3A示意性地示出了其中掩蔽装置7被集成为芯片载体基底8的顶部上的层的实施方案。
图3B示出了掩蔽装置7和芯片载体8进一步集成在单个基底中的另一实施方案。在一个实施方案中,掩蔽装置7包括根据芯片所附接的位置具有不同程度的透明度的箔。例如,区域7a可以是透明的,用于为第一芯片7a提供脉冲的全部强度,而另一区域(未示出)可以是部分不透明或半透明的,用于衰减例如冲击第二芯片的脉冲6的光,例如具有每照射面积较低的热容量。
图4A和图4B示意性地示出了其中多个芯片1a、1b被同时从芯片载体8转移到基底3并且焊接到基底3的实施方案。有利地,一个或更多个芯片的转移和焊接可以通过单个光脉冲6实现。
在一个实施方案中,具有不同的加热特性C1、C2的两个或更多个不同的芯片1a、1b被附接到芯片载体8。在另一或另外的实施方案中,在闪光灯5与芯片1a、1b之间设置掩蔽装置7,从而在通过掩蔽装置7的光脉冲6的不同区域6a、6b中造成不同的光强度Ia、Ib。因此,芯片1a、1b可以用不同的光强度Ia、Ib加热,用于至少部分地补偿不同的加热特性C1、C2,以减少由于光脉冲6的加热而导致的芯片之间的温度差距。
在一个实施方案中,该设备包括被配置成确定基底3和/或芯片1a、1b的位置的基底处理器4。例如,该设备包括被配置成确定芯片1a、1b相对于基底3的位置的传感器(未示出)。
在一个实施方案中,光脉冲6经由掩蔽装置7的掩蔽图案7a、7b、7c被同时透射到芯片1a、1b。例如,掩蔽图案7a、7b、7c包括使光脉冲6的具有第一光强度Ia的第一部分6a通过到达第一芯片1a的第一滤光器区域7a;以及使光脉冲6的具有第二光强度Ib的第二部分6b通过到达第二芯片1b的第二滤光器区域7b,其中第一光强度Ia不同于第二光强度Ib。光强度测量为例如每单位面积的接收部分光脉冲的芯片表面。
在一个实施方案中,第一芯片1a具有第一热容量C1,第二芯片1b具有与第一热容量C1不同的第二热容量C2。例如,在所示的实施方案中,第一芯片1a比第二芯片1b薄。物体的热容量被定义为例如作为转移给物体的热能的量与物体因此升高的温度的比率。对于较大的物体或对于包含具有较大比热容量(每单位质量)或体积热容量(每单位体积)的材料的物体,热容量会较大。优选地,不同的光强度Ia、Ib至少部分地补偿热容量C1、C2的差异或不同的芯片1a、1b之间的加热特性的其他差异,用于减小由光脉冲6加热的芯片的温度差距。
在一个实例中,具有不同厚度和表面积的两个部件可能需要用于焊接部件的不同的输入能量。例如,较低的厚度和表面可以导致低热容量,从而导致每输入能量单位相对高的温度增加,而相反地,减少数目的焊料接合可能需要较低的输入能量用于焊接相应的接合。使用具有对应透射滤光器的掩模,可以局部调整曝光因子,以允许用单个脉冲焊接不同的芯片。滤光器可以是例如具有固定的或可配置的透射率。
在一个实施方案中,该设备包括被配置成均匀地照射具有掩蔽图案7a、7b、7c的掩蔽装置7的区域的可选的照明光学装置(未示出)。在另一或另外的实施方案中,该设备包括被配置成将掩蔽图案7a、7b、7c的图像投射到芯片1a、1b上的可选的投射光学装置(未示出)。在所示实施方案中,在芯片1a、1b位于基底3上的同时,光脉冲6的透射光6a、6b被投射到芯片1a、1b上,其中焊料材料2在芯片和基底之间,从而加热芯片1a、1b。经加热的芯片1a、1b可以使焊料材料2至少部分地熔融,用于将芯片1a、1b附接到基底3(在再固化之后)。
在一个实施方案中,掩蔽装置7包括被配置成将光脉冲6选择性地透射到芯片1a、1b的掩蔽图案7a、7b、7c。在另一或另外的实施方案中,掩蔽图案7a、7b、7c包括具有第一透射系数Ta的第一滤光器区域7a,第一滤光器区域7a被配置成将光脉冲6的具有第一光强度Ia的光6a透射到第一芯片1a,用于熔融第一芯片1a和基底3之间的焊料材料2;和具有第二透射系数Tb的第二滤光器区域7b,第二滤光器区域7b被配置成将光脉冲6的具有第二光强度Ib的光6b透射到第二芯片1b,用于熔融第二芯片1a和基底3之间的焊料材料2。在另外的实施方案中,第一透射系数Ta不同于第二透射系数Tb,以用不同光强度Ib、Ib同时照射芯片1a、1b。透射系数是对通过表面或光学元件的电磁波(光)的多少的量度。例如,可以针对波的振幅或强度来计算透射系数。也通过取表面或元件之后的值与之前的值之比来计算。
在一个实施方案中,掩蔽图案的滤光器区域7a、7b、7c是可控的,以调整透射系数Ta、Tb。例如,掩蔽图案7a、7b、7c由可调光学装置例如数字镜的网格、LCD和/或偏振光学装置形成。在一个实施方案中,掩蔽图案7a、7b、7c包括具有第三透射系数Tc的第三滤光器区域7c,第三滤光器区域7c被配置成基本上阻挡光脉冲6的部分,例如否则将被直接投射到基底3上的部分。
在一个实施方案中,掩蔽装置7包括玻璃上的光刻金属。例如,使用铝或铬以两种、三种或更多种不同的强度改变脉冲的光强度。在一个实施方案中,掩蔽装置7包括冷却装置(未示出),例如水冷却以处理高能量光脉冲的(部分)吸收。
图5A示出了用于将芯片1a焊接到基底3上的设备,其中掩蔽装置7包括具有像素7p的第一滤光器区域7a,具有第一透射系数Ta的像素7p将光脉冲6的具有第一光强度Ia的光6a透射到第一芯片1a。
图5B示出了用于将芯片1a焊接到基底3上的设备,其中将光脉冲6的部分6a透射到芯片1a的滤光器区域7a包括具有不同透射系数的多个像素7p,其中第一光强度Ia由通过具有不同透射系数的像素7p透射的组合光强度来确定。例如,可以使用抖动的像素图案来减小冲击芯片1a的光6a的总体或平均强度Ia。图5A和图5B的实施方案可以例如与掩蔽装置7和基底3之间的芯片载体组合使用。
图6A示出了用于在卷对卷制造过程中转移和焊接芯片的设备的实施方案。在所示的实施方案中,基底处理器4包括处理可以是柔性的箔基底3的辊。在另一或另外的实施方案中,芯片载体8和/或掩蔽装置7也包括在柔性箔中。在另一或另外的实施方案中,芯片载体8和/或掩蔽装置7被配置成与基底3同步移动。在一个实施方案中,闪光灯5被配置成传送单个脉冲6以转移和焊接具有可能不同的尺寸或其他加热特性的多个芯片1a、1b。
在该实施方案中,该设备包括对准装置12(例如相机或其他传感器)和控制器15。在另一或另外的实施方案中,该设备包括被配置成控制对准装置12、基底处理器4和/或基底处理器4的控制器15。例如,控制器15被编程为将附接至芯片载体8的芯片相对于基底3上的目标位置对准。可替选地或另外地,控制器15被编程为将光脉冲6的不同区域6a、6b的不同光强度与不同芯片1a、1b的位置对准。
图6B示出了用于在卷对卷制造过程中焊接芯片的设备的另一实施方案。在该实施方案中,可变调整的掩蔽装置7被用在固定的位置处例如在由合适的载体处理器(未示出)保持的芯片载体8的上方。
在一个实施方案中,该设备包括被配置成根据芯片1a、1b的相应尺寸可变地调整光强度Ia、Ib的控制器15。在一个实施方案中,控制器15被配置成从芯片定位装置来确定芯片1a、1b的位置并且控制掩蔽装置7和/或基底处理器4。例如,控制器15被编程为将光脉冲6的不同区域6a、6b的不同光强度与不同芯片1a、1b的位置对准。例如,控制器15被编程为根据芯片1a、1b的相应尺寸来控制掩蔽装置7的滤光器区域的透射系数。
在一个实施方案中,控制器15被编程为针对用于具有每照射面积相对高的热容量的芯片1b例如相对厚的芯片的光脉冲6的部分6b设置相对高的光强度。在另一或另外的实施方案中,控制器15被编程为针对用于具有每照射面积相对低的热容量的芯片1a例如相对薄的芯片的光脉冲6的部分6a设置相对低的光强度。在一个实施方案中,控制器15被编程为针对用于相对较大尺寸的芯片1b的光脉冲6的部分6b设置相对较高的透射系数Tb,并针对用于相对较小尺寸的芯片1a的光脉冲6的部分6a设置相对较低的透射系数Ta。
在一个实施方案中,该设备包括被配置成检测迹线13上基底3的位置的传感器12(例如相机)。传感器12可以向可以用于对准芯片的位置和/或光的强度的控制器15提供反馈。在一个实施方案中,基底处理器4被配置成在光6a、6b被施加到芯片1a、1b时减慢或停止基底3的移动。
在一个实施方案中,该设备包括被配置成在芯片1a、1b被放置在基底3上之前将焊料材料2施加到基底3和/或芯片1a、1b上的焊料供应单元9,其中焊料材料2在芯片和基底之间。例如,焊料供应单元9包括刮刀涂覆装置和/或模印装置。
在一个实施方案中,该设备包括被配置成在施加焊料材料2之前将传导迹线施加(例如印刷)至基底3的迹线施加单元10,其中在使用中,芯片1a、1b电连接至迹线。
为了清楚和简洁描述的目的,本文将特征描述为相同的或单独的实施方案的部分,然而,将理解,本发明的范围可以包括具有所描述特征的全部或一些的组合的实施方案。例如,将清楚,参照图6A和图6B描述的装置也可以用于除了卷对卷处理之外的其他实施方案中。例如,控制器15也可以被用来控制芯片在固定基底上的放置。而且本文描述的其他装置10、9、12可以单独或以任何组合的方式可能在如本文描述的控制器15的单独或共享的控制下应用在其他实施方案中。控制器可以用允许其参照任何实施方案根据本文所描述的方法来执行操作步骤的软件来编程。
对于领会本公开内容的益处的技术人员而言,用于获得相似功能和结果的其他组合也将是很明显的。例如,电子部件和机械部件可以被组合或分成一个或更多个可替选部件。如讨论和示出的实施方案的各种元件提供了某些优点,例如芯片的快速和可靠的焊接和/或芯片的非接触转移。当然,要理解,上述实施方案或过程中的任何一个可以与一个或更多个其他实施方案或过程组合,以在寻找和匹配设计和优点方面提供更进一步的改进。要理解的是,本公开内容为卷对卷处理提供了特别的优点,并且通常可以应用于其中芯片被焊接的任何应用。
最后,上述讨论仅仅是为了举例说明本***和/或方法,并且不应被解释为将所附权利要求限制为任何特定实施方案或一组实施方案。相应地,说明书和附图以说明性的方式被看待,并不旨在限制所附权利要求的范围。在解释所附权利要求时,应当理解,词语“包括”不排除存在除了给定的权利要求中列出的那些以外的其他要素或行为;没有明确数量词修饰的要素不排除存在多个这样的要素;权利要求中的任何附图标记不限制其范围;数个“方式”可以由相同或不同的项目或实施的结构或功能来表示;任何公开的装置或其部分可以组合在一起或被分成另外的部分,除非另外特别说明。在相互不同的权利要求中叙述某些措施的事实并不表示这些措施的组合不能被用来获益。特别地,权利要求的所有工作组合被认为是固有地公开的。

Claims (15)

1.一种用于将芯片(1a)焊接到基底(3)的方法,所述方法包括:
-在闪光灯(5)和所述基底(3)之间设置芯片载体(8),其中所述芯片(1a)在所述芯片载体(8)的面向所述基底(3)的一侧上被附接到所述芯片载体(8),其中在所述芯片(1a)和所述基底(3)之间设置有焊料材料(2);以及
-用所述闪光灯(5)产生光脉冲(6)用于加热所述芯片(1a),其中对所述芯片(1a)进行加热使得所述芯片(1a)从所述芯片载体(8)脱离以朝向所述基底(3)非接触地转移,其中所述焊料材料(2)通过与经加热的芯片(1a)接触而至少部分地熔融,用于将所述芯片(1a)附接到所述基底(3)。
2.根据权利要求1所述的方法,其中所述光脉冲(6)的透射光(6a)继续照射所述芯片(1a),同时所述芯片(1a)在所述芯片载体(8)和所述基底(3)之间非接触地行进距离(Z)。
3.根据权利要求2所述的方法,其中根据时间对冲击所述芯片(1a)的所述光(6a)的强度(Ia)进行调节,其中所述光的强度(Ia)在所述芯片从所述芯片载体(8)脱离的时刻比所述芯片(1a)在所述芯片载体(8)和所述基底(3)之间行进的时间期间高。
4.根据权利要求3所述的方法,其中所述光脉冲(6)的所述透射光(6a)继续照射所述芯片(1a),同时所述芯片(1a)位于所述基底(3)上,并且其中所述光强度(Ia)在所述行进之后在所述芯片接触基底(3)上的所述焊料材料(2)时增加。
5.根据前述权利要求中任一项所述的方法,其中所述芯片载体(8)包括对所述光脉冲(6)透明的载体基底,其中所述芯片(1a)由透射通过所述芯片载体(8)的所述光脉冲(6)加热。
6.根据前述权利要求中任一项所述的方法,其中所述光脉冲(6)的所述光(6a)使所述芯片载体(8)和所述芯片(1a)之间的粘合材料(8a)分解,从而使所述芯片(1a)从所述芯片载体(8)脱离。
7.根据前述权利要求中任一项所述的方法,其中在距所述基底(3)的距离(Z)处将所述芯片(1a)附接到所述芯片载体(8),其中所述距离(Z)在50微米和500微米之间。
8.根据前述权利要求中任一项所述的方法,其中将包括掩蔽图案(7a,7c)的掩蔽装置(7)设置在所述闪光灯(5)和所述芯片(1a)之间,其中所述掩蔽图案(7a,7c)被配置成使所述光脉冲(6)的所述光(6a)选择性地通过到达所述芯片(1a)。
9.根据前述权利要求中任一项所述的方法,其中将多个芯片(1a,1b)同时从所述芯片载体(8)转移到所述基底(3)并且焊接到所述基底(3)。
10.根据前述权利要求中任一项所述的方法,其中一个或更多个芯片的所述转移和焊接通过单个光脉冲(6)实现。
11.根据前述权利要求中任一项所述的方法,其中
-具有不同的加热特性(C1、C2)的两个或更多个不同的芯片(1a,1b)被附接到所述芯片载体(8);并且
-在所述闪光灯(5)和所述芯片(1a,1b)之间设置掩蔽装置(7),从而通过所述掩蔽装置(7)的所述光脉冲(6)在不同区域(6a,6b)中造成不同的光强度(Ia,Ib),从而用不同的光强度(Ia,Ib)加热所述芯片(1a,1b),用于至少部分地补偿所述不同的加热特性(C1,C2),以减少由于所述光脉冲(6)的加热而导致的所述芯片之间的温度差距。
12.根据前述权利要求中任一项所述的方法,其中所述基底(3)包括卷对卷过程中的柔性箔。
13.一种用于将芯片(1a)焊接到基底(3)的设备,所述设备包括:
-基底处理器(4),其被配置成确定所述基底(3)的位置;
-载体处理器(18),其被配置成确定芯片载体(8)的位置,其中所述芯片(1a)在所述芯片载体(8)的面向所述基底(3)的一侧上附接至所述芯片载体(8);
-对准装置(12),其被配置成将附接至所述芯片载体(8)的所述芯片(1a)参考所述芯片(1a)在所述基底(3)上的目标位置(3t)对准;
-闪光灯(5),其被配置成产生用于加热所述芯片(1a)的光脉冲(6),其中对所述芯片(1a)的加热使所述芯片(1a)从所述芯片载体(8)朝向所述基底(3)脱离,并且其中在所述芯片(1a)和所述基底(3)之间的焊料材料(2)通过与经加热的芯片(1a)接触而至少部分地熔融,用于将所述芯片(1a)附接到所述基底(3)。
14.根据权利要求13所述的设备,包括掩蔽装置(7),所述掩蔽装置在使用时被设置在所述闪光灯(5)与所述芯片载体(8)之间,并且被配置成通过所述掩蔽装置(7)的所述光脉冲(6)在不同区域(6a,6b)中造成不同的光强度(Ia,Ib),以用不同的光强度(Ia,Ib)加热所述芯片载体(8)上的具有不同加热特性(C1,C2)的多个芯片(1a,1b)。
15.根据权利要求13或14所述的设备,包括焊料供应单元(9),所述焊料供应单元(9)被配置成在所述芯片(1a)被转移到所述基底(3)之前将所述焊料材料(2)施加到所述基底(3)和/或所述芯片(1a),其中所述焊料材料(2)在所述基底(3)和所述芯片(1a)之间。
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Publication number Priority date Publication date Assignee Title
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EP3276655A1 (en) * 2016-07-26 2018-01-31 Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO Method and system for bonding a chip to a substrate
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TWI774936B (zh) * 2019-03-08 2022-08-21 台灣愛司帝科技股份有限公司 承載結構及承載設備
KR102369108B1 (ko) * 2020-04-22 2022-03-02 주식회사 아큐레이저 기판에 배치된 디바이스 모듈 처리 장치
US11646293B2 (en) * 2020-07-22 2023-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and method
DE102022102364A1 (de) * 2022-02-01 2023-08-03 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Vorrichtung zum transferieren und verfahren
WO2023150363A1 (en) * 2022-02-04 2023-08-10 Abbott Diabetes Care Inc. Systems, devices, and methods for an analyte sensor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1434523A (zh) * 2002-01-23 2003-08-06 伊斯曼柯达公司 采用多路线性激光束通过热转移制造发光二极管器件
EP1455394A1 (en) * 2001-07-24 2004-09-08 Seiko Epson Corporation Transfer method, method of manufacturing thin film element, method of manufacturing integrated circuit, circuit substrate and method of manufacturing the circuit substrate, electro-optic device and method of manufacturing the electro-optic device, and ic card and electronic equipment
CN1656868A (zh) * 2002-05-24 2005-08-17 皇家飞利浦电子股份有限公司 适用于把载体支承的器件送到衬底上的所需位置的方法和为此设计的装置
US20060060979A1 (en) * 2004-09-22 2006-03-23 Frutschy Kristopher J Radiant energy heating for die attach
US20080210368A1 (en) * 2005-04-08 2008-09-04 Elke Zakel Method and Device for Transferring a Chip to a Contact Substrate

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005024908A2 (en) 2003-09-05 2005-03-17 Si2 Technologies, Inc. Laser transfer articles and method of making
JP2011216503A (ja) * 2008-08-11 2011-10-27 Yamaha Motor Co Ltd はんだ付け方法、実装基板の生産方法、およびはんだ付け装置
JP2010045287A (ja) * 2008-08-18 2010-02-25 Sony Corp 素子の移載方法
US7879691B2 (en) * 2008-09-24 2011-02-01 Eastman Kodak Company Low cost die placement
JP5444798B2 (ja) * 2009-04-10 2014-03-19 ソニー株式会社 素子の移載方法
JP6032637B2 (ja) * 2012-07-05 2016-11-30 パナソニックIpマネジメント株式会社 部品実装基板の製造システム及び製造方法
EP2747129A1 (en) 2012-12-18 2014-06-25 Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO Curing a heat-curable material in an embedded curing zone

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1455394A1 (en) * 2001-07-24 2004-09-08 Seiko Epson Corporation Transfer method, method of manufacturing thin film element, method of manufacturing integrated circuit, circuit substrate and method of manufacturing the circuit substrate, electro-optic device and method of manufacturing the electro-optic device, and ic card and electronic equipment
CN1434523A (zh) * 2002-01-23 2003-08-06 伊斯曼柯达公司 采用多路线性激光束通过热转移制造发光二极管器件
CN1656868A (zh) * 2002-05-24 2005-08-17 皇家飞利浦电子股份有限公司 适用于把载体支承的器件送到衬底上的所需位置的方法和为此设计的装置
US20060060979A1 (en) * 2004-09-22 2006-03-23 Frutschy Kristopher J Radiant energy heating for die attach
US20080210368A1 (en) * 2005-04-08 2008-09-04 Elke Zakel Method and Device for Transferring a Chip to a Contact Substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112151398A (zh) * 2019-06-26 2020-12-29 上海微电子装备(集团)股份有限公司 一种芯片封装方法
CN112151398B (zh) * 2019-06-26 2023-12-15 上海微电子装备(集团)股份有限公司 一种芯片封装方法

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WO2016175654A3 (en) 2017-01-05
US10304709B2 (en) 2019-05-28
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