CN216054715U

CN216054715U - Planar VDMOS device

Info

Publication number: CN216054715U
Application number: CN202120531039.1U
Authority: CN
Inventors: 马万里
Original assignee: Shenzhen Zhaosi Microelectronics Technology Co ltd
Current assignee: Shenzhen Zhaosi Microelectronics Technology Co ltd
Priority date: 2021-03-12
Filing date: 2021-03-12
Publication date: 2022-03-15
Anticipated expiration: 2031-03-12

Abstract

The utility model discloses a planar VDMOS device and a preparation method thereof. The planar VDMOS device comprises a substrate layer, an epitaxial layer, a patterned first gate dielectric layer, a grid, a body region, a source region, a contact body and a deep body region, wherein the epitaxial layer is stacked on the substrate layer; the upper surface of the body region is exposed from the upper surface of the epitaxial layer, the upper surface of the source region and the upper surface of the contact body are exposed from the upper surface of the body region, the contact body is arranged close to the side edge of the source region, and the deep body region is arranged below the source region and the contact body and close to the source region and the contact body. The deep body region of the planar VDMOS device is arranged below the source region and the contact body, and doping atoms in the deep body region can be obtained by diffusing the contact body with polycrystalline silicon through a thermal drive-in process, so that the limitation of injection energy and injection dosage in the manufacturing process of the deep body region is effectively avoided.

Description

Planar VDMOS device

Technical Field

The utility model relates to the technical field of semiconductors, in particular to a planar VDMOS device.

Background

A Vertical Double diffused Metal Oxide Semiconductor (VDMOS) transistor forms a channel by a difference in longitudinal Diffusion distance between source and body ion implantation. VDMOS combines the advantages of bipolar transistors and common MOS devices. Compared with a bipolar transistor, the bipolar transistor has the advantages of high switching speed, low switching loss, high input impedance and low driving power; the frequency characteristic is good, the transconductance is highly linear, and the like, and the method is widely applied to equipment such as motor speed regulation, inverters, switching power supplies and the like.

For planar VDMOS devices, there is a very important parameter, namely the single-pulse avalanche energy (E)_AS) Defined as the maximum energy that the device can dissipate in a single avalanche state. In applications where large voltage spikes are generated at the source and drain, the avalanche energy of the device must be considered. E_ASCapability is also an important criterion for measuring the performance of VDMOS devices.

The conventional VDMOS device comprises an epitaxial layer, and a source region and a body region which are prepared on the epitaxial layer, wherein the epitaxial layer, the source region and the body region can be intrinsically equivalent to a triode, namely a parasitic triode. When the planar VDMOS device is turned off, a reverse current between the source and the drain flows through the body region to generate a voltage drop, if the voltage drop is larger than the turn-on voltage of the parasitic triode, the parasitic triode is conducted by the reverse current due to the amplification effect of the triode to cause runaway, and at the moment, the grid voltage cannot turn off the VDMOS device, so that the VDMOS device is caused to have E_ASAnd (4) failing. It is necessary in principle to prevent the parasitic transistor from conducting in order to prevent the device from failing.

In the conventional technology, the doping concentration of the deep body region can be generally increased, or the short-circuit area of the source region and the body region can be increased, so that the body region resistance is reduced, and the parasitic triode is prevented from being conducted. However, the deep body region is usually formed by gate self-aligned implantation, and the dose is difficult to make large; if the implantation dosage is to be increased, the deep body region is closer to the channel region, so that the device in the adjacent region is affected during the implantation process, and the device is degraded.

SUMMERY OF THE UTILITY MODEL

In view of the above, it is desirable to provide a planar VDMOS device capable of effectively increasing the deep body implant dose while leaving the adjacent regions unaffected.

According to one embodiment of the utility model, a planar VDMOS device comprises a substrate, an epitaxial layer, a first gate dielectric layer, a gate electrode, a body region, a source region, a contact body and a deep body region;

the epitaxial layer is arranged on the substrate in a stacked mode, the first gate dielectric separates the epitaxial layer and the gate, the body region is arranged in the epitaxial layer, and the source region, the deep body region and the contact body are all arranged in the body region;

wherein the upper surface of the body region is exposed from the epitaxial layer, the source region and the contact body are exposed from the body region, the contact body is arranged in contact with the side edge of the source region, and the deep body region is arranged below the source region and the contact body, wraps the contact body and is in contact with the contact region and the source region;

the doping type in the source region is a first doping type, the contact is a polysilicon contact and the doping type of the contact is a second doping type different from the first doping type, the doping types of the body region and the deep body region are both the first doping type and the second doping type, and in one embodiment, the depth of embedding the contact into the body region is larger than the depth of embedding the source region into the body region.

In one embodiment, the contact is embedded into the body region to a depth of 2-3 μm.

In one embodiment, the thickness of the body region is d, and the contact is embedded in the body region to a depth of 80% d or less.

In one embodiment, the thickness of the first gate dielectric layer is

In one embodiment, the semiconductor device further comprises a first metal layer and a second gate dielectric layer wrapping the gate electrode, the first metal layer entirely covers the second gate dielectric layer, the source region and the contact, and the first metal layer contacts the source region and the contact.

In one embodiment, the semiconductor device further comprises a second metal layer, the second metal layer is arranged on one side surface of the substrate layer far away from the epitaxial layer, and the doping concentration in the contact body is lower than that in the source region.

In one embodiment, the doping concentration in the contact is lower than the doping concentration in the source region.

In one embodiment, the gate is a polysilicon gate.

In one embodiment, the gate has a thickness of

In the structure of the planar VDMOS device of the above embodiment, a polysilicon contact is included which is disposed at the side of the source region. The polycrystalline silicon contact body with the second doping type is exposed on the surface of the body region and can be directly contacted with a metal electrode arranged on the body region, and the polycrystalline silicon contact body can be regarded as an integral resistor; the whole body is not only contacted with the upper surface of the source region, but also contacted with the side surface of the source region, so that the short circuit area between the source region and the body region is greatly increased, and the E of the device_ASThe capability is greatly improved. Furthermore, the deep body region is arranged below the source region and the contact body, and doping atoms in the deep body region can be obtained by diffusing polycrystalline silicon with a second doping type through a thermal drive-in process, so that the limitation of injection energy and injection dosage in the manufacturing process of the deep body region is effectively avoided. Additionally, the deep body region in the device can be prepared by diffusing the polysilicon with the second doping type through a thermal drive-in process without needing additional preparation steps as in the traditional process, so that the generation rate can be effectively reducedThe production cost.

Drawings

Fig. 1 illustrates a structure of a planar VDMOS device according to an embodiment;

fig. 2 is a schematic diagram of a process for fabricating a planar VDMOS device;

fig. 3 is a top view of the device in step S3 shown in fig. 2;

wherein, each reference number and description are as follows:

10. planar VDMOS devices; 101. a first metal layer; 102. a second metal layer; 110. a substrate layer; 120. an epitaxial layer; 130. a first gate dielectric layer; 140. a gate electrode; 150. a second gate dielectric layer; 160. A body region; 170. a source region; 180. a contact body; 190. a deep body region; 210. a source region photoresist; 220. a contact photoresist.

Detailed Description

To facilitate an understanding of the utility model, the utility model will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the utility model herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. As used herein, "plurality" includes two and more than two items. As used herein, "above a certain number" should be understood to mean a certain number and a range greater than a certain number.

the source region, the contact body, the body region and the deep body region are all doped semiconductors; the doping type in the source region is a first doping type, the contact body is a polycrystalline silicon contact body, the doping type of the contact body is a second doping type different from the first doping type, the doping types of the body region and the deep body region are both the second doping type, and the doping concentrations of the contact body and the deep body region are both higher than those of the body region.

Referring to fig. 1, a structure of a planar VDMOS device 10 according to the above embodiment is shown. The planar VDMOS device 10 includes a substrate layer 110, an epitaxial layer 120, a first gate dielectric layer 130, a gate 140, a body region 160 disposed in the epitaxial layer 120, a source region 170 disposed in the body region 160, a contact 180, and a deep body region 190. The epitaxial layer 120 is disposed on the substrate layer 110, the first gate dielectric layer 130 is disposed on the epitaxial layer 120 in a patterned manner, and the gate 140 is disposed on the first gate dielectric layer 130. Where "upper" is a relative orientation used for convenience in the description herein and does not represent an absolute position of each component in the device, it corresponds to the orientation shown in fig. 1. The "patterned first gate dielectric layers 130" have a space between the first gate dielectric layers 130, for example, to expose a portion of the epitaxial layer 120.

The body region 160 is disposed at an upper end of the epitaxial layer 120, and specifically, an upper surface of the body region 160 is exposed from an upper surface of the epitaxial layer 120; source region 170 is disposed at an upper end of body region 160, and specifically, an upper surface of source region 170 is exposed from an upper surface of body region 160. The upper surface of contact 180 is also exposed from the upper surface of body region 160, contact 180 is disposed immediately to the side of source region 170, and deep body region 190 is disposed below source region 170 and contact 180 and immediately adjacent to source region 170 and contact 180.

More specifically, the doping type of the source region 170 is a first doping type, the contact 180 is a polysilicon contact 180 and the doping type thereof is a second doping type, the doping types of the body region 160 and the deep body region 190 are both the second doping type, and the doping concentration in the deep body region 190 is higher than that of the body region 160.

It can be understood that the doping types of the semiconductor are generally divided into N-type doping and P-type doping, and when the first doping type is N-type doping, the second doping type is P-type doping; if the first doping type is P-type doping, the second doping type is N-type doping. In one specific example, the first doping type is N-type doping and the second doping type is P-type doping. In the following embodiments herein, for convenience of understanding, the description is made directly with "N-type doping" and "P-type doping".

More specifically, in this embodiment, substrate layer 110 is doped N-type, and epitaxial layer 120 is doped N-type; source region 170 is heavily doped N-type, body region 160 is heavily doped P-type, and deep body region 190 is heavily doped P-type. It is understood that "heavily doped" is a relative concept. For example, the source region 170 has a higher N-type doping concentration than the epitaxial layer 120, and is an N-type heavily doped region, which is denoted as an "N + source region 170"; the deep body region 190 has a higher P-type doping concentration than the body region 160, is P-type heavily doped, and is denoted as "P + deep body region 190", and the body region 160 is denoted as "P-body region 160".

In one specific example, as shown in fig. 1, two spaced apart source regions 170 are disposed at the upper end of body region 160, and contact 180 is disposed between the two source regions 170 and abuts against the two source regions 170. It will be appreciated that, based on the general structural arrangement of a VDMOS device, the epitaxial layer 120 is disposed outside one body region 160, and there is also a space between the boundary of the body region 160 and the boundary of the source region 170. The first gate dielectric layer 130 and the gate electrode 140 are disposed on the epitaxial layer 120 between two adjacent body regions 160 and extend to cover the nearest source region 170.

In the structure of planar VDMOS device 10 of the above embodiment, polysilicon contacts 180 are included that are disposed to the sides of source regions 170. The polysilicon contact 180 having the second doping type is exposed on the surface of the body region 160, and can directly contact with a metal electrode subsequently disposed thereon, which can be regarded as an overall resistor; the whole body is not only contacted with the upper surface of the source region 170, but also contacted with the side surface of the source region 170, so that the short circuit area between the source region 170 and the body region 160 is greatly increased, and the EAS capability of the device is greatly improved. Further, the deep body region 190 is disposed below the source region 170 and the contact body 180, and the doping atoms therein can be obtained by diffusing the polysilicon with the second doping type through a thermal drive-in process, so as to effectively avoid the limitation of implantation energy and implantation dose in the manufacturing process of the deep body region 190. Additionally, the deep body region 190 in the device can be made of polysilicon with the second doping type by diffusion through a thermal drive-in process, without requiring additional preparation steps as in the conventional process, thereby effectively reducing the production cost.

In one particular example, contact 180 is embedded into body region 160 to a depth greater than the depth of source region 170 embedded into body region 160. The depth to which contact 180 is embedded in body region 160 is set to be greater than the depth to which source region 170 is embedded in body region 160, on the one hand, so that the area of contact 180 contacting the side of source region 170 is made larger to further improve the EAS capability of the device. On the other hand, the contact area between the contact body 180 and the body region 160 can be made larger, so that the diffusion speed and efficiency of the doping atoms to the body region 160 in the actual manufacturing process can be significantly improved, and the uniformity of the distribution of the doping atoms in the formed deep body region 190 can be improved.

In one particular example, contact 180 is embedded in body region 160 to a depth of 2 μm to 3 μm.

In one specific example, the body region 160 has a thickness d, and the contact 180 is embedded in the body region 160 to a depth ≦ 80% d. Contact 180 has P-type dopant atoms, and the implantation of deep body region 190 depends on the thermal drive-in of the dopant atoms in contact 180 during the actual fabrication process, which may cause the P-type dopant atoms in contact 180 to diffuse into N-type epitaxial layer 120 if contact 180 is embedded too deeply, thereby affecting the normal operation of epitaxial layer 120. Therefore, the depth of embedding the contact body 180 is limited to be less than or equal to 80% d, which is beneficial to further ensure that the overall quality of the device is not significantly affected.

Further, the depth of embedding the contact 180 into the body region 160 is 50% d to 80% d. Optionally, the depth to which contact 180 is embedded in body region 160 is 50% d, 60% d, or 70% d.

In one specific example, the first gate dielectric layer 130 is disposed not only on the surface of the epitaxial layer 120 between adjacent body regions 160, but also in contact with the upper surfaces of the body regions 160 and the upper surfaces of the source regions 170. It is understood that the patterned first gate dielectric layer 130 should also expose a portion of the source region 170 so that the source region 170 can contact a subsequently disposed metal electrode.

In one specific example, the semiconductor device further includes a first metal layer 101 and a second gate dielectric layer 150 wrapping the gate 140, and the first metal layer 101 entirely covers the second gate dielectric layer 150, the source region 170 and the contact 180. It is understood that the first metal layer 101 is insulated from the gate electrode 140 due to the presence of the second gate dielectric layer 150. First metal layer 101 covers contact 180, and first metal layer 101 and contact 180 as a whole can be considered as one resistor. First metal layer 101 covers source region 170 and may serve as a source contact.

In one specific example, the device further comprises a second metal layer 102, and the second metal layer 102 is disposed on a side surface of the substrate layer 110 away from the epitaxial layer 120.

Further, the doping concentration in contact 180 is lower than the doping concentration in source region 170 to prevent the P-type doping material in contact 180 from significantly affecting the N-type doping state in source region 170 during subsequent thermal drive-in.

In one specific example, the material of the N-type epitaxial layer 120 is selected from N-type doped monocrystalline silicon.

In one specific example, the first gate dielectric layer 130 has a thickness of

For example, the thickness of the first gate dielectric layer 130 is

And the like. The thickness of the first gate dielectric layer 130 is not too thin, otherwise, the gate 140 may be shorted with the source region 170 or the body region 160; the thickness of the first gate dielectric layer 130 should not be too thick, otherwise, the gate 140 may not control the on/off of the VDMOS device.

In one specific example, the gate 140 is selected from a polysilicon gate 140.

In one specific example, the gate 140 has a thickness of

For example, the gate 140 has a thickness of

And the like.

In one specific example, the doping element of the body region 160 includes B. The body region 160 may be formed at the upper end of the epitaxial layer 120 through B doping.

In one specific example, the doping element of the source region 170 is selected from As or P, and the source region 170 may be formed at the upper end of the body region 160 by doping with As or P.

In one particular example, the polysilicon contact 180 is a P-type polysilicon contact 180.

Further, an embodiment of the present invention further provides a method for manufacturing a planar VDMOS device, which includes the following steps:

preparing a patterned first gate dielectric layer and a gate on an epitaxial layer arranged on a substrate layer, wherein the gate is formed on the first gate dielectric layer;

carrying out body region injection and thermal drive-in treatment on the epitaxial layer between the first gate dielectric layers, and forming a body region with a second doping type in the epitaxial layer;

forming source region photoresist exposing a source region area on the surface of the body region, performing source region injection on the source region area on the surface of the body region, removing the source region photoresist, and performing thermal drive-in treatment to prepare a source region;

preparing contact body photoresist exposing the contact body region, etching the contact body region on the surface of the body region to form a contact body groove, removing the contact body photoresist, depositing polycrystalline silicon with the doping type being the second doping type in the contact body groove, and preparing a contact body;

and heating the contact body to diffuse the doping impurities in the contact body into the body region.

Further, please refer to fig. 2, which shows a schematic diagram of an actual operation process of one embodiment of the above-mentioned preparation method.

Step S1, a patterned first gate dielectric layer and a gate electrode are prepared on the epitaxial layer disposed on the substrate layer, and the gate electrode is formed on the first gate dielectric layer. The substrate layer is an N-type substrate layer, and the epitaxial layer is an N-type epitaxial layer.

Specifically, the first gate dielectric layer may be formed on the upper surface of the N-type epitaxial layer by a thermal oxidation process. The thickness of the first gate dielectric layer can be controlled according to parameters such as actual oxidation time and the like, and is determined according to the design of the device.

After the first gate dielectric layer is formed, a layer of in-situ doped N-type polycrystalline silicon is deposited on the surface of the first gate dielectric layer to be used as a gate. And then, photoetching and etching the polycrystalline silicon, removing the first gate dielectric layer and the gate material on the partial region of the surface of the epitaxial layer, and exposing the surface of the epitaxial layer of the region, namely the patterned first gate dielectric layer and the gate arranged on the first gate dielectric layer.

Specifically, on the upper surface of the device, the first gate dielectric layers are distributed in a plurality of spaced shapes, and the exposed epitaxial layer surface is arranged between the adjacent first gate dielectric layers.

Step S2, performing body region implantation and thermal drive-in processing on the epitaxial layer between the first gate dielectric layers, and forming a P-type doped body region in the epitaxial layer.

The doping element may be implanted through the window between the gates. In one of themIn an example, the implantation energy is 50keV to 130keV and the implantation dose is 1 × 10 during the body implantation process¹³Per cm²～9×10¹³Per cm²。

The dopant species implanted into the epitaxial layer is usually concentrated in a certain location and therefore usually needs to be further diffused to form the desired body region. The process for promoting the diffusion of the doping element can be selected from thermal drive-in treatment, and the drive-in temperature is 1000-1200 ℃ in the process of carrying out body-area thermal drive-in treatment. It will be appreciated that the length of time for the heat drive in may be designed by the operator.

In particular, the implanted element is selected from B, which is capable of forming a P-body region by thermal diffusion.

After the body region is formed, source region injection and thermal drive-in treatment are carried out on a source region on the surface of the body region, and a source region is prepared. The steps can be divided into steps S3 and S4.

Step S3, a source region photoresist 210 exposing the source region is formed on the surface of the body region, and then source region implantation is performed on the unshielded portion of the source region photoresist 210.

In step S4, a thermal drive-in process is performed after the source region photoresist 210 is removed to prepare a source region.

To facilitate understanding of the overall structure of the device, a top view of the device after forming the source region photoresist 210 is shown in fig. 3.

The doping element can be implanted through the region uncovered by the photoresist in the source region, in one specific example, the implantation energy is 30 keV-100 keV and the implantation dosage is 5 × 10 keV during the process of performing the source region implantation¹⁵Per cm²～1×10¹⁶Per cm²。

Further, specifically, the doping element may be selected from As or P.

The dopant implanted into the epitaxial layer is usually concentrated in a certain location and therefore usually needs to be further diffused to form the desired source region. The process for promoting the diffusion of the doping element can be selected from thermal drive-in treatment, and the drive-in temperature is 850-1000 ℃ in the process of carrying out the thermal drive-in treatment of the source region. It will be appreciated that the length of time for the heat drive in may be designed by the operator.

Preparing contact body photoresist exposing the contact body region, etching the contact body region on the surface of the body region to form a contact body groove, removing the contact body photoresist, depositing polycrystalline silicon with the doping type being the second doping type in the contact body groove, and preparing the contact body. The process can be divided into steps S5 to S7.

Specifically, in step S5, contact photoresist 220 exposing the contact region is prepared.

In one specific example, the pattern of contact photoresist 220 is the inverse of the pattern of source region photoresist 210. In an actual operation process, the contact photoresist 220 and the source region photoresist 210 may be prepared by using the same mask plate, and only one of the photoresists needs to be exposed by using a negative photoresist process, for example, the contact photoresist 220 is exposed by using the negative photoresist process to form a pattern opposite to that of the source region photoresist 210.

In step S6, after forming contact photoresist, the regions not covered by the contact photoresist 220 are etched to form contact trenches. In one specific example, the depth of the contact trench is 2 μm to 3 μm. Further, the depth of the contact trench does not exceed 80% of the body region thickness, preventing the subsequent thermal drive-in process of the contact material from having a significant impact on the body region.

And step S7, removing the contact photoresist, and depositing in-situ doped P-type polycrystalline silicon on the surface to prepare a contact. Furthermore, the doping concentration in the contact body is lower than that in the source region, so that the influence of P-type impurities on the source region in a subsequent thermal process is prevented.

Further, in one specific example, after the in-situ doped P-type polysilicon is deposited, an etching back step is further included to remove the excess P-type polysilicon formed on the surface of the source region.

In step S8, the contact body is heated to diffuse the dopant element in the contact body into the body region.

After the doping elements in the contact body diffuse into the body region, the number of doping atoms in the original body region can be increased, so that the doping concentration in the part of the body region is improved, and a deep body region is formed. Since the deep body region is formed by diffusion of the doping element in the contact, it is apparent that the deep body region is located below the contact and the source region.

In one specific example, in the process of heating the contact body, the heating temperature is 750-900 ℃, and the heating time is 25-45 min.

Step S9, a second gate dielectric layer, a first metal layer and a second metal layer are prepared.

Specifically, the second gate dielectric layer covers the surface of the gate, the first metal layer entirely covers the second gate dielectric layer, the source region and the contact body, and the second metal layer is formed on the surface of one side, far away from the epitaxial layer, of the substrate layer.

In the preparation process, the deep body region of the device is formed by polycrystalline thermal diffusion in the groove, and the deep body region does not need to be independently made, so that the production steps can be saved, and the production cost can be effectively reduced. More importantly, by adopting the preparation method, the deep body region is formed by implantation directly between the gate windows without the limitation of implantation energy and implantation dosage.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the utility model. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A planar VDMOS device is characterized by comprising a substrate, an epitaxial layer, a first gate dielectric layer, a grid electrode, a body region, a source region, a contact body and a deep body region;

wherein the upper surface of the body region is exposed from the epitaxial layer, the source region and the contact are exposed from the body region, the contact is arranged in contact with the side edge of the source region, and the deep body region is arranged below the source region and the contact, wraps the contact and is in contact with the contact and the source region;

the source region, the contact body, the body region and the deep body region are all doped semiconductors, the doping type in the source region is a first doping type, the contact body is a polycrystalline silicon contact body, the doping type of the contact body is a second doping type different from the first doping type, the doping types of the body region and the deep body region are both second doping types, and the doping concentrations of the contact body and the deep body region are higher than that of the body region.

2. The planar VDMOS device of claim 1, wherein the depth to which the contact is embedded in the body region is greater than the depth to which the source region is embedded in the body region.

3. The planar VDMOS device of claim 2, wherein the contact is embedded in the body region to a depth of 2 μ ι η to 3 μ ι η.

4. The planar VDMOS device of claim 2, wherein the body region has a thickness d, and wherein the contact is embedded in the body region to a depth d of 80% or less.

5. The planar VDMOS device of claim 4, wherein the first gate dielectric layer has a thickness of

6. The planar VDMOS device of claim 5, further comprising a first metal layer and a second gate dielectric layer encasing the gate, wherein the first metal layer entirely covers the second gate dielectric layer, the source region, and the contact, and wherein the first metal layer contacts the source region and the contact.

7. The planar VDMOS device of any one of claims 1 to 4, further comprising a second metal layer disposed on a surface of the substrate on a side away from the epitaxial layer, wherein a doping concentration in the contact is lower than a doping concentration in the source region.

8. The planar VDMOS device of any one of claims 1 to 4, wherein a doping concentration in the contact is lower than a doping concentration in the source region.

9. The planar VDMOS device of any one of claims 1 to 4, wherein the gate is a polysilicon gate.

10. The planar VDMOS device of any one of claims 1 to 4, wherein the gate has a thickness of