CN107636813B - 具有高密度管芯至管芯连接的半导体封装及其制造方法 - Google Patents

具有高密度管芯至管芯连接的半导体封装及其制造方法 Download PDF

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CN107636813B
CN107636813B CN201680025551.0A CN201680025551A CN107636813B CN 107636813 B CN107636813 B CN 107636813B CN 201680025551 A CN201680025551 A CN 201680025551A CN 107636813 B CN107636813 B CN 107636813B
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layer
die
dielectric layer
package
bridge
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CN107636813A (zh
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H·B·蔚
D·W·金
J·S·李
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Qualcomm Inc
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Qualcomm Inc
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Abstract

根据本公开的一些示例的半导体封装可包括：具有嵌入在基板中的桥的基板、耦合至该基板的第一管芯和第二管芯、以及基板中的将桥耦合至第一管芯和第二管芯的多个导电桥互连。该多个导电桥互连可具有：直接耦合至该桥的第一桥接触层、在第一桥接触层上的第一焊料层、在第一焊料层上的第二桥接触层、在第二桥接触层上的第二焊料层、以及直接耦合至第一管芯和第二管芯中的一者的管芯接触层，其中该多个导电桥互连被嵌入在基板中。

Description

具有高密度管芯至管芯连接的半导体封装及其制造方法
相关申请的交叉引用
本专利申请要求于2015年5月4日提交的题为“SEMICONDUCTOR PACKAGE WITHHIGH DENSITY DIE TO DIE CONNECTION AND METHOD OF MAKING THE SAME(具有高密度管芯至管芯连接的半导体封装及其制造方法)”的美国临时申请No.62/156,857的权益，该临时申请已被转让给本申请受让人并由此通过援引明确地整体纳入于此。
公开领域
本公开一般涉及具有管芯至管芯连接的半导体封装，并且尤其但不排他地涉及具有高密度管芯至管芯连接的半导体封装。
背景
半导体封装中的高密度管芯至管芯连接难以制造为了制造具有高密度管芯至管芯连接的半导体封装，必须克服许多技术障碍以创建精细的线路/间隔(L/S)。一般而言，常规的制造技术要求生成半导体封装中的额外层或者生成中介体以制造高密度管芯至管芯连接。该额外层或中介体的使用增大了在常规半导体封装上进行制造的难度和成本，并且导致并不理想地适用于一些应用的具有大轮廓的封装。
概述
以下给出了与本文所公开的各装置和方法相关联的一个或多个方面和/或示例相关的简化概述。如此，以下概述既不应被视为与所有构想的方面和/或示例相关的详尽纵览，以下概述也不应被认为标识与所有构想的方面和/或示例相关的关键性或决定性要素或描绘与任何特定方面和/或示例相关联的范围。相应地，以下概述仅具有在以下给出的详细描述之前以简化形式呈现与关于本文所公开的装置和方法的一个或多个方面和/或示例相关的某些概念的目的。
在一个方面，一种半导体封装包括：具有第一多个通孔的基板；嵌入在该基板中的桥；耦合至该基板的第一管芯；耦合至该基板且与该第一管芯水平间隔开的第二管芯；以及至少部分地在该基板中的多个导电桥互连，其配置成将桥耦合至第一管芯和第二管芯。
在另一方面，一种层叠封装半导体封装包括：具有第三管芯的第一封装；以及附连至第一封装的第二封装。该第二封装包括：具有第一多个通孔的基板；嵌入在该基板中的桥；耦合至该基板的第一管芯；耦合至该基板且与该第一管芯水平间隔开的第二管芯；以及至少部分地在该基板中的多个导电桥互连，其配置成将桥耦合至第一管芯和第二管芯。
在又一方面，一种用于形成半导体封装的方法包括：将晶种层施加于载体；在该晶种层上形成第一路由层，该第一路由层具有第一桥接触层；将桥耦合至该第一桥接触层；在该晶种层上形成第一电介质层；移除该载体和晶种层；在该第一桥接触层上形成第一焊料层；在第一焊料层上形成第二桥接触层；该第一电介质层至少部分地封装第一桥接触层、第一焊料层、以及第二桥接触层；在该第二桥接触层和第一路由层上形成第二焊料层；在该第二焊料层上形成第一管芯接触层；将第一管芯耦合至该第一管芯接触层；以及将邻近第一管芯且与该第一管芯水平间隔开的第二管芯耦合至第一管芯接触层。
在又一方面，一种用于形成半导体封装的方法包括：将晶种层施加于载体；在该晶种层上形成第一路由层，该第一路由层具有第一桥接触层；将桥耦合至该第一桥接触层；在该晶种层上形成第一电介质层；移除该载体和晶种层；在该第一桥接触层上形成第一焊料层；在该第一焊料层上形成第二桥接触层；该第一电介质层至少部分地封装第一桥接触层、第一焊料层、以及第二桥接触层；在该第二桥接触层和第一路由层上形成第二焊料层；在该第二焊料层上形成第一管芯接触层；将第一管芯耦合至该第一管芯接触层；以及将邻近第一管芯且与该第一管芯水平间隔开的第二管芯耦合至第一管芯接触层。
基于附图和详细描述，与本文公开的各装置和方法相关联的其它特征和优点对本领域技术人员而言将是明了的。
附图简要说明
对本公开的各方面及其许多伴随优点的更完整领会将因其在参考结合附图考虑的以下详细描述时变得更好理解而易于获得，附图仅出于解说目的被给出而不对本公开构成任何限定，并且其中：
图1A解说了根据本公开的一些示例的半导体封装的部分分解的侧视图。
图1B解说了根据本公开的一些示例的具有两个并排管芯的半导体封装的侧视图。
图2A-2T解说了根据本公开的一些示例的用于半导体封装的制造的示例性部分过程流。
图3解说了根据本公开的一些示例的用于形成半导体封装的示例性部分过程流。
图4是根据本公开的一些示例的包括半导体封装的无线设备的示例性框图。
根据惯例，附图所描绘的特征可能并非按比例绘制。相应地，为了清晰起见，所描绘的特征的尺寸可能被任意放大或缩小。根据惯例，为了清晰起见，某些附图被简化。由此，附图可能未绘制特定装置或方法的所有组件。此外，类似附图标记贯穿说明书和附图标示类似特征。
详细描述
本文所公开的示例性方法、装置和***有利地解决了业界需求以及其他先前未标识出的需求，并且缓解了常规方法、装置和***的不足。例如，可使用嵌入式迹线基板(ETS)工艺以及用于管芯至管芯连接的预制桥来制造较低成本的半导体封装。该桥为逻辑信号提供了电通路，并且还可以在两个管芯之间提供功率信号，因此管芯可使用由该桥提供的电通路而不是其他潜在更长的通路来将信号从一个管芯路由至另一管芯。这将由于已经具有精细线路设计的桥而使精细线路工艺最小化，所以可以使用较便宜、较不复杂的光刻工艺。这还将使得管芯至管芯连接更加容易并且消除制造过程期间的桥位置误差。另外，薄的封装轮廓(诸如移动应用所期望的封装轮廓)可通过避免使用中介体和附加的基板来达成。本文中所公开的诸示例在为管芯至管芯连接提供电通路的ETS内部提供了高密度的桥，提供了允许安全的位置准确性的经焊料连接的桥，以及提供了用于管芯至管芯连接的常规工艺的使用。
图1A解说了根据本公开的一些示例的半导体封装的部分分解的侧视图。如图1A中示出的，半导体封装100可包括基板166(例如，电介质、硅、氧化硅、氧化铝、蓝宝石、锗、砷化镓、硅和锗的合金、或磷化铟基板)、嵌入在基板166中的桥116、耦合至基板166的第一管芯152、邻近第一管芯152且与该第一管芯152水平间隔开的耦合至基板166的第二管芯154、至少部分地在基板166中的耦合至第一管芯152和第二管芯154的多个管芯互连168、以及至少部分地在基板166中的耦合至桥116、第一管芯152和第二管芯154的多个导电桥互连167。桥116可以是硅或有机的，且具有用于管芯至管芯连接的精细图案设计。桥116可具有亚微米设计能力(硅)或具有最小2um的精细图案设计能力(有机的)。基板166可包括第一电介质层122、在第一电介质层122下方的第二电介质层130、在第二电介质层下方在半导体封装100的底部的第三电介质层138、以及在第一电介质层122上方在半导体封装100的顶部的第四电介质层146。
第三电介质层138可包括：邻近第二电介质层130的嵌入在第三电介质层138中的第三路由层136和从第三电介质层138延伸至第三路由层136的第一焊点图案140。第二电介质层130可包括：邻近第一电介质层122的嵌入在第二电介质层130中的第二路由层128和从第三路由层136穿过第二电介质层130延伸至第二路由层128的第二多个通孔134。第一电介质层122可包括：嵌入在第一电介质层122中的桥116、邻近第四电介质层146的嵌入在第一电介质层122中的第一路由层110、以及从第二路由层128穿过第一电介质层122延伸至第一路由层110的第一多个通孔126。第四电介质层146可包括：从第一路由层110穿过第四电介质层146延伸至半导体封装100的第一表面的第二焊点图案148、具有嵌入在其中的第一管芯152和第二管芯154的第一底部填料层156。
图1A包括多个导电桥互连167的第一部分分解图170和多个管芯互连168的第二部分分解图172。如在第一部分分解图170中所见的，多个导电桥互连167将桥116耦合至第二管芯154并且可包括直接耦合至桥116的第一桥接触层112、第一桥接触层112上的第一焊料层142、第一焊料层142上的第二桥接触层144、第二桥接触层144上的第二焊料层143、以及直接耦合至第二管芯154的第一管芯接触层145。第一桥接触层112、第一焊料层142、以及第二桥接触层144可被嵌入在第一电介质层122中。第二焊料层143和第一管芯接触层145可被嵌入在第四电介质层146中。
如在第二部分分解图172中所见的，多个管芯互连168将第二管芯154耦合至第一多个通孔126并且可包括直接耦合至第一多个通孔126的第一路由层110、第一路由层110上的第三焊料层198、以及直接耦合至第二管芯154的第二管芯接触层199。第一多个通孔126和第一路由层110可被嵌入在第一电介质层122中。第三焊料层198和第二管芯接触层199可被嵌入在第四电介质层146中。
图1B解说了根据本公开的一些示例的具有两个并排管芯的自立半导体封装的侧视图。如图1B中示出的，半导体封装100可包括基板166(例如，电介质、硅、氧化硅、氧化铝、蓝宝石、锗、砷化镓、硅和锗的合金、或磷化铟基板)、嵌入在基板166中的桥116、耦合至基板166的第一管芯152、邻近第一管芯152且与该第一管芯152水平间隔开的耦合至基板166的第二管芯154、至少部分地在基板166中的耦合至第一管芯152和第二管芯154的多个管芯互连(例如，图1A的管芯互连168)、以及至少部分地在基板166中的耦合至桥116、第一管芯152、和第二管芯154的多个导电桥互连(例如，图1A的桥互连167)。基板166可包括第一电介质层122、在第一电介质层122下方的第二电介质层130、在第二电介质层下方在半导体封装100的底部的第三电介质层138、在第一电介质层122上方的封装第一管芯152和第二管芯154的模塑复合物147、以及在半导体封装100的底部上的用于外部连接的多个焊球135。
第三电介质层138可包括：邻近第二电介质层130的嵌入在第三电介质层138中的第三路由层136和从第三电介质层138延伸至第三路由层136的第一焊点图案140。第二电介质层130可包括：邻近第一电介质层122的嵌入在第二电介质层130中的第二路由层128和从第三路由层136穿过第二电介质层130延伸至第二路由层128的第二多个通孔134。第一电介质层122可包括：嵌入在第一电介质层122中的桥116、邻近模塑复合物147的嵌入在第一电介质层122中的第一路由层110、以及从第二路由层128穿过第一电介质层122延伸至第一路由层(例如，图1A的第一路由层110)的第一多个通孔126。多个焊球可被耦合至第三路由层136和第一焊点图案140。
图2A-2T解说了根据本公开的一些示例的用于半导体封装100的制造的示例性部分过程流。如图2A中示出的，该部分过程开始于将铜晶种层102施加于载体104(例如，铜载体)。在图2B中，该过程通过在铜晶种层102上施加光致抗蚀剂层106来继续。在图2C中，应用光刻工艺以在光致抗蚀剂层106中形成第一路由层图案108。在图2D中，应用铜镀敷工艺以在第一路由层图案108中形成第一路由层110。在图2E中，光致抗蚀剂层106被剥离掉，从而暴露包括第一桥接触层112的第一路由层110。
在图2F中，该过程通过在第一桥接触层112上施加非导电膏层114来继续以在第一桥接触层112上附连管芯(参见以下)。在图2G中，该过程通过在非导电膏层114上将桥116耦合至第一桥接触层112来继续以将管芯与第一桥接触层112上的铜凸块接合。桥116可以是硅或有机的，且具有用于管芯至管芯连接的精细图案设计。桥116可具有亚微米设计能力(硅)或具有最小2um的精细图案设计能力(有机的)。在图2H中，该过程通过应用第一层压层118和第二层压层120来继续。如图2I中示出的，第一层压层118和第二层压层120形成第一电介质层122。
在图2J中，该过程通过将第一通孔图案124蚀刻至桥116的任一侧并且穿过第一电介质层122延伸至第一路由层110来继续。在图2K中，该过程通过在第一通孔图案124中应用铜以在第一电介质层122上除了第二路由层128之外还形成第一多个通孔126来继续。在图2L中，第二电介质层130被形成在第一电介质层122上，并且应用选择性蚀刻过程以形成第二通孔图案132。在图2M中，该过程通过在第二通孔图案132中应用铜以在第二电介质层130上除了第三路由层136之外还形成第二多个通孔134来继续。
该过程在图2N中通过在第二电介质层130上应用第三电介质层138并且将第一焊点图案140穿过第三电介质层138蚀刻至第三路由层136来继续。图2O示出了被重新取向的半导体封装100，但是应当理解，这仅仅出于解说性目的并且对于制造过程的剩余部分而言半导体封装100可保持在初始取向上在图2O中，该过程通过移除铜载体104以及铜晶种层102来继续。该过程通过在第一桥接触层112上应用第一焊料层142，然后在第一焊料层142上应用第二桥接触层144来继续。
在图2P中，该过程通过在第一电介质层122上应用第四电介质层146并且蚀刻第四电介质层146以在第二桥接触层144上形成第二焊点图案148和空的中心区域150来继续。在图2Q中，该过程通过在第二桥接触层144上形成第二焊料层143以及在中心区域150中形成第一路由层110的一部分，然后形成第一管芯接触层145来继续。该过程通过将第一管芯152耦合至第一管芯接触层145的一部分以及将邻近第一管芯152并且与第一管芯152水平间隔开的第二管芯154耦合至第一管芯接触层145的另一部分，然后应用第一底部填料层156来继续。
在图2R中，该过程通过附连具有第三半导体管芯159(其可以是存储器、半导体管芯、或集成逻辑芯片)并且使用形成在第二焊点图案148中的第二多个焊点160来耦合至第一路由层110的第一封装158来继续，其中第二焊点图案148将第一封装158电耦合至第一路由层110。在图2S中，该过程通过在第一封装158与第四电介质层146之间应用第二底部填料层162来继续。在图2T中，该部分过程通过在将第三路由层136电耦合至第一多个焊点164的第一焊点图案140中形成第一多个焊点164来结束。
应当理解，尽管以上描述提及了硅桥、铜镀敷、以及铅焊料材料，但是替代材料可被用于代替这些材料。替代材料可包括以上材料的合金或呈现与以上材料类似性质的材料。
现在参照图3，描绘了用于形成半导体封装的部分过程流。如图3中示出的，该部分过程流在300处开始于将晶种层(例如，铜晶种层)施加于载体(例如，铜载体)。在302中，该过程通过在晶种层上形成第一路由层来继续，并且该第一路由层具有第一桥接触层。在304中，桥被耦合至第一桥接触层。在306中，该过程通过在晶种层上形成第一电介质层来继续。接下来在308中，该过程通过移除载体和晶种层来继续。随后在310中，该过程通过在第一桥接触层上形成第一焊料层来继续。在312中，该过程通过在第一焊料层上形成第二桥接触层来继续，该第一电介质层至少部分地封装第一桥接触层、第一焊料层、以及第二桥接触层。接下来在314中，该过程通过在第二桥接触层和第一路由层上形成第二焊料层来继续。在316中，该过程通过在第二焊料层上形成第一管芯接触层来继续。接下来在318中，该过程通过将第一管芯耦合至第一管芯接触层来继续。在320中，该部分过程通过将邻近第一管芯且与第一管芯水平间隔开的第二管芯耦合至第一管芯接触层来结束。
现在参照图4，描绘了包括半导体封装(例如，如图1A和1B中示出的半导体封装100)的无线设备的框图并且一般地被标示为400。无线设备400包括具有半导体封装100的处理器401。处理器401可被通信地耦合至存储器410。指令高速缓存在这一示图中未被显式地示出，但是如本领域中已知的，指令高速缓存可以是处理器401的一部分或者可以是耦合在处理器401与存储器410之间的单独的块。图4还示出了耦合至处理器401和显示器428的显示器控制器426。编码器/解码器(CODEC)434(例如，音频和/或语音CODEC)可被耦合至处理器401。还解说了其它组件，诸如无线控制器440(其可包括调制解调器)。扬声器436和话筒438可耦合至CODEC 434。图4还指示无线控制器440可耦合至无线天线442。在特定方面，处理器401、显示器控制器426、存储器410、CODEC 434以及无线控制器440被包括在***级封装或片上***设备422中。
在特定方面，输入设备430和电源444被耦合至片上***设备422。此外，在特定方面，如图4中所解说的，显示器428、输入设备430、扬声器436、话筒438、无线天线442和电源444在片上***设备422的外部。然而，显示器428、输入设备430、扬声器436、话筒438、无线天线442和电源444中的每一者可被耦合至片上***设备422的组件，诸如接口或控制器。应当注意，尽管图4描绘了无线通信设备，但是处理器401和存储器410还可被集成到选自包括以下各项的组的设备中：音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、移动设备、移动电话、智能电话、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、膝上型计算机、服务器、以及机动车辆中的车载设备或其他类似设备。
本文所描述的方法、装置和***的各示例可在许多应用中使用。进一步的应用对于本领域普通技术人员应该是显而易见的。例如，根据本公开的半导体封装可被集成到各种设备中，诸如选自包括以下各项的组的设备：音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、移动设备、移动电话、智能电话、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、膝上型计算机、服务器、以及机动车辆中的车载设备。
措辞“示例性”在本文中用于表示“用作示例、实例或解说”。本文中描述为“示例性”的任何细节不必被解释为优于或胜过其他示例。同样，术语“示例”并不要求所有示例都包括所讨论的特征、优点、或工作模式。术语“在一个示例中”、“示例”、“在一个特征中”和/或“特征”在本说明书中的使用并非必然引述相同特征和/或示例。此外，特定的特征和/或结构可与一个或多个其他特征和/或结构组合。并且，由此描述的装置的至少一部分可被配置成执行由此描述的方法的至少一部分。
本文中所使用的术语是仅出于描述特定示例的目的，且并非旨在限制本公开的各示例。如本文所使用的，单数形式的“一”、“某”和“该”旨在也包括复数形式，除非上下文另外明确指示。还将理解，术语“包括”、“具有”、“包含”和/或“含有”在本文中使用时指明所陈述的特征、整数、操作、元素、和/或组件的存在，但并不排除一个或多个其他特征、整数、操作、元素、组件和/或其群组的存在或添加。
应该注意，术语“连接”、“耦合”或其任何变体意指在元件之间的直接或间接的任何连接或耦合，且可涵盖两个元件之间中间元件的存在，这两个元件经由该中间元件被“连接”或“耦合”在一起。元件之间的耦合和/或连接可为物理的、逻辑的、或其组合。如本文所采用的，元件可例如通过使用一条或多条导线、电缆、和/或印刷电气连接来“连接”或“耦合”在一起。这些是若干非限定和非穷尽性示例。
本文中使用诸如“第一”、“第二”等之类的指定对元素的任何引述并不限定那些元素的数量和/或次序。确切而言，这些指定被用作区别两个或更多个元素和/或元素实例的便捷方法。由此，对第一元素和第二元素的引述并不意味着仅能采用两个元素，或者第一元素必须必然地位于第二元素之前。同样，除非另外声明，否则元素集合可包括一个或多个元素。另外，在说明书或权利要求中使用的“A、B、或C中的至少一者”形式的术语可被解读为“A或B或C或这些元素的任何组合”。
本申请中已描述或描绘的任何内容都不旨在指定任何组件、特征、益处、优点、或等同物奉献给公众，无论这些组件、特征、益处、优点或等同物是否记载在权利要求中。
此外还应注意，本描述或权利要求中公开的方法可由包括用于执行该方法的相应动作的装置的设备来实现。
此外，在一些示例中，个体动作可被细分为多个子动作或包含多个子动作。此类子动作可被包含在个体动作的公开中并且可以是个体动作的公开的一部分。
尽管前面的公开示出了本公开的解说性示例，但是应当注意，在其中可作出各种变更和修改而不会脱离如所附权利要求定义的本公开的范围。根据本文中所描述的本公开的各示例的方法权利要求中的功能和/或动作不一定要以任何特定次序执行。另外，众所周知的元素将不被详细描述或可被省去以免模糊本文所公开的各方面和示例的相关细节。此外，尽管本公开的要素可能是以单数来描述或主张权利的，但是复数也是已料想了的，除非显式地声明了限定于单数。

Claims (38)

1.一种半导体封装，包括：
基板，所述基板包括第一多个通孔；
嵌入在所述基板中的桥；
耦合至所述基板的第一管芯；
耦合至所述基板且与所述第一管芯水平间隔开的第二管芯；
至少部分地在所述基板中的多个导电桥互连，所述多个导电桥互连配置成将所述桥耦合至所述第一管芯和所述第二管芯，并且所述多个导电桥互连中的每一者包括：直接耦合至所述桥的第一桥接触层，在所述第一桥接触层上的第一焊料层，在所述第一焊料层上的第二桥接触层；
配置成将所述第一管芯和所述第二管芯耦合至所述第一多个通孔的多个管芯互连；
所述基板的第一电介质层，所述第一电介质层配置成封装所述桥和第一路由层，并且至少部分地封装所述多个导电桥互连和所述多个管芯互连、所述第一桥接触层、所述第一焊料层、以及所述第二桥接触层；以及
所述基板的在所述第一电介质层上方的第四电介质层，所述第四电介质层配置成至少部分地封装所述第一管芯、所述第二管芯、所述多个导电桥互连、以及所述多个管芯互连，所述第四电介质层包括从所述第一路由层穿过所述第四电介质层延伸至第一表面的第二焊点图案。
2. 如权利要求1所述的半导体封装，其特征在于，所述多个导电桥互连中的每一者进一步包括：
在所述第二桥接触层上的第二焊料层，以及
在所述第二焊料层上且直接耦合至所述第一管芯或所述第二管芯中的一者的第一管芯接触层。
3.如权利要求1所述的半导体封装，其特征在于，所述多个管芯互连中的每一者进一步包括：
直接耦合至所述第一多个通孔中的一者的第一路由层，
在所述第一路由层上的第三焊料层，以及
在所述第三焊料层上且直接耦合至所述第一管芯或所述第二管芯中的一者的第二管芯接触层。
4. 如权利要求1所述的半导体封装，其特征在于，所述基板进一步包括：
在所述第一电介质层下方的第二电介质层，以及
在所述第二电介质层下方的第三电介质层，
所述第三电介质层包括：邻近所述第二电介质层的嵌入在所述第三电介质层中的第三路由层和从第二表面穿过所述第三电介质层延伸至所述第三路由层的第一焊点图案；以及
所述第二电介质层包括：邻近所述第一电介质层的嵌入在所述第二电介质层中的第二路由层和从所述第三路由层穿过所述第二电介质层延伸至所述第二路由层的第二多个通孔。
5.如权利要求4所述的半导体封装，其特征在于，所述半导体封装被纳入到选自包括以下各项的组的设备中：音乐播放器、视频播放器、导航设备、通信设备、移动设备、智能电话、个人数字助理、固定位置终端、计算机、可穿戴设备、服务器、以及机动车辆中的车载设备。
6.如权利要求4所述的半导体封装，其特征在于，所述半导体封装被纳入到娱乐单元中。
7.如权利要求4所述的半导体封装，其特征在于，所述半导体封装被纳入到移动电话中。
8.如权利要求4所述的半导体封装，其特征在于，所述半导体封装被纳入到膝上型计算机或平板计算机中。
9. 一种层叠封装半导体封装，包括：
具有第三管芯的第一封装；以及
附连至所述第一封装的第二封装，所述第二封装包括：
具有第一多个通孔的基板；
嵌入在所述基板中的桥；
耦合至所述基板的第一管芯；
耦合至所述基板且与所述第一管芯水平间隔开的第二管芯；
至少部分地在所述基板中的多个导电桥互连，所述多个导电桥互连配置成将所述桥耦合至所述第一管芯和所述第二管芯，并且所述多个导电桥互连中的每一者包括：直接耦合至所述桥的第一桥接触层，在所述第一桥接触层上的第一焊料层，在所述第一焊料层上的第二桥接触层；
配置成将所述第一管芯和所述第二管芯耦合至所述第一多个通孔的多个管芯互连；
所述基板的第一电介质层，所述第一电介质层配置成封装所述桥和第一路由层，并且至少部分地封装所述多个导电桥互连和所述多个管芯互连、所述第一桥接触层、所述第一焊料层、以及所述第二桥接触层；以及
所述基板的在所述第一电介质层上方的第四电介质层，所述第四电介质层配置成至少部分地封装所述第一管芯、所述第二管芯、所述多个导电桥互连、以及所述多个管芯互连，所述第四电介质层包括从所述第一路由层穿过所述第四电介质层延伸至第一表面的第二焊点图案。
10.如权利要求9所述的层叠封装半导体封装，其特征在于，所述多个导电桥互连中的每一者进一步包括：
在所述第二桥接触层上的第二焊料层，以及
在所述第二焊料层上且直接耦合至所述第一管芯或所述第二管芯中的一者的第一管芯接触层。
11.如权利要求9所述的层叠封装半导体封装，其特征在于，所述多个管芯互连中的每一者进一步包括：
直接耦合至所述第一多个通孔中的一者的第一路由层，
在所述第一路由层上的第三焊料层，以及
在所述第三焊料层上且直接耦合至所述第一管芯或所述第二管芯中的一者的第二管芯接触层。
12.如权利要求9所述的层叠封装半导体封装，其特征在于，所述基板进一步包括：
在所述第一电介质层下方的第二电介质层，以及
在所述第二电介质层下方的第三电介质层，
所述第三电介质层包括：邻近所述第二电介质层的嵌入在所述第三电介质层中的第三路由层和从第二表面穿过所述第三电介质层延伸至所述第三路由层的第一焊点图案；以及
所述第二电介质层包括：邻近所述第一电介质层的嵌入在所述第二电介质层中的第二路由层和从所述第三路由层穿过所述第二电介质层延伸至所述第二路由层的第二多个通孔。
13.如权利要求12所述的层叠封装半导体封装，其特征在于，所述第一封装被耦合至所述第一路由层并且包括形成在将所述第一封装电耦合至所述第一路由层的所述第二焊点图案中的第二多个焊点。
14.如权利要求13所述的层叠封装半导体封装，其特征在于，所述层叠封装半导体封装被纳入到选自包括以下各项的组的设备中：音乐播放器、视频播放器、导航设备、通信设备、移动设备、智能电话、个人数字助理、固定位置终端、计算机、可穿戴设备、服务器、以及机动车辆中的车载设备。
15.如权利要求13所述的层叠封装半导体封装，其特征在于，所述层叠封装半导体封装被纳入到娱乐单元中。
16.如权利要求13所述的层叠封装半导体封装，其特征在于，所述层叠封装半导体封装被纳入到移动电话中。
17.如权利要求13所述的层叠封装半导体封装，其特征在于，所述层叠封装半导体封装被纳入到膝上型计算机或平板计算机中。
18.一种用于形成半导体封装的方法，包括：
将晶种层施加于载体；
在所述晶种层上形成第一路由层，所述第一路由层具有第一桥接触层；
将桥耦合至所述第一桥接触层；
在所述晶种层上形成第一电介质层；
移除所述载体和所述晶种层；
在所述第一桥接触层上形成第一焊料层，
在所述第一焊料层上形成第二桥接触层；
所述第一电介质层至少部分地封装所述第一桥接触层、所述第一焊料层、以及所述第二桥接触层；
在所述第二桥接触层和所述第一路由层上形成第二焊料层；
在所述第二焊料层上形成第一管芯接触层；
将第一管芯耦合至所述第一管芯接触层；
将邻近所述第一管芯且与所述第一管芯水平间隔开的第二管芯耦合至所述第一管芯接触层；以及
在所述第一电介质层中形成第一多个通孔，所述第一多个通孔耦合至所述第一路由层。
19.如权利要求18所述的方法，其特征在于，进一步包括：
在所述第一电介质层上形成第二路由层，所述第二路由层耦合至所述第一多个通孔；
在所述第一电介质层上形成第二电介质层；
在所述第二电介质层中形成第二多个通孔，所述第二多个通孔耦合至所述第二路由层；
在所述第二电介质层上形成第三路由层，所述第三路由层耦合至所述第二多个通孔；
在所述第二电介质层上形成第三电介质层；以及
形成穿过所述第三电介质层至所述第三路由层的第一焊点图案。
20.如权利要求19所述的方法，其特征在于，进一步包括在所述第一电介质层上与所述第二电介质层相对地形成第四电介质层，所述第四电介质层封装所述第二焊料层和所述第一管芯接触层。
21.如权利要求20所述的方法，其特征在于，进一步包括形成穿过所述第四电介质层至所述第一路由层的第二焊点图案。
22.如权利要求21所述的方法，其特征在于，进一步包括：
在所述第二焊点图案中形成第二多个焊点；以及
将第一封装耦合至所述第二多个焊点，所述第一封装具有在所述第一封装中的半导体。
23.如权利要求22所述的方法，其特征在于，进一步包括：
将底料填充层施加在所述第一封装与所述第四电介质层之间；以及
在所述第一焊点图案中形成第一多个焊点，所述第一多个焊点电耦合至所述第三路由层。
24.如权利要求23所述的方法，其特征在于，进一步包括将所述半导体封装纳入到从包括以下各项的组中选择的设备中：音乐播放器、视频播放器、导航设备、通信设备、移动设备、智能电话、个人数字助理、位置固定的终端、计算机、可穿戴设备、服务器、以及机动车辆中的车载设备。
25.如权利要求23所述的方法，其特征在于，进一步包括将所述半导体封装纳入到娱乐单元中。
26.如权利要求23所述的方法，其特征在于，进一步包括将所述半导体封装纳入到移动电话中。
27.如权利要求23所述的方法，其特征在于，进一步包括将所述半导体封装纳入到膝上型计算机或平板计算机中。
28.一种用于形成半导体封装的方法，包括：
将晶种层施加于载体；
在所述晶种层上形成第一路由层，所述第一路由层具有第一桥接触层；
将桥耦合至所述第一桥接触层；
在所述晶种层上形成第一电介质层；
移除所述载体和所述晶种层；
在所述第一桥接触层上形成第一焊料层，
在所述第一焊料层上形成第二桥接触层；
所述第一电介质层至少部分地封装所述第一桥接触层、所述第一焊料层、以及所述第二桥接触层；
在所述第二桥接触层和所述第一路由层上形成第二焊料层；
在所述第二焊料层上形成第一管芯接触层；
将第一管芯耦合至所述第一管芯接触层；
将邻近所述第一管芯且与所述第一管芯水平间隔开的第二管芯耦合至所述第一管芯接触层；以及
在所述第一电介质层中形成第一多个通孔。
29.如权利要求28所述的方法，其特征在于，进一步包括：
在所述第一电介质层上形成第二路由层；
在所述第一电介质层上形成第二电介质层；
在所述第二电介质层中形成第二多个通孔；
在所述第二电介质层上形成第三路由层；
在所述第二电介质层上形成第三电介质层；以及
形成穿过所述第三电介质层至所述第三路由层的第一焊点图案。
30.如权利要求29所述的方法，其特征在于，进一步包括在所述第一电介质层上与所述第二电介质层相对地形成第四电介质层，所述第四电介质层封装所述第二焊料层和所述第一管芯接触层。
31.如权利要求30所述的方法，其特征在于，进一步包括形成穿过所述第四电介质层至所述第一路由层的第二焊点图案。
32.如权利要求31所述的方法，其特征在于，进一步包括：
在所述第二焊点图案中形成第二多个焊点；以及
将第一封装耦合至所述第二多个焊点，所述第一封装具有在所述第一封装中的半导体。
33.如权利要求32所述的方法，其特征在于，进一步包括：
将底料填充层施加在所述第一封装与所述第四电介质层之间；以及
在所述第一焊点图案中形成第一多个焊点，所述第一多个焊点电耦合至所述第三路由层。
34.如权利要求33所述的方法，其特征在于，进一步包括：
将所述第一多个通孔耦合至所述第一路由层；
将所述第二路由层耦合至所述第一多个通孔；
将所述第二多个通孔耦合至所述第二路由层；以及
将所述第三路由层耦合至所述第二多个通孔。
35.如权利要求34所述的方法，其特征在于，进一步包括将所述半导体封装纳入到从包括以下各项的组中选择的设备中：音乐播放器、视频播放器、导航设备、通信设备、移动设备、智能电话、个人数字助理、位置固定的终端、计算机、可穿戴设备、服务器、以及机动车辆中的车载设备。
36.如权利要求34所述的方法，其特征在于，进一步包括将所述半导体封装纳入到娱乐单元中。
37.如权利要求34所述的方法，其特征在于，进一步包括将所述半导体封装纳入到移动电话中。
38.如权利要求34所述的方法，其特征在于，进一步包括将所述半导体封装纳入到膝上型计算机或平板计算机中。
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