CN107591366A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN107591366A
CN107591366A CN201610527878.XA CN201610527878A CN107591366A CN 107591366 A CN107591366 A CN 107591366A CN 201610527878 A CN201610527878 A CN 201610527878A CN 107591366 A CN107591366 A CN 107591366A
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dielectric layer
gate structure
layer
metal gate
interlayer dielectric
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CN107591366B (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Abstract

A kind of semiconductor structure and forming method thereof, the semiconductor structure include：Substrate is provided；Metal gate structure is formed in substrate, the metal gate structure includes gate dielectric layer, the work-function layer on gate dielectric layer and the metal level in work-function layer；Barrier layer is formed at the top of metal gate structure；Interlayer dielectric layer is formed in substrate between metal gate structure；Form the contact hole plug through the interlayer dielectric layer；After forming the contact hole plug, substrate is made annealing treatment.The present invention forms barrier layer after metal gate structure is formed at the top of metal gate structure；The barrier layer is used in subsequent anneal processing procedure; the metal gate structure is played a protective role; the easy diffusing atom in annealing is avoided to diffuse in the work-function layer of metal gate structure; so as to avoid the work function value to work-function layer from having an impact, and then the electric property of semiconductor devices can be optimized.

Description

Semiconductor structure and forming method thereof
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
The main semiconductor devices of integrated circuit especially super large-scale integration is metal-oxide-partly lead Body FET (MOS transistor).With the continuous development of production of integrated circuits technology, semiconductor device Part technology node constantly reduces, and the physical dimension of semiconductor devices follows Moore's Law and constantly reduced.When half It is various because caused by the physics limit of semiconductor devices when conductor device is reduced in size to a certain degree Second-order effect occurs in succession, and the characteristic size of semiconductor devices is scaled to become more and more difficult.Its In, in field of semiconductor fabrication, most challenging is how to solve that semiconductor device creepage is big to ask Topic.The leakage current of semiconductor devices is big, caused mainly by the constantly reduction of traditional gate dielectric layer thickness.
The solution method currently proposed is to replace traditional silicon dioxide gate dielectric using high-k gate dielectric material Material, and metal is used as gate electrode, to avoid high-g value that Fermi's energy occurs with conventional gate electrodes material Level pinning effect and boron osmotic effect.The introducing of high-k/metal gate, reduce the leakage current of semiconductor devices.
Although the introducing of high-k/metal gate can improve the electric property of semiconductor devices to a certain extent, But the electric property of the semiconductor devices of prior art formation has much room for improvement.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of semiconductor structure and forming method thereof, optimization semiconductor device The electric property of part.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：There is provided Substrate；Form metal gate structure on the substrate, the metal gate structure include gate dielectric layer, Work-function layer on the gate dielectric layer and the metal level in the work-function layer；Institute State and barrier layer is formed at the top of metal gate structure；Forming layer in substrate between the metal gate structure Between dielectric layer；Form the contact hole plug through the interlayer dielectric layer；After forming the contact hole plug, The substrate is made annealing treatment.
Accordingly, the present invention also provides a kind of semiconductor structure, including：Substrate；Metal gate structure, In the substrate, the metal gate structure includes gate dielectric layer, on the gate dielectric layer Work-function layer and the metal level in the work-function layer；Barrier layer, positioned at the metal gates The top of structure；Interlayer dielectric layer, in the substrate between the metal gate structure.
Compared with prior art, technical scheme has advantages below：
The present invention forms barrier layer after metal gate structure is formed at the top of the metal gate structure； The barrier layer is used in subsequent anneal processing procedure, and the metal gate structure is played a protective role. The easy diffusing atom in the annealing is avoided to diffuse in the work-function layer of the metal gate structure, So as to avoid that the work function value of the work-function layer is had an impact, and then semiconductor devices can be optimized Electric property.
In alternative, the annealing is carried out under containing hydrogen atmosphere, the material on the barrier layer be containing Carbon material (such as：Rich carbon carbonitride of silicium, SiBCN, SiOCN or SiCN), wherein, carbon atom energy Enough preferably hydrogen ion adsorptions are to form carbon-hydrogen link, so as to effectively act as stopping hydrogen atom diffusion Effect, and then be advantageous to improve the protective effect to work-function layer.
In alternative, the step of forming the protective layer, includes：Remove the metal gates knot of segment thickness Structure, groove is formed in the bottom interlayer dielectric layer；Formed in the bottom of the groove and side wall described Barrier layer.Before being made annealing treatment to the substrate, the forming method also includes：In the stop The low K dielectric layer of the full groove of filling is formed on layer.The low K dielectric layer advantageously reduces the gold Belong to the parasitic capacitance value of grid structure and back segment metal level, so as to be advantageous to and improve the fortune of semiconductor devices Scanning frequency rate.
The present invention provides a kind of semiconductor structure, and the semiconductor structure includes being located at the metal gates knot Barrier layer at the top of structure, the barrier layer is used in the annealing for forming the semiconductor structure, right The metal gate structure plays a protective role, and prevents the easy diffusing atom in the annealing from diffusing to In the work-function layer of the metal gate structure, so as to avoid the work function value generation to the work-function layer Influence, and then the electric property of semiconductor devices can be optimized.
Brief description of the drawings
Fig. 1 to Figure 19 be semiconductor structure of the present invention the embodiment of forming method one in each step counter structure Schematic diagram.
Embodiment
From background technology, the electric property for the semiconductor devices that prior art is formed has much room for improvement.Knot The forming method of unification kind semiconductor structure analyzes its reason, and the forming method includes：
Substrate is provided, the substrate includes substrate and protrudes from the fin of the substrate, the substrate bag Include N-type region domain and p type island region domain；It is developed across the partial sidewall surface of the fin and the covering fin With the pseudo- grid structure of top surface；Source and drain doping area is formed in the fin of dummy gate structure both sides；Institute State on the substrate between fin formation bottom interlayer dielectric layer, at the top of the bottom interlayer dielectric layer with it is described Pseudo- grid structural top flushes；Dummy gate structure is removed, in the interlayer dielectric layer of N-type region domain bottom The first opening is formed, the second opening is formed in the interlayer dielectric layer of p type island region domain bottom；Described High-K gate dielectric layer, the high K grid are formed in one open bottom and side wall, the second open bottom and side wall Dielectric layer is also covered at the top of the bottom interlayer dielectric layer；P-type work(is formed on the high-K gate dielectric layer Function layer；Remove the P-type workfunction layer in the N-type region domain；High-K gate dielectric in the N-type region domain N-type workfunction layer is formed on layer, the N-type workfunction layer also covers the p-type work content in the p type island region domain Several layers；The metal material of full first opening of filling and the second opening is formed on the N-type workfunction layer Material；Remove higher than the metal material at the top of the bottom interlayer dielectric layer, form metal level, and remove height N-type workfunction layer, P-type workfunction layer and high-K gate dielectric at the top of the bottom interlayer dielectric layer Layer, wherein, high-K gate dielectric layer, N-type workfunction layer and metal level in first opening form institute State the first metal gate structure, high-K gate dielectric layer, P-type workfunction layer, N in second opening Type work-function layer and metal level form second metal gate structure；Formed and cover bottom interlayer Jie The interlayer dielectric layer of matter layer, the first metal gate structure and the second metal gate structure；It is situated between in the interlayer Contact hole plug, the contact hole plug and the source and drain doping are formed in matter layer and bottom interlayer dielectric layer Area is in contact；The substrate is made annealing treatment using hydrogen-containing gas.
But in the annealing, the isotope atom of hydrogen atom or hydrogen is easy diffusing atom, easily Diffuse in the work-function layer of first metal gate structure and the second metal gate structure, so as to cause The work function value increase of work-function layer, and then cause the electric property of semiconductor devices to decline.And by institute State P-type workfunction layer to be covered by the N-type workfunction layer, the isotope atom of the hydrogen atom or hydrogen expands The diffusion path of the N-type workfunction layer is dissipated to, less than the diffusion road for diffusing to the P-type workfunction layer Footpath, therefore be particularly acute the problem of N-type semiconductor device electric property decline.
In order to solve the technical problem, the present invention is forming barrier layer at the top of the metal gate structure； The barrier layer is used in subsequent anneal processing procedure, and the metal gate structure is played a protective role. The easy diffusing atom in the annealing is avoided to diffuse in the work-function layer, so as to avoid to described The work function value of work-function layer has an impact, and then can optimize the electric property of semiconductor devices.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings The specific embodiment of the present invention is described in detail.
Fig. 1 to Figure 19 be semiconductor structure of the present invention the embodiment of forming method one in each step counter structure Schematic diagram.
With reference to reference to figure 1 and Fig. 2, wherein, Fig. 1 is that the stereogram of semiconductor structure (only illustrates two Fin), Fig. 2 is cross-sectional views of the Fig. 1 along AA1 directions, there is provided substrate.
The substrate provides technique platform to be subsequently formed semiconductor structure.The substrate includes first area I (as shown in Figure 2) and second area II (as shown in Figure 2).In the present embodiment, the first area I For forming N-type device, the second area II is used to form P-type device.In another embodiment, The first area is used to form P-type device, and the second area is used to form N-type device.At other In embodiment, the substrate can also be only for forming N-type device or be only for forming P-type device.
In the present embodiment, so that the semiconductor structure of formation is fin formula field effect transistor as an example, the substrate Including substrate 100 and protrude from the fin (not indicating) of the substrate 100.Accordingly, institute is protruded from The fin stated on first area I substrates 100 is the first fin 110, protrudes from the second area II substrates Fin on 100 is the second fin 120.In another embodiment, the semiconductor structure is flat crystal Pipe, the substrate is planar substrates.
In the present embodiment, the substrate 100 is silicon substrate.In other embodiments, the material of the substrate Material can also be germanium, SiGe, carborundum, GaAs or gallium indium, and the substrate can also be insulation The germanium substrate on silicon substrate or insulator on body.The material of the material of the fin and the substrate 100 Expect identical.In the present embodiment, the material of the fin is silicon.In other embodiment, the material of the fin Material can also be germanium, SiGe, carborundum, GaAs or gallium indium.
Specifically, forming the processing step of the substrate 100 and fin includes：Initial substrate is provided； The initial substrate surface forms patterned hard mask layer 200；Carved with the hard mask layer 200 for mask Lose the initial substrate, the initial substrate after etching is as substrate 100, the projection positioned at the surface of substrate 100 As fin.
In the present embodiment, after forming the substrate 100 and fin, retain the hard mask at the top of fin Layer 200.The material of the hard mask layer 200 is silicon nitride, subsequently when carrying out planarization process technique, The top surface of hard mask layer 200 is used for the stop position for defining planarization process technique, plays protection Effect at the top of fin.
With reference to reference to figure 3, it is necessary to explanation, after forming the substrate 100 and fin, the formation side Method also includes：Isolation structure 101, the isolation structure are formed on substrate 100 between the fin 101 tops are less than at the top of the fin.
Isolation structure of the isolation structure 101 as semiconductor structure, for adjacent devices are played every From effect.In the present embodiment, the material of the isolation structure 101 is silica.In other embodiments, The material of the isolation structure can also be silicon nitride or silicon oxynitride.
Specifically, the step of forming isolation structure 101 includes：Substrate 100 between the fin Upper formation barrier film, the top top (as shown in Figure 2) higher than the hard mask layer 200 of the barrier film； Remove the barrier film higher than the top of hard mask layer 200；Remove segment thickness barrier film with formed every From structure 101；Remove the hard mask layer 200.
With reference to reference to figure 4 to Figure 12, Fig. 4 is along fin bearing of trend (the BB1 directions in such as Fig. 1) Cross-sectional view, on the substrate formed metal gate structure (not indicating), the metal gate Pole structure includes gate dielectric layer 200 (as shown in figure 12), the work function on the gate dielectric layer 200 Layer (not indicating) and the metal level 240 (as shown in figure 12) in the work-function layer.
In the present embodiment, metal gates (high k last metal are formed after high-k gate dielectric layer is formed after Gate last) technique form the metal gate structure.It is described in detail below with reference to accompanying drawing.
With reference to figure 4, there is provided after the substrate, pseudo- grid structure, the pseudo- grid knot are formed on the fin Structure is across the partial sidewall surface and top surface of the fin and the covering fin.
Dummy gate structure takes up space position to be subsequently formed metal gate structure.In the present embodiment, shape Include into the step of dummy gate structure：It is developed across first fin 110 and covering first fin The partial sidewall surface in portion 110 and the first of top surface the pseudo- grid structure 111, are developed across second fin The second pseudo- grid structure on the partial sidewall surface and top surface of portion 120 and covering second fin 120 121。
It should be noted that forming dummy gate structure, the forming method also includes：Described first Side wall 130 is formed in the pseudo- pseudo- side wall of grid structure 121 of grid structure 111 and second.In the present embodiment, the side The material of wall 130 is silicon nitride.
With continued reference to Fig. 4, first is formed in the first fin 110 of the described first pseudo- both sides of grid structure 111 Source and drain doping area 112；The second source is formed in the second fin 120 of the described second pseudo- both sides of grid structure 121 Leak doped region 122.
Bottom interlayer is formed with continued reference to Fig. 4, in the substrate between dummy gate structure (not indicating) to be situated between Matter layer 102, the top of the bottom interlayer dielectric layer 102 at the top of dummy gate structure with flushing.
The material of the bottom interlayer dielectric layer 102 is insulating materials, for example, silica, silicon nitride, Silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.In the present embodiment, the bottom interlayer The material of dielectric layer 102 is silica.
With reference to figure 5, dummy gate structure (not indicating) is removed, in the bottom interlayer dielectric layer 102 Form opening (not indicating).
The opening provides locus to be subsequently formed metal gate structure.In the present embodiment, institute is removed The first pseudo- grid structure 111 (as shown in Figure 4) is stated, first is formed in the bottom interlayer dielectric layer 102 Opening 113；The described second pseudo- grid structure 121 (as shown in Figure 4) is removed, in the bottom inter-level dielectric The second opening 123 is formed in layer 102.
With reference to figure 6, on the described first 113 bottoms of opening and side wall and the second 123 bottoms of opening and Gate dielectric layer 200 is formed in side wall.
In the present embodiment, the material of the gate dielectric layer 200 is high-k gate dielectric material, wherein, high k Gate dielectric material refers to that relative dielectric constant is more than the gate dielectric material of silica relative dielectric constant. In the present embodiment, the material of the gate dielectric layer 200 is HfO2, the gate dielectric layer 200 is also located at institute State on the top of interlayer dielectric layer 102.In other embodiments, the material of the gate dielectric layer can also be HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、ZrO2Or Al2O3。
It should be noted that in order that there is good boundary between the gate dielectric layer 200 and substrate that must be formed Face performance, to improve the formation quality of the gate dielectric layer 200, formed the gate dielectric layer 200 it Before, the forming method also includes：In the described first 113 bottoms of opening and the second 123 bottoms of opening Form boundary layer 140.In the present embodiment, the boundary layer 140, the boundary are formed using thermal oxidation technology The material of surface layer 140 is silica.
With reference to figure 7, the first work-function layer 210 is formed on the gate dielectric layer 200.
Follow-up the first work-function layer 210 removed in the first opening 113, retain the in the second opening 123 One work-function layer 210, first work-function layer 210 are used to adjust second area II semiconductor structures Threshold voltage.
In the present embodiment, the second area II is used to form P-type device；Accordingly, first work( Function layer 210 is p-type work function material, and p-type work function material workfunction range is 5.1ev to 5.5ev, For example, 5.2ev, 5.3ev or 5.4ev.In the present embodiment, described is formed using atom layer deposition process One work-function layer 210, the material of first work-function layer 210 is TiN.In other embodiments, institute The material for stating the first work-function layer can also be TaN, TiSiN or TaSiN；Chemical gaseous phase can also be used Depositing operation or physical gas-phase deposition form first work-function layer.
With reference to figure 8, full first opening 113 of filling is formed in first work-function layer 210 (such as Shown in Fig. 7) and second opening 123 (as shown in Figure 7) packed layer 201.
The material of the packed layer 201 is different from the material of the first work-function layer 210, and to be easy to be gone The material removed so that the follow-up technique for removing packed layer 201 will not cause to damage to the first work-function layer 210 Wound.In the present embodiment, the material of the packed layer 201 is ODL (Organic Dielectric Layer) Material, the packed layer 201 is formed using spin coating process, and the top of the packed layer 201 with it is described The top of first work-function layer 210 flushes.In other embodiments, the material of the packed layer can also be BARC (Bottom Anti-Reflective Coating) materials or DUO (Deep UV Light Absorbing Oxide) material.Wherein, the DUO materials are a kind of siloxane polymer materials, including CH3-SiOX、 Si-OH or SiOH3Deng.
With continued reference to Fig. 8, in the work-function layer 210 of packed layer 201 and first of the second area II Form photoresist layer 202.
With reference to figure 9, the work-function layer of packed layer 201 and first in the described first opening 113 is removed 210。
Specifically, (as shown in Figure 8) for mask with the photoresist layer 202, using dry etch process, Remove the work-function layer 210 of packed layer 201 and first in first opening 113；Remove the photoetching Glue-line 202.
With reference to figure 10, the packed layer 201 (as shown in Figure 9) in the described second opening 123 is removed, Expose the surface of the first work-function layer 210 in the second opening 123.
In the present embodiment, the packed layer in second opening 123 is removed using dry etch process etching 201.Specifically, the etching gas that the dry etch process uses include CF4Or CHF3.At other In embodiment, wet-etching technology etching can also be used to remove the packed layer in second opening.
With reference to figure 11, the second work-function layer is formed on the gate dielectric layer 200 in the described first opening 113 220。
Second work-function layer 220 is used for the threshold voltage for adjusting the first area I semiconductor structures.
In the present embodiment, the first area I is used to form N-type device；Accordingly, second work( Function layer 220 is N-type work function material, and N-type work function material workfunction range is 3.9ev to 4.5ev, For example, 4ev, 4.1ev or 4.3ev.In the present embodiment, described second is formed using atom layer deposition process Work-function layer 220, second work-function layer 220 are also located at the top of the first work-function layer 210；Institute The material for stating the second work-function layer 220 is TiAl.In other embodiments, second work-function layer Material can also be TaAlN, TiAlN, MoN, TaCN and AlN；Chemical vapor deposition can also be used Product technique or physical gas-phase deposition form second work-function layer.
It should be noted that saving light shield to reduce technology difficulty, second work-function layer 220 is formed Afterwards, the second work-function layer 220 positioned at the top of the first work-function layer 210 is retained.
It should also be noted that, after forming second work-function layer 220, the forming method also includes： Cap 230 is formed in second work-function layer 220.There is easily diffusion in the metal level being subsequently formed Ion, the cap 230 can stop the easily diffusion ion into second work-function layer 220 Diffusion, prevent the work function value of second work-function layer 220 from becoming big.In the present embodiment, the block The material of layer 230 is TiN or TaN..
With reference to figure 12, full first 113 (as shown in figure 11) of opening of filling and the second opening 123 are formed The metal level 240 of (as shown in figure 11).
The material of the metal level 240 is Al, Cu, Ag, Au, Pt, Ni, Ti or W.This implementation In example, the material of the metal level 240 is W.
Specifically, forming the processing step of the metal level 240 includes：In the described first 113 Hes of opening The full metal material of filling in second opening 123, the metal material top are higher than the second work-function layer 220 Top；Grinding removes forms the metal higher than the metal material at the top of the bottom interlayer dielectric layer 102 Layer 303, and also grinding removes the cap 230 higher than the top of bottom interlayer dielectric layer 102, the second work content Several layers of the 220, first work-function layer 210 and gate dielectric layer 200.Wherein, positioned at the described first opening 113 Interior gate dielectric layer 200, the second work-function layer 220, cap 230 and metal level 240 forms described First area I metal gate structure；Gate dielectric layer 200, first in the described second opening 123 Work-function layer 210, the second work-function layer 220, cap 230 and metal level 240 form described second Region II metal gate structure.
In another embodiment, metal gates (high k first are initially formed using being initially formed high-k gate dielectric layer Metal gate first) technique form the metal gate structure.Accordingly, formed on the substrate The step of metal gate structure, includes：Metal gate structure, first area metal are formed on the fin Grid structure is across the partial sidewall surface and top table of first fin and covering first fin Face, second area metal gate structure is across the part side of second fin and covering second fin Wall surface and top surface；After forming the metal gate structure, the forming method also includes：Institute State and the first source and drain doping area is formed in the first fin of first area metal gate structure both sides；Described The second source and drain doping area is formed in second fin of two regional metal grid structure both sides.
With reference to reference to figures 13 to Figure 15, barrier layer 311 is formed at the top of the metal gate structure (as schemed Shown in 15).
The barrier layer 311 is used in subsequent anneal processing, and protection is played to the metal gate structure Effect.
The material on the barrier layer 311 is carbonaceous material.In the present embodiment, the carbonaceous material is rich carbon Carbonitride of silicium (Carbon Rich Nitride).In other embodiments, the carbonaceous material can also be SiBCN, SiOCN or SiCN.Wherein, rich carbon carbonitride of silicium refers to the higher carbonitride of silicium of carbon content Material.Subsequent anneal processing is typically carried out under containing hydrogen atmosphere, and carbon atom can preferably adsorb described move back Hydrogen atom in fire processing, to form carbon-hydrogen link, so as to effectively act as stopping hydrogen atom diffusion Effect, is reduced or avoided the hydrogen atom and diffuses to the work-function layer of the first work-function layer 210 and second In 220, and then it can avoid causing the work-function layer 220 of the first work-function layer 210 and second bad Influence.
It should be noted that the atom percentage content of carbon is unsuitable too low, it is also unsuitable too high.If carbon Atom percentage content is too low, and in subsequent anneal processing, the ability of carbon atom hydrogen ion adsorption is poor, So as to cause the barrier layer 311 to stop, the ability of hydrogen atom diffusion is poor；If the atomic percent of carbon Too high levels, easily cause the relative dielectric constant on the barrier layer 311 too high, so as to easily cause institute State metal gate structure and posted with back segment (Back End Of Line, the BEOL) metal level being subsequently formed Raw capacitance is too high, and then reduces the operating rate of semiconductor devices.Therefore, in the present embodiment, it is described In rich carbon carbonitride of silicium, the atom percentage content of carbon is 3% to 15%.
It should also be noted that, the thickness on the barrier layer 311 is unsuitable excessively thin, it is also unsuitable blocked up.If The thickness on the barrier layer 311 is excessively thin, and the barrier layer 311 stops that the ability of hydrogen atom diffusion is poor； If the thickness on the barrier layer 311 is blocked up, easily cause the relative dielectric constant on the barrier layer 311 It is too high, so as to cause the parasitic capacitance value of metal level of the metal gate structure with being subsequently formed too high, And then the operating rate of semiconductor devices is caused to decline.Therefore, in the present embodiment, the barrier layer 311 Thickness beExtremely
In the present embodiment, include at the top of the metal gate structure the step of formation barrier layer 311：Go Except the metal gate structure of segment thickness, in the first area I and second area II bottom layer Between groove 241 (as shown in figure 13) is formed in dielectric layer 102；The resistance is formed in the groove 241 Barrier 311.
In the present embodiment, the metal gate structure of segment thickness is removed using dry etch process. In other embodiment, wet-etching technology can also be used, or, dry etch process and wet etching The technique that technique is combined removes the metal gate structure.
It should be noted that the depth of the groove 241 is unsuitable too small, it is also unsuitable excessive.It is if described Depth is too small, and it is too small easily to result in the process window on the barrier layer 311, so as to reduce the resistance The formation quality of barrier 311, and then reduce the ability that the barrier layer 311 stops hydrogen atom diffusion；Such as Depth is excessive described in fruit, i.e. the height of residual metallic grid structure is too small, so as to be easily reduced the metal The performance of grid structure, and then reduce the electric property of semiconductor devices.Therefore, in the present embodiment, institute The depth for stating groove isExtremely
In the present embodiment, the barrier layer 311 is formed at bottom and the side wall of the groove 241.Formed Behind barrier layer 311, the forming method also includes：It is full described that filling is formed on the barrier layer 311 The low K dielectric layer 321 (as shown in figure 15) of groove 241, the top of low K dielectric layer 321 and institute The top for stating bottom interlayer dielectric layer 102 flushes.
In the present embodiment, the material of the low K dielectric layer 321 is low k dielectric materials (low k dielectric material Material refers to relative dielectric constant more than or equal to the 2.6, dielectric material less than or equal to 3.9).The low K Dielectric layer 321 advantageously reduces the parasitic capacitance value of the metal gate structure and back segment metal level, so as to Be advantageous to improve the operating rate of semiconductor devices.In the present embodiment, the material of the low K dielectric layer 321 Expect for SiBCN.In other embodiments, the material of the low K dielectric layer can also be SiON, SiOCN Or SiBN.
Specifically, the step of forming the barrier layer 311 and low K dielectric layer 321 includes：Formed conformal Cover the barrier film 310 (as shown in figure 14) of the bottom of groove 241 and side wall, the barrier film 310 Also cover the top of bottom interlayer dielectric layer 102；Low-K dielectric film is formed on the barrier film 310 320 (as shown in figure 14), the low-K dielectric film fill out 320 and are full of the groove 241；Using planarization Technique, remove the low-K dielectric film 320 and barrier film at the top higher than the bottom interlayer dielectric layer 102 310, remaining barrier film 310 is the barrier layer 311, and remaining low-K dielectric film 320 is described low K dielectric layer 321.
In the present embodiment, the technique for forming the barrier film 310 is atom layer deposition process.Specifically, The material of the barrier film 310 is rich carbon carbonitride of silicium, the technological parameter bag of the atom layer deposition process Include：The presoma being passed through into ald room is the presoma containing Si, C and O, and technological temperature is 300 degrees Celsius to 600 degrees Celsius, pressure is 1 millitorr to 500 millitorrs, and the total gas flow rate of presoma is 300sccm to 5000sccm, frequency of depositing are 10 times to 100 times.
Wherein, when technological temperature is less than 300 degrees Celsius, the deposition speed of each depositing operation is easily caused Spend it is slow, so as to cause the thinner thickness of the barrier film 310, or need to increase the process time with up to To target thickness value, so as to reduce the formation efficiency of the barrier film 310；When the technological temperature is higher than At 600 degrees Celsius, easily cause the thermal decomposition of the presoma, so as to introduce similar chemical vapor deposition Phenomenon, and then the purity and step coverage of the barrier film 310 are influenceed, finally reduce the barrier film 310 formation quality.Based on the technological temperature of the setting, the gas of chamber pressure, presoma is always flowed Amount and frequency of depositing are set in zone of reasonableness value, so as to ensure the high-purity of the barrier film 310 and good Good step coverage, and the barrier film 310 to be formed is met target thickness value, and then improve the stop The formation quality of film 310.
In the present embodiment, the technique for forming the low-K dielectric film 320 is atom layer deposition process.Specifically Ground, the technological parameter of the atom layer deposition process include：The presoma being passed through into ald room Including SiH2Cl2、NH3、BHXAnd CHX, technological temperature is 300 degrees Celsius to 650 degrees Celsius, preceding The total gas flow rate for driving body is 200sccm to 5000sccm.
With reference to figure 16, inter-level dielectric is formed in the substrate between the metal gate structure (not indicating) Layer 400.
The material of the interlayer dielectric layer 400 is insulating materials, for example, silica, silicon nitride, nitrogen oxygen SiClx, silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.In the present embodiment, the interlayer dielectric layer 400 Material be silica.
In the present embodiment, metal gates (high k last metal are formed after high-k gate dielectric layer is formed after Gate last) technique form the metal gate structure, between the metal gate structure (not indicating) Substrate on formed with the bottom interlayer dielectric layer 102；Accordingly, the interlayer dielectric layer 400 is formed The step of in, the interlayer dielectric layer 400 is located at the bottom interlayer dielectric layer 102 and metal gates knot On at the top of structure.In another embodiment, metal gates (high is initially formed using being initially formed high-k gate dielectric layer K first metal gate first) technique form the metal gate structure；Accordingly, the interlayer is formed In the step of dielectric layer, with being flushed at the top of the metal gate structure at the top of the interlayer dielectric layer.
With reference to reference to figure 17 and Figure 18, the contact hole plug 420 through the interlayer dielectric layer 400 is formed (as shown in figure 18).
The contact hole plug 420 is used to realize the electrical connection in semiconductor devices, is additionally operable to realize device Electrical connection between device.In the present embodiment, the material of the contact hole plug 420 is W.Can be with The contact hole plug 420 is formed using chemical vapor deposition method, sputtering technology or electroplating technology.At it In his embodiment, the material of the contact hole plug can also be the metal materials such as Al, Cu, Ag or Au.
Specifically, the step of forming contact hole plug 420 includes：In the interlayer dielectric layer 400 Reveal with formation contact hole 410 (as shown in figure 17), the contact hole 410 in bottom interlayer dielectric layer 102 Go out source and drain doping area 122 of the first source and drain doping area 112 and second；Form the full contact hole of filling 410 contact hole plug 420 (as shown in figure 18), the contact hole plug 420 and first source and drain The source and drain doping area 122 of doped region 112 and second is in contact.
With reference to figure 19, after forming the contact hole plug 420, annealing 500 is carried out to the substrate.
The annealing 500 is carried out under containing hydrogen atmosphere.Specifically, it is described annealing 500 containing Have and carried out under the atmosphere of the isotope atom of hydrogen atom or hydrogen.During the annealing 500, hydrogen The isotope atom of atom or hydrogen is diffused under the metal gate structure via the contact hole plug 420 In the fin of side, to improve the interfacial state performance between metal gate structure and fin, the annealing 500 are additionally operable to the stress release of follow-up back segment (Back End Of Line, BEOL) interlayer, so as to improve The electric property and reliability performance of semiconductor devices.
In the present embodiment, the technological parameter of the annealing 500 includes：Pressure is an atmospheric pressure, Reacting gas is hydrogen or deuterium, and the gas flow of reacting gas rises to 10 every point for 0.5 standard per minute Clock standard liter.It should be noted that the hydrogen-containing gas is the isotope atom of hydrogen atom or hydrogen.At it In his embodiment, the hydrogen-containing gas can also include tritium atom.
It should be noted that the annealing temperature of the annealing 500 is unsuitable too high, it is also unsuitable too low. If the annealing temperature of the annealing 500 is too high, easily the ion distribution adulterated is caused bad Influence, so as to reduce the electric property of semiconductor devices；If the annealing temperature of the annealing 500 It is too low, improve the interfacial state performance between metal gate structure and fin, and for follow-up back segment (Back End Of Line, BEOL) interlayer stress release effect it is not obvious enough.Therefore, in the present embodiment, The annealing temperature of the annealing 500 is 200 degrees Celsius to 450 degrees Celsius, and the process time is 10 points Clock was to 120 minutes.
The present invention is formed at the top of the metal gate structure and stopped after the metal gate structure is formed 311 (as shown in figure 15) of layer, the barrier layer 311 are used to make annealing treatment 500 (as shown in figure 19) During, the metal gate structure is played a protective role, avoids the hydrogen atom from diffusing to described In two work-function layers 220 and the first work-function layer 210, so as to avoid to second work-function layer 220 Had an impact with the work function value of the first work-function layer 210, the threshold voltage of semiconductor devices is in pre- If in desired value, and then the electric property of semiconductor devices can be optimized.
With continued reference to Figure 19, the present invention also provides a kind of semiconductor structure, including：
Substrate；Metal gate structure (does not indicate), in the substrate, the metal gate structure bag Include gate dielectric layer 200, the work-function layer (not indicating) on the gate dielectric layer 200 and be located at Metal level 240 in the work-function layer；Barrier layer 311, positioned at the top of the metal gate structure； Interlayer dielectric layer 400, in the substrate between the metal gate structure；Contact hole plug 420, is passed through Wear the interlayer dielectric layer 400.
The substrate includes first area I and second area II.In the present embodiment, the first area I's Semiconductor structure is N-type device, and the semiconductor structure of the second area II is P-type device.Another In embodiment, the semiconductor structure of the first area is P-type device, the semiconductor of the second area Structure is N-type device.In other embodiments, the semiconductor structure in the substrate can also be only Including N-type device or only include P-type device.
In the present embodiment, so that the semiconductor structure of formation is fin formula field effect transistor as an example, the substrate Including substrate 100 and protrude from the fin of the substrate 100.Accordingly, firstth area is protruded from Fin on domain I substrates 100 is the first fin 110, is protruded from the second area II substrates 100 Fin is the second fin 120.In another embodiment, the semiconductor structure is planar transistor, described Substrate is planar substrates.
In the present embodiment, the substrate 100 is silicon substrate.In other embodiments, the material of the substrate Material can also be germanium, SiGe, carborundum, GaAs or gallium indium, and the substrate can also be insulation The germanium substrate on silicon substrate or insulator on body.The material of the material of the fin and the substrate 100 Expect identical.In the present embodiment, the material of the fin is silicon.In other embodiment, the material of the fin Material can also be germanium, SiGe, carborundum, GaAs or gallium indium.
It should be noted that the semiconductor structure also includes：Between the fin on substrate 100 Isolation structure 101, the top of the isolation structure 101 is less than at the top of the fin.The isolation structure 101 isolation structure as semiconductor structure, for playing buffer action to adjacent devices.In the present embodiment, The material of the isolation structure 101 is silica.In other embodiments, the material of the isolation structure Can also be silicon nitride or silicon oxynitride.
In the present embodiment, the first area I metal gate structures are across first fin 110 and cover The partial sidewall surface of first fin 110 and top surface；The second area II metal gates knots Structure is across the partial sidewall surface and top table of second fin 120 and covering second fin 120 Face.
The material of the gate dielectric layer 200 is high-k gate dielectric material, wherein, high-k gate dielectric material refers to , gate dielectric material of the relative dielectric constant more than silica relative dielectric constant.In the present embodiment, The material of the gate dielectric layer 200 is HfO2.In other embodiments, the material of the gate dielectric layer is also Can be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2Or Al2O3。
It should be noted that the semiconductor structure also includes：Between gate dielectric layer 200 and fin Boundary layer 140.The boundary layer 140 is used to improve the interface between the gate dielectric layer 200 and substrate Performance, it is additionally operable to improve the formation quality of the gate dielectric layer 200.In the present embodiment, the boundary layer 140 material is silica.
In the present embodiment, the work-function layer includes the on the second area I gate dielectric layers 200 One work-function layer 210, and the second work-function layer on the first area I gate dielectric layers 200 220。
First work-function layer 210 is used for the threshold voltage for adjusting second area II semiconductor structure. In the present embodiment, the semiconductor structure of the second area II is P-type device；Accordingly, described first Work-function layer 210 is p-type work function material, and p-type work function material workfunction range is 5.1ev to 5.5ev, For example, 5.2ev, 5.3ev or 5.4ev.In the present embodiment, the material of first work-function layer 210 is TiN.In other embodiments, the material of first work-function layer can also be TaN, TiSiN or TaSiN。
Second work-function layer 220 is used for the threshold value electricity for adjusting the semiconductor structure of the first area I Pressure.In the present embodiment, the semiconductor structure of the first area I is N-type device；Accordingly, it is described Second work-function layer 220 is N-type work function material, and N-type work function material workfunction range is 3.9ev To 4.5ev, for example, 4ev, 4.1ev or 4.3ev.In the present embodiment, second work-function layer 220 Material be TiAl.In other embodiments, the material of second work-function layer can also be TaAlN, TiAlN, MoN, TaCN and AlN.
The material of the metal level 240 is Al, Cu, Ag, Au, Pt, Ni, Ti or W.This implementation In example, the material of the metal level 240 is W.
It should be noted that the semiconductor structure also includes：Positioned at the metal level 240 and described the Cap 230 between two work-function layers 220.There is easy diffusion ion in the metal level 240, it is described Cap 230 can stop easily diffusion ion expanding into second work-function layer 220, prevent The work function value of second work-function layer 220 becomes big.In the present embodiment, the material of the cap 230 Expect for TiN or TaN.
In the present embodiment, the barrier layer 311 is used in the annealing for forming the semiconductor structure, The metal gate structure is played a protective role.
The material on the barrier layer 311 is carbonaceous material.In the present embodiment, the carbonaceous material is rich carbon Carbonitride of silicium (Carbon Rich Nitride).In other embodiments, the carbonaceous material can also be SiBCN, SiOCN or SiCN.Wherein, rich carbon carbonitride of silicium refers to the higher carbonitride of silicium of carbon content Material.The annealing is typically carried out under containing hydrogen atmosphere, and carbon atom can preferably adsorb described move back Hydrogen atom in fire processing, to form carbon-hydrogen link, so as to effectively act as stopping hydrogen atom diffusion Effect, is reduced or avoided the hydrogen atom and diffuses to the work-function layer of the first work-function layer 210 and second In 220, and then it can avoid causing the work-function layer 220 of the first work-function layer 210 and second bad Influence.
It should be noted that the atom percentage content of carbon is unsuitable too low, it is also unsuitable too high.If carbon Atom percentage content is too low, and in the annealing, the ability of carbon atom hydrogen ion adsorption is poor, So as to cause the barrier layer 311 to stop, the ability of hydrogen atom diffusion is poor；If the atomic percent of carbon Too high levels, easily cause the relative dielectric constant on the barrier layer 311 too high, so as to easily cause institute State metal gate structure and the parasitic capacitance value of back segment metal level (not shown) is too high, and then reduce and partly lead The operating rate of body device.Therefore, in the present embodiment, in the rich carbon carbonitride of silicium, the atom hundred of carbon It is 3% to 15% to divide than content.
It should also be noted that, the thickness on the barrier layer 311 is unsuitable excessively thin, it is also unsuitable blocked up.If The thickness on the barrier layer 311 is excessively thin, and the barrier layer 311 stops that the ability of hydrogen atom diffusion is poor； If the thickness on the barrier layer 311 is blocked up, easily cause the dielectric constant on the barrier layer 311 too high, So as to cause the parasitic capacitance value of the metal gate structure and back segment metal level too high, and then cause partly to lead The operating rate of body device declines.Therefore, in the present embodiment, the thickness on the barrier layer 311 is Extremely
It should be noted that the semiconductor structure also includes：The base between the metal gate structure Bottom interlayer dielectric layer 102 on bottom, the top of the bottom interlayer dielectric layer 102 are higher than the metal gate The top of pole structure；Accordingly, the interlayer dielectric layer 400 is located at the bottom interlayer dielectric layer 102 On the top of metal gate structure.
The material of the interlayer dielectric layer 400 and bottom interlayer dielectric layer 102 is insulating materials, is, for example, Silica, silicon nitride, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.The present embodiment In, the material of the interlayer dielectric layer 400 and bottom interlayer dielectric layer 102 is silica.
It should also be noted that, the semiconductor structure also includes：Positioned at the top of barrier layer 311 Low K dielectric layer 321, the top of the low K dielectric layer 321 and the bottom interlayer dielectric layer 102 Top flushes；The barrier layer 311 is also located at the low K dielectric layer 321 and bottom interlayer dielectric layer 102 Between.That is, the interlayer dielectric layer 400 covers the bottom interlayer dielectric layer 102, barrier layer 311 and the top of low K dielectric layer 321.
In the present embodiment, the material of the low K dielectric layer 321 is low k dielectric materials (low k dielectric material Material refers to relative dielectric constant more than or equal to the 2.6, dielectric material less than or equal to 3.9).The low K Dielectric layer 321 advantageously reduces the parasitic capacitance value of the metal gate structure and back segment metal level, so as to Be advantageous to the operating rate with improving semiconductor devices.In the present embodiment, the low K dielectric layer 321 Material is SiBCN.In other embodiments, the material of the low K dielectric layer can also be SiON, SiOCN or SiBN.
It should be noted that the thickness of the low K dielectric layer 321 is unsuitable excessively thin, it is also unsuitable blocked up.Such as The thickness of low K dielectric layer 321 is excessively thin described in fruit, the DeGrain to reducing parasitic capacitance value；If The thickness of the low K dielectric layer 321 is blocked up, i.e., the height of described metal gate structure is too small, easily drop The performance of the low metal gate structure, so as to reduce the electric property of semiconductor devices.Therefore, this reality Apply in example, the thickness of the low K dielectric layer 321 isExtremely
The contact hole plug 420 is used to realize the electrical connection in semiconductor devices, is additionally operable to realize device Electrical connection between device.In the present embodiment, the material of the contact hole plug 420 is W.At it In his embodiment, the material of the contact hole plug can also be the metal materials such as Al, Cu, Ag or Au.
It should be noted that in the present embodiment, the contact hole plug 420 also extends through the bottom interlayer Dielectric layer 102, it is in contact with source and drain doping area 122 of the first source and drain doping area 112 and second.
It should also be noted that, in the present embodiment, the semiconductor structure also includes：Positioned at described first The first source and drain doping area 112 in first fin 110 of region I metal gates knots both sides；Positioned at described The second source and drain doping area 122 in second fin 120 in two regions II metal gate structures both sides.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore the guarantor of the present invention Shield scope should be defined by claim limited range.

Claims (20)

  1. A kind of 1. forming method of semiconductor structure, it is characterised in that including：
    Substrate is provided；
    Metal gate structure is formed on the substrate, and the metal gate structure includes gate dielectric layer, the work-function layer on the gate dielectric layer and the metal level in the work-function layer；
    Barrier layer is formed at the top of the metal gate structure；
    Interlayer dielectric layer is formed in substrate between the metal gate structure；
    Form the contact hole plug through the interlayer dielectric layer；
    After forming the contact hole plug, the substrate is made annealing treatment.
  2. 2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material on the barrier layer is rich carbon carbonitride of silicium, SiBCN, SiOCN or SiCN；
    In the rich carbon carbonitride of silicium, the atom percentage content 3% to 15% of carbon.
  3. 3. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the thickness on the barrier layer isExtremely
  4. 4. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the semiconductor structure is fin formula field effect transistor；
    In the step of providing substrate, the substrate includes substrate and protrudes from the fin of the substrate；
    The step of forming metal gate structure on the substrate includes：Metal gate structure is formed on the fin, the metal gate structure is across the partial sidewall surface and top surface of the fin and the covering fin；After forming the metal gate structure, the forming method also includes：Source and drain doping area is formed in the fin of the metal gate structure both sides；In the step of interlayer dielectric layer is formed in substrate between the metal gate structure, with being flushed at the top of the metal gate structure at the top of the interlayer dielectric layer；
    Or
    After providing the substrate, the forming method also includes：Pseudo- grid structure is formed on the fin, dummy gate structure is across the partial sidewall surface and top surface of the fin and the covering fin；Source and drain doping area is formed in the fin of dummy gate structure both sides；Bottom interlayer dielectric layer is formed in substrate between dummy gate structure, the top of the bottom interlayer dielectric layer at the top of dummy gate structure with flushing；Dummy gate structure is removed, opening is formed in the bottom interlayer dielectric layer；The step of forming metal gate structure on the substrate includes：Metal gate structure is formed in the opening, is flushed at the top of the metal gate structure with bottom interlayer dielectric layer top；In the step of interlayer dielectric layer is formed in substrate between the metal gate structure, the interlayer dielectric layer is located on the bottom interlayer dielectric layer and metal gate structure top.
  5. 5. the forming method of semiconductor structure as claimed in claim 4, it is characterised in that formed includes through the step of contact hole plug of the interlayer dielectric layer：Contact hole is formed in the interlayer dielectric layer and bottom interlayer dielectric layer, the contact hole exposes the source and drain doping area；
    The contact hole plug of the full contact hole of filling is formed, the contact hole plug is in contact with the source and drain doping area.
  6. 6. the forming method of semiconductor structure as claimed in claim 4, it is characterised in that the interlayer dielectric layer is located at the top of the bottom interlayer dielectric layer and metal gate structure；The step of barrier layer is formed at the top of the metal gate structure includes：The metal gate structure of segment thickness is removed, groove is formed in the bottom interlayer dielectric layer；
    The barrier layer is formed in the groove.
  7. 7. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that in the step of forming the barrier layer in the groove, the barrier layer is formed in the bottom of the groove and side wall；
    After forming barrier layer at the top of the metal gate structure, formed before the contact hole plug of the interlayer dielectric layer, the forming method also includes：The low K dielectric layer of the full groove of filling is formed on the barrier layer, is flushed at the top of the low K dielectric layer with bottom interlayer dielectric layer top.
  8. 8. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that the material of the low K dielectric layer is SiON, SiOCN, SiBN or SiBCN.
  9. 9. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that the step of forming the barrier layer and low K dielectric layer includes：The conformal covering bottom portion of groove and the barrier film of side wall are formed, the barrier film also covers the bottom interlayer dielectric layer；
    Low-K dielectric film, the full groove of low-K dielectric film filling are formed on the barrier film；
    Using flatening process, low-K dielectric film and barrier film of the removal higher than the top of the bottom interlayer dielectric layer.
  10. 10. the forming method of semiconductor structure as claimed in claim 9, it is characterised in that the technique for forming the barrier film is atom layer deposition process.
  11. 11. the forming method of semiconductor structure as claimed in claim 10, it is characterised in that the material of the barrier film is rich carbon carbonitride of silicium, and the technological parameter of the atom layer deposition process includes：The presoma containing Si, C and O is passed through into ald room, technological temperature is 300 degrees Celsius to 600 degrees Celsius, and pressure is 1 millitorr to 500 millitorrs, and the total gas flow rate of presoma is 300sccm to 5000sccm, and frequency of depositing is 10 times to 100 times.
  12. 12. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the annealing is carried out under containing hydrogen atmosphere.
  13. A kind of 13. semiconductor structure, it is characterised in that including：
    Substrate；
    Metal gate structure, in the substrate, the metal gate structure includes gate dielectric layer, the work-function layer on the gate dielectric layer and the metal level in the work-function layer；
    Barrier layer, positioned at the top of the metal gate structure；
    Interlayer dielectric layer, in the substrate between the metal gate structure；
    Contact hole plug, through the interlayer dielectric layer.
  14. 14. semiconductor structure as claimed in claim 13, it is characterised in that the material on the barrier layer is rich carbon carbonitride of silicium, SiBCN, SiOCN or SiCN；
    In the rich carbon carbonitride of silicium, the atom percentage content of carbon is 3% to 15%.
  15. 15. semiconductor structure as claimed in claim 13, it is characterised in that the thickness on the barrier layer isExtremely
  16. 16. semiconductor structure as claimed in claim 13, it is characterised in that the semiconductor structure also includes：Bottom interlayer dielectric layer between the metal gate structure in substrate, the top of the bottom interlayer dielectric layer are higher than the top of the metal gate structure；
    The interlayer dielectric layer is located on the top of the bottom interlayer dielectric layer and metal gate structure；
    The contact hole plug also extends through the bottom interlayer dielectric layer.
  17. 17. semiconductor structure as claimed in claim 16, it is characterised in that the semiconductor structure also includes：Low K dielectric layer, at the top of the barrier layer, the top of the low K dielectric layer at the top of the bottom interlayer dielectric layer with flushing；
    The barrier layer is also located between the low K dielectric layer and bottom interlayer dielectric layer.
  18. 18. semiconductor structure as claimed in claim 17, it is characterised in that the thickness of the low K dielectric layer isExtremely
  19. 19. semiconductor structure as claimed in claim 17, it is characterised in that the material of the low K dielectric layer is SiON, SiOCN, SiBN or SiBCN.
  20. 20. semiconductor structure as claimed in claim 13, it is characterised in that the semiconductor structure is fin formula field effect transistor, and the substrate includes substrate and protrudes from the fin of the substrate；
    The metal gate structure is across the partial sidewall surface and top surface of the fin and the covering fin；
    The semiconductor structure also includes：Source and drain doping area in the fin of the metal gate structure both sides.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110534433A (en) * 2018-05-25 2019-12-03 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN111106158A (en) * 2018-10-29 2020-05-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN113644026A (en) * 2021-07-29 2021-11-12 上海华力集成电路制造有限公司 Method for improving threshold voltage adaptation and alternating current performance of FinFET device
CN114121658A (en) * 2020-08-28 2022-03-01 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102640291A (en) * 2009-12-30 2012-08-15 英特尔公司 Self-aligned contacts
CN104810368A (en) * 2014-01-28 2015-07-29 中芯国际集成电路制造(上海)有限公司 Cmos transistor and forming method thereof
CN105336589A (en) * 2014-05-27 2016-02-17 中芯国际集成电路制造(上海)有限公司 Formation method of transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102640291A (en) * 2009-12-30 2012-08-15 英特尔公司 Self-aligned contacts
CN104810368A (en) * 2014-01-28 2015-07-29 中芯国际集成电路制造(上海)有限公司 Cmos transistor and forming method thereof
CN105336589A (en) * 2014-05-27 2016-02-17 中芯国际集成电路制造(上海)有限公司 Formation method of transistor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110534433A (en) * 2018-05-25 2019-12-03 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN110534433B (en) * 2018-05-25 2023-09-22 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN111106158A (en) * 2018-10-29 2020-05-05 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN111106158B (en) * 2018-10-29 2023-11-10 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN114121658A (en) * 2020-08-28 2022-03-01 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN113644026A (en) * 2021-07-29 2021-11-12 上海华力集成电路制造有限公司 Method for improving threshold voltage adaptation and alternating current performance of FinFET device
CN113644026B (en) * 2021-07-29 2024-04-26 上海华力集成电路制造有限公司 Method for improving threshold voltage adaptation and alternating current performance of FinFET device

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