CN113644026A - Method for improving threshold voltage adaptation and alternating current performance of FinFET device - Google Patents

Method for improving threshold voltage adaptation and alternating current performance of FinFET device Download PDF

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CN113644026A
CN113644026A CN202110862502.5A CN202110862502A CN113644026A CN 113644026 A CN113644026 A CN 113644026A CN 202110862502 A CN202110862502 A CN 202110862502A CN 113644026 A CN113644026 A CN 113644026A
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side wall
finfet
dielectric layer
region
grid structure
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CN113644026B (en
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李勇
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a method for improving threshold voltage adaptation and alternating current performance of a FinFET device, which comprises a grid structure positioned between a source region epitaxial region and a drain region epitaxial region; a first interlayer dielectric layer covering the gate structure; flattening the grid structure to expose the top of the grid; back-etching the metal gate and the work function layer to form a groove; depositing a first barrier layer covering the groove, the grid structure and the first interlayer dielectric layer; forming an oxygen plug in the groove, and depositing a second barrier layer covering the first interlayer dielectric layer, the grid structure and the oxygen plug; forming a second interlayer dielectric layer on the second barrier layer; and respectively leading out contact lines in the epitaxial region of the source region and the epitaxial region of the drain region. The invention can improve the alternating current performance of the device; the fluorine is prevented from entering the high-K dielectric layer and reacting with oxygen to deteriorate the threshold voltage of the device; the isolation performance from the grid electrode to the metal layer is improved, and the yield of the SRAM and the logic circuit is improved; the process is simplified; the occurrence of cavities in the plug is avoided; the blocking effect is increased.

Description

Method for improving threshold voltage adaptation and alternating current performance of FinFET device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving threshold voltage adaptation and alternating current performance of a FinFET device.
Background
In the prior art FINFET manufacturing process, SiN is generally used as a plug of a gate, and the SiN plug has the advantage of improving the alternating current performance of the device; oxygen can be reduced, and fluorine enters the HK layer to react with oxygen, so that the threshold voltage of the device is deteriorated; the isolation performance from the grid electrode to the metal layer is improved, and the yield of the SRAM and the logic circuit is improved.
However, the use of SiN plugs also has the following problems: the deposition of SiN plugs often results in voids, especially as technology nodes shrink below 20 nm; when the SiN plug is ground, the residues of the SiN plug can enter the SiN cavity, so that the number of defects is increased; during the etching process of the metal gate contact hole, the SiN plug can be cracked due to the existence of the hole, and the threshold voltage of the device is unstable.
Therefore, a new method is needed to solve the above problems.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for improving threshold voltage adaptation and ac performance of a FinFET device, so as to solve the problem of device performance degradation caused by using a SiN plug during the FinFET device manufacturing process in the prior art.
To achieve the above and other related objects, the present invention provides a method for improving threshold voltage adaptation and ac performance of a FinFET device, comprising:
step one, providing an MOS structure, wherein the MOS structure at least comprises: a substrate; a source region epitaxial region and a drain region epitaxial region on the substrate; the grid structure is positioned between the source region epitaxial region and the drain region epitaxial region; the gate structure includes at least: a metal grid; a work function layer surrounding the side wall and the bottom of the metal gate; an inner sidewall attached to the sidewall of the work function layer; the SiN side wall is attached to the side wall of the inner side wall;
an outer side wall is formed on the side wall of the SiN side wall of the grid structure; a first interlayer dielectric layer covering the grid structure is formed on the substrate; carrying out upper surface planarization on the grid structure to expose the top of the grid;
step two, back-etching the metal gate and the work function layer to form a groove;
depositing a first barrier layer, wherein the first barrier layer covers the surface of the groove, the upper surface of the grid structure and the upper surface of the first interlayer dielectric layer;
step four, forming an oxygen plug in the groove, and grinding to flatten the upper surface of the oxygen plug;
depositing a second barrier layer, wherein the second barrier layer covers the first interlayer dielectric layer, the upper surface of the grid structure and the upper surface of the oxygen plug; forming a second interlayer dielectric layer on the upper surface of the second barrier layer;
and sixthly, respectively leading out contact lines in the epitaxial region of the source region and the epitaxial region of the drain region.
Preferably, the work function layer in step one comprises a HfO2 layer.
Preferably, the inner sidewall spacer in the first step is a low-K dielectric layer.
Preferably, the outer sidewall in the first step is a low-K dielectric layer.
Preferably, the dielectric constant of the inner sidewall spacer in the first step is about 5.
Preferably, the dielectric constant of the outer wall in the first step is about 5.
Preferably, the thickness of the SiN side wall in the first step is 2-8 nm.
Preferably, the SiN side wall and the outer side wall in the first step extend to the upper surfaces of the source region epitaxial region and the drain region epitaxial region.
Preferably, the method for planarizing the upper surface of the gate structure in the first step is a chemical mechanical polishing method.
Preferably, the first barrier layer in step three is one of SiN, SiON, SiC, SiCN, SiCBN, SiCOBN, Al2O3, ZrO 2.
Preferably, the method is used for processes of technology nodes of 7nm and above.
As described above, the method for improving the threshold voltage adaptation and the ac performance of the FinFET device of the present invention has the following beneficial effects: the method of the invention can improve the alternating current performance of the device; reducing oxygen, and avoiding fluorine from entering the high-K dielectric layer to react with oxygen to deteriorate the threshold voltage of the device; the isolation performance from the grid electrode to the metal layer is improved, and the yield of the SRAM and the logic circuit is improved; the grinding process of the SiN plug is omitted, so that the process is simplified; the SiN plug is replaced by the oxygen plug and the barrier layer, and the oxygen filling capacity is superior to that of the SiN plug, so that the occurrence of a cavity in the plug is avoided; the invention uses two barrier layers, thereby increasing the barrier effect.
Drawings
FIG. 1 is a schematic diagram of a MOS structure according to the present invention;
FIG. 2 is a schematic structural diagram of the metal gate and the work function layer after being etched back to form a groove in the present invention;
FIG. 3 is a schematic structural diagram of the present invention after a first barrier layer is formed;
FIG. 4 is a schematic view showing a structure after formation of an oxygen plug in the present invention;
FIG. 5 is a schematic structural diagram of the present invention after forming a second barrier layer and a second interlayer dielectric layer;
FIG. 6 is a schematic structural diagram of the present invention after contact lines are respectively led out from the epitaxial regions of the source region and the epitaxial regions of the drain region;
fig. 7 shows a flow chart of a method of improving threshold voltage adaptation and ac performance of a FinFET device in accordance with the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 7. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The present invention provides a method for improving threshold voltage adaptation and ac performance of a FinFET device, as shown in fig. 7, and fig. 7 is a flowchart illustrating a method for improving threshold voltage adaptation and ac performance of a FinFET device according to the present invention. The method at least comprises the following steps:
step one, providing an MOS structure, wherein the MOS structure at least comprises: a substrate; a source region epitaxial region and a drain region epitaxial region on the substrate; the grid structure is positioned between the source region epitaxial region and the drain region epitaxial region; the gate structure includes at least: a metal grid; a work function layer surrounding the side wall and the bottom of the metal gate; an inner sidewall attached to the sidewall of the work function layer; the SiN side wall is attached to the side wall of the inner side wall;
an outer side wall is formed on the side wall of the SiN side wall of the grid structure; a first interlayer dielectric layer covering the grid structure is formed on the substrate; carrying out upper surface planarization on the grid structure to expose the top of the grid;
as shown in fig. 1, fig. 1 is a schematic diagram of a MOS structure according to the present invention. The MOS structure in the first step at least includes: a substrate 01; a source region epitaxial region and a drain region epitaxial region (02) located on the substrate 01; the grid structure is positioned between the source region epitaxial region and the drain region epitaxial region; the gate structure includes at least: a metal grid 03; a work function layer surrounding the sidewall and bottom of the metal gate 03; an inner sidewall 04 attached to the sidewall of the work function layer; and the SiN side wall 05 is attached to the side wall of the inner side wall 04.
As shown in fig. 1, an outer sidewall 06 is formed on a sidewall of the SiN sidewall spacer 05 of the gate structure; a first interlayer dielectric layer 07 covering the gate structure is formed on the substrate 01;
further, the work function layer in the first step of this embodiment includes an HfO2 layer.
Further, in the present invention, the inner sidewall 04 in the first step of this embodiment is a low-K dielectric layer. The dielectric constant value of the inner side wall in the first step is about 5.
Further, in the present invention, the outer sidewall 06 in the first step of this embodiment is a low-K dielectric layer. The dielectric constant of outer wall 06 in step one is about 5.
Further, the thickness of the SiN sidewall spacer 05 in the first step of this embodiment is 2 to 8 nm. This thickness refers to the width of the SiN sidewall spacers 05 in fig. 1 in the lateral direction, i.e. the width of the SiN sidewall spacers to the left and right in the plane of fig. 1.
Further, in the present invention, in the first step of this embodiment, the SiN sidewall spacers 05 and the outer sidewall spacers 06 extend to the upper surfaces of the source region epitaxial region and the drain region epitaxial region 02.
The step of carrying out upper surface planarization on the grid structure to expose the top of the grid; as shown in fig. 1, the structure in fig. 1 is a schematic view of the gate structure after the gate structure has been planarized, and the top of the gate structure is exposed.
Further, the method for planarizing the upper surface of the gate structure in the second step of the present embodiment is a Chemical Mechanical Polishing (CMP) method.
Step two, back-etching the metal gate and the work function layer to form a groove; as shown in fig. 2, fig. 2 is a schematic structural diagram of the metal gate and the work function layer after being etched back to form a groove in the present invention. In this step two, the metal gate 03 and the work function layer are etched back to form a groove 08 as shown in fig. 2.
Depositing a first barrier layer, wherein the first barrier layer covers the surface of the groove, the upper surface of the grid structure and the upper surface of the first interlayer dielectric layer; as shown in fig. 3, fig. 3 is a schematic structural view after a first barrier layer is formed in the present invention. The first barrier layer 09 deposited in the third step covers the surface of the groove 08, the upper surface of the gate structure and the upper surface of the first interlayer dielectric layer 07.
Further, in the third step of this embodiment, the first barrier layer is one of SiN, SiON, SiC, SiCN, SiCBN, SiCOBN, Al2O3, and ZrO 2.
Step four, forming an oxygen plug in the groove, and grinding to flatten the upper surface of the oxygen plug; as shown in fig. 4, fig. 4 is a schematic view showing the structure of the present invention after the formation of the oxygen plug. In the fourth step, the oxygen plug 10 is formed on the first barrier layer 09 of the recess 08, and the upper surface thereof is planarized by polishing since the surface is not flat after the formation of the oxygen plug.
Depositing a second barrier layer, wherein the second barrier layer covers the first interlayer dielectric layer, the upper surface of the grid structure and the upper surface of the oxygen plug; forming a second interlayer dielectric layer on the upper surface of the second barrier layer; as shown in fig. 5, fig. 5 is a schematic structural diagram after forming a second barrier layer and a second interlayer dielectric layer in the present invention. In the fifth step, the second barrier layer 11 covers the first interlayer dielectric layer 07, the upper surface of the gate structure and the upper surface of the oxygen plug 10; and then forming the second interlayer dielectric layer 12 on the upper surface of the second barrier layer 11.
And sixthly, respectively leading out contact lines in the epitaxial region of the source region and the epitaxial region of the drain region. As shown in fig. 6, fig. 6 is a schematic structural diagram after contact lines are respectively led out from the source region epitaxial region and the drain region epitaxial region in the present invention. In the sixth step, contact lines 13 are respectively led out from the epitaxial regions of the source region and the epitaxial regions of the drain region.
Further, the method of the present embodiment is applied to the process of the technology node of 7nm and above.
In conclusion, the method of the invention can improve the alternating current performance of the device; reducing oxygen, and avoiding fluorine from entering the high-K dielectric layer to react with oxygen to deteriorate the threshold voltage of the device; the isolation performance from the grid electrode to the metal layer is improved, and the yield of the SRAM and the logic circuit is improved; the grinding process of the SiN plug is omitted, so that the process is simplified; the SiN plug is replaced by the oxygen plug and the barrier layer, and the oxygen filling capacity is superior to that of the SiN plug, so that the occurrence of a cavity in the plug is avoided; the invention uses two barrier layers, thereby increasing the barrier effect. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (11)

1. A method of improving threshold voltage adaptation and ac performance of a FinFET device, comprising:
step one, providing an MOS structure, wherein the MOS structure at least comprises: a substrate; a source region epitaxial region and a drain region epitaxial region on the substrate; the grid structure is positioned between the source region epitaxial region and the drain region epitaxial region; the gate structure includes at least: a metal grid; a work function layer surrounding the side wall and the bottom of the metal gate; an inner sidewall attached to the sidewall of the work function layer; the SiN side wall is attached to the side wall of the inner side wall;
an outer side wall is formed on the side wall of the SiN side wall of the grid structure; a first interlayer dielectric layer covering the grid structure is formed on the substrate; carrying out upper surface planarization on the grid structure to expose the top of the grid;
step two, back-etching the metal gate and the work function layer to form a groove;
depositing a first barrier layer, wherein the first barrier layer covers the surface of the groove, the upper surface of the grid structure and the upper surface of the first interlayer dielectric layer;
step four, forming an oxygen plug in the groove, and grinding to flatten the upper surface of the oxygen plug;
depositing a second barrier layer, wherein the second barrier layer covers the first interlayer dielectric layer, the upper surface of the grid structure and the upper surface of the oxygen plug; forming a second interlayer dielectric layer on the upper surface of the second barrier layer;
and sixthly, respectively leading out contact lines in the epitaxial region of the source region and the epitaxial region of the drain region.
2. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: the work function layer in the first step comprises an HfO2 layer.
3. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: and the inner side wall in the first step is a low-K dielectric layer.
4. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: and the outer side wall in the first step is a low-K dielectric layer.
5. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: the dielectric constant value of the inner side wall in the first step is about 5.
6. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: the dielectric constant of the outer wall in step one is about 5.
7. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: the thickness of the SiN side wall in the first step is 2-8 nm.
8. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: and the SiN side walls and the outer side walls in the first step extend to the upper surfaces of the source region epitaxial region and the drain region epitaxial region.
9. The method for fabricating an air sidewall spacer of a FinFET for reducing parasitic capacitance of claim 1, wherein: the method for flattening the upper surface of the grid structure in the first step is a chemical mechanical polishing method.
10. The method of claim 1, wherein the FinFET device comprises a threshold voltage adaptation circuit and an alternating current performance circuit, the method comprising: in the third step, the first barrier layer is one of SiN, SiON, SiC, SiCN, SiCBN, SiCOBN, Al2O3, and ZrO 2.
11. The method of claim 1, wherein the FinFET device comprises a threshold voltage adaptation circuit and an alternating current performance circuit, the method comprising: the method is used for the technology of the technical node of 7nm and above.
CN202110862502.5A 2021-07-29 2021-07-29 Method for improving threshold voltage adaptation and alternating current performance of FinFET device Active CN113644026B (en)

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US6235603B1 (en) * 1999-07-12 2001-05-22 Motorola Inc. Method for forming a semiconductor device using an etch stop layer
US20170103948A1 (en) * 2015-10-12 2017-04-13 Samsung Electronics Co., Ltd. Integrated circuit device and method of fabricating the same
CN107591366A (en) * 2016-07-06 2018-01-16 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN107591398A (en) * 2016-07-06 2018-01-16 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN108666267A (en) * 2017-04-01 2018-10-16 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6235603B1 (en) * 1999-07-12 2001-05-22 Motorola Inc. Method for forming a semiconductor device using an etch stop layer
US20170103948A1 (en) * 2015-10-12 2017-04-13 Samsung Electronics Co., Ltd. Integrated circuit device and method of fabricating the same
CN107591366A (en) * 2016-07-06 2018-01-16 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN107591398A (en) * 2016-07-06 2018-01-16 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN108666267A (en) * 2017-04-01 2018-10-16 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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