CN107919323A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
- Publication number
- CN107919323A CN107919323A CN201610884437.5A CN201610884437A CN107919323A CN 107919323 A CN107919323 A CN 107919323A CN 201610884437 A CN201610884437 A CN 201610884437A CN 107919323 A CN107919323 A CN 107919323A
- Authority
- CN
- China
- Prior art keywords
- layer
- nitrogenous
- opening
- work
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 89
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 239000010410 layer Substances 0.000 claims abstract description 574
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims abstract description 161
- 239000000463 material Substances 0.000 claims abstract description 103
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 74
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 72
- 239000004411 aluminium Substances 0.000 claims abstract description 39
- 239000011229 interlayer Substances 0.000 claims abstract description 35
- 230000008021 deposition Effects 0.000 claims abstract description 31
- 238000000151 deposition Methods 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 31
- 239000002184 metal Substances 0.000 claims description 31
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 28
- 230000008569 process Effects 0.000 claims description 27
- 239000007789 gas Substances 0.000 claims description 24
- 125000004433 nitrogen atom Chemical group N* 0.000 claims description 24
- 230000000802 nitrating effect Effects 0.000 claims description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 125000004429 atom Chemical group 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000005137 deposition process Methods 0.000 claims description 8
- 229910010038 TiAl Inorganic materials 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 229910017083 AlN Inorganic materials 0.000 claims description 6
- 229910004490 TaAl Inorganic materials 0.000 claims description 6
- 229910004491 TaAlN Inorganic materials 0.000 claims description 6
- 229910010041 TiAlC Inorganic materials 0.000 claims description 6
- 229910010037 TiAlN Inorganic materials 0.000 claims description 6
- 229910003074 TiCl4 Inorganic materials 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000005121 nitriding Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 21
- 230000004888 barrier function Effects 0.000 description 21
- 238000002955 isolation Methods 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 230000006870 function Effects 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 239000000377 silicon dioxide Substances 0.000 description 10
- 239000003989 dielectric material Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 230000009931 harmful effect Effects 0.000 description 7
- 238000004062 sedimentation Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- 229910010271 silicon carbide Inorganic materials 0.000 description 6
- 238000010276 construction Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 229910008482 TiSiN Inorganic materials 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- -1 Oxonium ion Chemical class 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, the described method includes：Substrate is provided, including for forming the first area of the first transistor and second area for forming second transistor, the channel length of the first transistor is less than the channel length of second transistor；Interlayer dielectric layer is formed in substrate；The first opening and the second opening are formed in interlayer dielectric layer；Gate dielectric layer is formed in the first open bottom and side wall and on the second open bottom and side wall；The first nitrogenous layer is formed on second area gate dielectric layer；Work-function layer of the material containing aluminium is formed on first area gate dielectric layer and the first nitrogenous layer.The present invention is by forming the first nitrogenous layer, reduce deposition capability of the aluminium atom in the second opening, the problem of wide more inconsistent than the inconsistent aluminium atom deposition capability brought, is indulged by opening to make up, makes the work-function layer thickness of the first transistor and second transistor suitable and aluminium content is suitable.
Description
Technical field
The present invention relates to semiconductor applications, more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
The main semiconductor devices of integrated circuit especially super large-scale integration is Metal-oxide-semicondutor field effect
It should manage (MOS transistor).With the continuous development of production of integrated circuits technology, semiconductor device art node constantly reduces, and half
The physical dimension of conductor device follows Moore's Law and constantly reduces.It is various when dimensions of semiconductor devices reduces to a certain extent
Because second-order effect caused by the physics limit of semiconductor devices occurs in succession, the characteristic size of semiconductor devices contracts in proportion
It is small to become more and more difficult.Wherein, in field of semiconductor fabrication, most challenging is how to solve semiconductor device creepage
The problem of big.The leakage current of semiconductor devices is big, caused mainly by the constantly reduction of traditional gate dielectric layer thickness.
The solution method currently proposed is to replace traditional silicon dioxide gate dielectric material using high-k gate dielectric material, and
Using metal as gate electrode, fermi level pinning effect occurs with conventional gate electrodes material to avoid high-g value and boron oozes
Penetration effect.The introducing of high-k/metal gate, reduces the leakage current of semiconductor devices.
It is existing although the introducing of high-k/metal gate can improve the electric property of semiconductor devices to a certain extent
The electric property for having the semiconductor devices of technology formation still has much room for improvement.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of semiconductor structure and forming method thereof, optimize the electricity of semiconductor devices
Performance.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided, it is described
Substrate includes being used for the first area for forming the first transistor and second area for forming second transistor, and described first
The channel region length of transistor is less than the channel region length of the second transistor；Interlayer dielectric layer is formed on the substrate；
The first opening for exposing the first area substrate is formed in the interlayer dielectric layer and exposes the second area substrate
Second opening；Gate medium is formed on the bottom of the described first opening and side wall and on the bottom of the second opening and side wall
Layer；The first nitrogenous layer is formed on the second area gate dielectric layer；On the first area gate dielectric layer and described
Work-function layer of the material containing aluminium is formed on one nitrogenous layer；Full first opening of filling and second are formed in the work-function layer
The metal layer of opening.
Optionally, the material of first nitrogenous layer is TiN.
Optionally, the thickness of first nitrogenous layer isExtremely
Optionally, in the step of forming the first nitrogenous layer on the second area gate dielectric layer, in the first area
The second nitrogenous layer is formed on gate dielectric layer, wherein the mass percentage content of nitrogen-atoms is less than described the in second nitrogenous layer
The mass percentage of nitrogen-atoms in one nitrogenous layer.
Optionally, the thickness of second nitrogenous layer isExtremely
Optionally, the material of first nitrogenous layer and the second nitrogenous layer is TiN；Form first nitrogenous layer and second
The step of nitrogenous layer, includes：Ti layers are formed on the gate dielectric layer；To described Ti layers progress nitrating technique, by segment thickness
Ti layers change into TiN layer.
Optionally, thickness Ti layers described isExtremely
Optionally, it is chemical vapor deposition method to form technique Ti layers described.
Optionally, the parameter of the chemical vapor deposition method includes：Reacting gas is TiCl4And H2, TiCl4Gas
Flow is 10sccm to 100sccm, H2Gas flow be 2000sccm to 4000scm, reaction temperature is 400 DEG C to 600, work(
Rate is 600W to 1000W, and pressure is 2Torr to 6Torr.
Optionally, the nitrating technique is plasma nitridation process.
Optionally, reacting gas is N used by the plasma nitridation process2Or NH3。
Optionally, the parameter of the plasma nitridation process includes：Power is 600W to 1000W, pressure for 2Torr extremely
6Torr, process time are 2s to 6s, and the gas flow of reacting gas is 500sccm to 1000sccm.
Optionally, the material of the work-function layer is TiAl, TaAl, TiAlC, AlN, TiAlN or TaAlN.
Optionally, the technique for forming the work-function layer is atom layer deposition process.
Correspondingly, the present invention also provides semiconductor structure, including：Substrate, the substrate are included with the first transistor
First area and the second area with second transistor, the channel region length of the first transistor are less than the described second crystalline substance
The channel region length of body pipe；Interlayer dielectric layer in the substrate, has in the interlayer dielectric layer and exposes described first
First opening of substrate areas and the second opening for exposing the second area substrate；First in the described first opening
Gate structure, including gate dielectric layer in first open bottom and side wall, on the gate dielectric layer and material
Work-function layer containing aluminium, and in the work-function layer and full first opening of filling metal layer；Positioned at described
Second grid structure in second opening, including gate dielectric layer in second open bottom and side wall, positioned at described
The first nitrogenous layer on gate dielectric layer, on first nitrogenous layer and work-function layer of the material containing aluminium, and positioned at described
In work-function layer and the metal layer of second opening is expired in filling.
Optionally, the material of first nitrogenous layer is TiN.
Optionally, the thickness of first nitrogenous layer isExtremely
Optionally, the material of the work-function layer is TiAl, TaAl, TiAlC, AlN, TiAlN or TaAlN.
Optionally, the first grid structure further includes：Between the first area gate dielectric layer and work-function layer
The second nitrogenous layer, the material identical of the material of second nitrogenous layer and first nitrogenous layer, and second nitrogenous layer
The mass percentage content of middle nitrogen-atoms is less than the mass percentage of nitrogen-atoms in first nitrogenous layer.
Optionally, the thickness of second nitrogenous layer isExtremely
Compared with prior art, technical scheme has the following advantages：
The present invention is opened by forming the first nitrogenous layer on second area gate dielectric layer with reducing aluminium atom described second
Deposition capability in mouthful, width is indulged than the inconsistent influence brought to make up by opening, therefore can be made in the work-function layer
Aluminium atom is suitable with the deposition capability in the second opening in the described first opening, so that the first transistor and the second crystalline substance
The work-function layer thickness of body pipe is suitable, and aluminium content is suitable in the work-function layer of the first transistor and second transistor, and then
Make the threshold voltage of the first transistor and second transistor suitable, avoid the first transistor because work-function layer thickness compared with
It is small, aluminium content is relatively low and the problem of causing threshold voltage higher.
In alternative, in the step of forming the first nitrogenous layer on second area gate dielectric layer, in first area, grid are situated between
Form the second nitrogenous layer on matter layer, first nitrogenous layer and the second nitrogenous layer by carry out nitrating techniques to Ti layers with convert and
Into the mass percentage content of nitrogen-atoms is less than the quality percentage of nitrogen-atoms in first nitrogenous layer in second nitrogenous layer
Content, and the mass percentage of nitrogen-atoms is bigger, the effect for reducing aluminium atom deposition capability is more obvious；Therefore by controlling
The mass percentage of the first nitrogenous layer and the nitrogen-atoms in the second nitrogenous layer is stated, width is indulged by opening so as to relatively well make up
Than the inconsistent influence brought, deposition capability of the balance aluminium atom in the described first opening and in the second opening.
In alternative, the material of first nitrogenous layer is TiN, is formed and Ti elements are included in the material of gate structure
And N element, therefore can have preferable processing compatibility with forming transistor to avoid the introducing of impurity element, TiN materials,
So as to avoid the electric property to semiconductor devices from producing harmful effect.
The present invention provides a kind of semiconductor structure, including in second grid structure between gate dielectric layer and work-function layer
The first nitrogenous layer, first nitrogenous layer advantageously reduce aluminium atom described second opening in deposition capability it is poor, more
Mend and width is indulged than the inconsistent influence brought by opening, so as to so that aluminium atom is open in interior and the second opening described first
Deposition capability is suitable, therefore the work-function layer thickness of the first transistor and second transistor is suitable and aluminium content is suitable, into
And make the threshold voltage of the first transistor and second transistor suitable, the first transistor is avoided because of work-function layer thickness
It is smaller, aluminium content is relatively low and the problem of causing threshold voltage higher.
Brief description of the drawings
Fig. 1 be aluminium sedimentation rate and nitrogenous layer in the concentration dependent change curve of nitrating；
Fig. 2 to Fig. 9 be semiconductor structure of the present invention one embodiment of forming method in each step counter structure schematic diagram.
Embodiment
From background technology, the electric property of semiconductor devices still has much room for improvement.With reference to a kind of shape of semiconductor structure
Its reason is analyzed into method.
The forming method includes：Substrate is provided, the substrate include being used for being formed the first area of the first transistor with
And for forming the second area of second transistor, the channel region length of the first transistor is less than the second transistor
Channel region length；Interlayer dielectric layer is formed on the substrate；Formed in the interlayer dielectric layer and expose the first area
First opening of substrate and the second opening for exposing the second area substrate；On the bottom and side wall of the described first opening
And second opening bottom and side wall on form gate dielectric layer；Work-function layer is formed on the gate dielectric layer；In the work(
The metal layer of full first opening of filling and the second opening is formed on function layer.
The first transistor is short channel device, and the second transistor is long channel device, therefore described first opens
Mouthful opening size be less than the opening size of the described second opening, correspondingly, first opening is vertical wide than being more than described the
The vertical wide ratio of two openings.
Using formation material on gate dielectric layer of the ALD process in the described first opening and in the second opening containing Al's
During work-function layer, since the atomic volume of Al in presoma containing Al is larger, presoma containing Al is difficult to open into described first
In mouthful, so as to cause deposition capabilities of the Al in the described first opening poor, and then cause the thickness of first area work-function layer
Less than the thickness of second area work-function layer, and the atomic mass degree of Al is less than second in the work-function layer of first area
The atomic mass degree of Al in regional work functions layer.
Wherein, the atomic mass degree of Al and the work function value of work-function layer inversely, work-function layer
Thickness and work function value inversely, and since the atomic mass degree of Al in the work-function layer of first area is smaller,
And the thickness of first area work-function layer is less than the thickness of second area work-function layer, therefore the first area work-function layer
Work function value is more than the work function value of the second area work-function layer, so as to cause the first transistor threshold voltage occur
Higher phenomenon, and then cause the repugnant problem of electric property of the first transistor and second transistor.
In order to solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：Base is provided
Bottom, the substrate include being used for the first area for forming the first transistor and the second area for forming second transistor,
The channel region length of the first transistor is less than the channel region length of the second transistor；Interlayer is formed on the substrate
Dielectric layer；The first opening for exposing the first area substrate is formed in the interlayer dielectric layer and exposes secondth area
Second opening of domain substrate；Grid are formed on the bottom of the described first opening and side wall and on the bottom of the second opening and side wall
Dielectric layer；The first nitrogenous layer is formed on the second area gate dielectric layer；On the first area gate dielectric layer and institute
State formation work-function layer of the material containing aluminium on the first nitrogenous layer；Formed in the work-function layer full first opening of filling and
The metal layer of second opening.
As shown in Figure 1, Fig. 1 show aluminium sedimentation rate and nitrogenous layer in the concentration dependent change curve of nitrating, it is horizontal
Coordinate representation nitrating concentration, ordinate represent the sedimentation rate of aluminium；Nitrating concentration is higher in nitrogenous layer, and aluminium is on the nitrogenous layer
Sedimentation rate it is smaller, i.e., deposition capability is poorer.So the present invention is nitrogenous by forming first on second area gate dielectric layer
Layer, to reduce deposition capability of the aluminium atom in the described second opening, with make up indulged by opening it is wide than the inconsistent influence brought,
Therefore the aluminium atom in the work-function layer can be made suitable with the deposition capability in the second opening in the described first opening, from
And make the work-function layer thickness of the first transistor and second transistor suitable, the first transistor and second transistor
Aluminium content is suitable in work-function layer, and then makes the threshold voltage of the first transistor and second transistor suitable, avoids described
The first transistor because work-function layer thickness is smaller, aluminium content is relatively low cause threshold voltage higher the problem of.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 2 to Fig. 9 be semiconductor structure of the present invention one embodiment of forming method in each step counter structure schematic diagram.
With reference to figure 2, there is provided substrate, the substrate include being used to form the first area I of the first transistor and for shape
Into the second area II of second transistor, the channel region length of the first transistor is less than the channel region of the second transistor
Length.
In the present embodiment, the substrate is used to form fin field effect pipe transistor, therefore the substrate includes substrate 100
And the discrete fin 110 on substrate 100.Specifically, the first area I substrates are used to form the first N-type transistor,
The second area II substrates are used to form the second N-type transistor；First N-type transistor is short-channel transistor, described
Second N-type transistor is long channel MOSFET.
In other embodiments, the substrate can be also used for forming planar transistor, and the substrate is planar substrates.
The first area I and second area II can be adjacent area, or non-conterminous region.The present embodiment
In, the first area I and second area II are non-conterminous area.
In the present embodiment, the substrate 100 is silicon substrate.In other embodiments, the material of the substrate can also be
Germanium, SiGe, carborundum, GaAs or gallium indium, the substrate can also be on silicon substrate or insulator on insulator
Germanium substrate.
The material identical of the material of the fin 110 and the substrate 100.In the present embodiment, the material of the fin 110
For silicon.In other embodiment, the material of the fin can also be germanium, SiGe, carborundum, GaAs or gallium indium.
Specifically, forming the processing step of the substrate 100 and fin 110 includes：Initial substrate is provided；Described initial
Substrate surface forms patterned hard mask layer (not shown)；Using the hard mask layer as initial substrate described in mask etching, shape
Into substrate 100 and protrude from the fin 110 on 100 surface of substrate.
In the present embodiment, after forming the substrate 100 and fin 110, retain the hard mask layer positioned at the top of fin 110.
The material of the hard mask layer is silicon nitride, and subsequently when carrying out planarization process technique, the hard mask layer top surface is used
In the stop position of definition planarization process technique, and play the role of protecting the top of fin 110.
It should be noted that after forming the substrate 100 and fin 110, the forming method further includes：Adjacent described
Isolation structure 101 is formed on substrate 100 between fin 110, the top of isolation structure 101 is less than the top of fin 110.
Isolation structure of the isolation structure 101 as semiconductor devices, for playing buffer action to adjacent devices.This
In embodiment, the material of the isolation structure 101 is silica.In other embodiments, the material of the isolation structure may be used also
Think silicon nitride or silicon oxynitride.
Specifically, forming the processing step of the isolation structure 101 includes：Substrate between the adjacent fin 110
Full isolation film is filled on 100, is higher than at the top of the isolation film at the top of hard mask layer (not shown)；Grinding is removed to be covered firmly higher than described
Isolation film at the top of film layer；The remaining isolation film of segment thickness is removed, forms the isolation structure 101, the isolation structure 101
Top is less than the top of fin 110；Remove the hard mask layer.
With continued reference to Fig. 2, it is necessary to which explanation, after forming the isolation structure 101, the forming method further includes：Shape
Into the first pseudo- grid structure 121 across the first area I fins 110 and covering 110 atop part of fin and sidewall surfaces；Shape
Into the second pseudo- grid structure 122 across the second area II fins 110 and covering 110 atop part of fin and sidewall surfaces.
The first pseudo- grid structure 121 is that the gate structure for being subsequently formed the first N-type transistor takes up space position, described
Second pseudo- grid structure 122 is that the gate structure for being subsequently formed the second N-type transistor takes up space position.
Described first pseudo- grid structure 121 is single layer structure or laminated construction, and the described second pseudo- grid structure 122 is single layer structure
Or laminated construction.Described first pseudo- 121 and second pseudo- grid structure 122 of grid structure includes pseudo- grid layer；Or the first puppet grid
The pseudo- grid structure 122 of structure 121 and second includes pseudo- oxide layer and the pseudo- grid layer in the pseudo- oxide layer.Wherein, institute
The material for stating pseudo- grid layer is polysilicon, silica, silicon nitride, silicon oxynitride, carborundum, carbonitride of silicium, carbon silicon oxynitride or non-
Brilliant carbon, the material of the puppet oxide layer is silica or silicon oxynitride.
In the present embodiment, after forming the described first pseudo- 121 and second pseudo- grid structure 122 of grid structure, the forming method is also
Including：Side wall 130 is formed on the side wall of the described first pseudo- 121 and second pseudo- grid structure 122 of grid structure；Form the side wall
After 130, the interior fin 110 with the second pseudo- 122 both sides of grid structure of fin 110 respectively in the described first pseudo- 121 both sides of grid structure
Interior formation source and drain doping area 140.
The material of the side wall 130 can be silica, silicon nitride, carborundum, carbonitride of silicium, carbon silicon oxynitride, nitrogen oxygen
SiClx, boron nitride or boron carbonitrides；The side wall 130 can be single layer structure or laminated construction.In the present embodiment, the side wall
130 be single layer structure, and the material of the side wall 130 is silicon nitride.
In the present embodiment, the substrate is used to form the first N-type transistor and the second N-type transistor.Correspondingly, the source
The Doped ions for leaking doped region 140 are N-type ion, are, for example, P, As or Sb.
With continued reference to Fig. 2, interlayer dielectric layer 150 is formed on the substrate.
The material of the interlayer dielectric layer 150 is insulating materials.In the present embodiment, the material of the interlayer dielectric layer 150
For silica.In other embodiments, the material of the interlayer dielectric layer can also be silicon nitride, silicon oxynitride, silicon oxide carbide,
Carbonitride of silicium or carbon silicon oxynitride.
In the present embodiment, on the substrate 100 between the described first pseudo- grid structure 121 between the second pseudo- grid structure 122
The interlayer dielectric layer 150 is formed, the interlayer dielectric layer 150 covers the described first pseudo- 121 and second pseudo- grid structure of grid structure
122 side walls, and the top of the interlayer dielectric layer 150 and the described first pseudo- pseudo- 122 top of grid structure of grid structure 121 and second are neat
It is flat.
With reference to figure 3, formed in the interlayer dielectric layer 150 expose the first opening 151 of the first area I substrates with
And expose the second opening 152 of the second area II substrates.
First opening 151 provides locus to be subsequently formed the gate structure of the first N-type transistor, and described second
Opening 152 provides locus to be subsequently formed the gate structure of the second N-type transistor.
In the present embodiment, formed in the first area I interlayer dielectric layers 150 and expose the first area I fins 110
First opening 151, in the second area II interlayer dielectric layers 150 formed expose the second area II fins 110
Second opening 152.
Specifically, the step of forming first opening 151 and the second opening 152 includes：Remove the described first pseudo- grid knot
Structure 121 (as shown in Figure 2), forms in the first area I interlayer dielectric layers 150 and exposes the first area I fins 110
First opening 151；The described second pseudo- grid structure 122 (as shown in Figure 2) is removed, in the second area II interlayer dielectric layers 150
It is middle to form the second opening 152 for exposing the second area II fins 110.
In the present embodiment, it is combined using dry etch process, wet etching or dry etch process and wet etching
Technique, removes the described first pseudo- 121 and second pseudo- grid structure 122 of grid structure.Since the etching technics is to the described first pseudo- grid
The pseudo- grid structure 122 of structure 121 and second has higher etching selection ratio, that is to say, that the etching technics is pseudo- to described first
The etch rate of the pseudo- grid structure 122 of grid structure 121 and second is more than the etch rate to the interlayer dielectric layer 150, so
When removing described first pseudo- grid structure 121 and the second pseudo- grid structure 122, it can be reduced to institute using the way of the etching technics
State the loss of interlayer dielectric layer 150.
With reference to figure 4, on the bottom of the described first opening 151 and side wall and second is open on 152 bottom and side wall
Form gate dielectric layer 220.
Specifically, the step of forming gate dielectric layer 220 includes：Described first opening 151 bottoms and side wall and
Gate dielectric layer 220 is formed on second 152 bottoms of opening and side wall, the gate dielectric layer 220 also covers the interlayer dielectric layer 150
Top.
In the present embodiment, the material of the gate dielectric layer 220 is high-k gate dielectric material, wherein, high-k gate dielectric material refers to
, gate dielectric material of the relative dielectric constant more than silica relative dielectric constant.
The gate dielectric layer 220 is formed using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process.This reality
Apply in example, the material of the gate dielectric layer 220 is HfO2, the gate dielectric layer 220 is formed using atom layer deposition process.At it
In his embodiment, the material of the gate dielectric layer can also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2Or
Al2O3。
It should be noted that before the gate dielectric layer 220 is formed, the forming method further includes：Described first
Be open 151 bottoms and the second opening 152 bottoms formation boundary layer (IL, Interfacial Layer) 211.
On the one hand, the boundary layer 211 can be as the follow-up part for forming gate structure, with the high-k gate dielectric
Layer 220 forms the gate dielectric layer of laminated construction；On the other hand, the boundary layer 211 provides boundary to form high-k gate dielectric layer 220
Face basis, so as to improve the quality of formed high-k gate dielectric layer 220, reduces between the high-k gate dielectric layer 220 and fin 110
Interface state density, and avoid the high-k gate dielectric layer 220 directly contacted with fin 110 caused by harmful effect.
In the present embodiment, the boundary layer 211 is formed using thermal oxidation technology, the material of the boundary layer 211 is oxidation
Silicon.In another embodiment, the material of the boundary layer can also be silicon oxynitride.
Correspondingly, in the step of forming gate dielectric layer 220, in the described first 151 side walls of opening, the second opening 152
Side wall, first are open on the boundary layer 211 of 151 bottoms and form the grid on the boundary layer 211 of the second 152 bottoms of opening
Dielectric layer 220.
With reference to reference to figure 5, it is necessary to explanation, after forming the gate dielectric layer 220, the forming method further includes：
Cap 230 is formed on the gate dielectric layer 220.
In the present embodiment, the cap 230 not only plays a protective role the gate dielectric layer 220, avoids follow-up work(
Metal ion in function layer is diffused in the gate dielectric layer 220；Also, it is also prevented from the gate dielectric layer 220
Oxonium ion is diffused in the work-function layer, so that the problem of improving Lacking oxygen content increase in the gate dielectric layer 220.
In the present embodiment, the material of the cap 230 is TiN, can form the lid using atom layer deposition process
Cap layers 230.In other embodiments, the material of the cap can also be TiSiN or TaN, and formation process can also be thing
Physical vapor deposition technique or chemical vapor deposition method.
First opening, 151 and second opening 152 provides locus for follow-up filling metal layer, is ensureing the lid
While cap layers 230 can play a protective role to the gate dielectric layer 220, also need to avoid the cap 230 from occupying too much
The space of first opening, 151 and second opening 152, therefore the thickness of the cap 230 is unsuitable too small, also should not mistake
Greatly.In the present embodiment, the thickness of the cap 230 isExtremely
With reference to reference to figure 6 and Fig. 7,242 (such as Fig. 7 of the first nitrogenous layer is formed on the second area II gate dielectric layers 220
It is shown).
First nitrogenous layer 242 has the function that to suppress follow-up work-function layer formation.
When being subsequently formed work-function layer of the material containing aluminium, since deposition capability of the aluminium atom on nitrogenous layer is poor, and nitrogen
The mass percentage content of atom is higher, and the deposition capability of aluminium atom is poorer, therefore by forming first nitrogenous layer 242,
Sedimentation rate of the aluminium atom on the second area II gate dielectric layers 220 can be reduced, so as to reduce formed second area
The thickness of II work-function layers, reduces the mass percentage content for forming aluminium atom in second area II work-function layers.
Further, since the vertical wide vertical wide ratio than more than the described second opening 152 of first opening 151, is subsequently formed
During work-function layer of the material containing aluminium, under the conditions of same process, deposition capability of the aluminium atom in the described first opening 151 compared with
Difference, compared to second opening 152 formed in work-function layer, first opening 151 formed in work-function layer thickness it is smaller and
Aluminium content is relatively low.Therefore by first nitrogenous layer 242, the vertical width by the first opening 151 and the second opening 152 can be made up
Than the inconsistent influence brought, so that the work-function layer thickness in first opening, 151 and second opening 152 is quite and aluminium
Content is suitable.
In the present embodiment, in the step of forming the first nitrogenous layer 242 on the second area II gate dielectric layers 220,
The second nitrogenous layer 241 (as shown in Figure 7) is formed on the first area I gate dielectric layers 220, wherein second nitrogenous layer 241
The mass percentage content of middle nitrogen-atoms is less than the mass percentage of nitrogen-atoms in first nitrogenous layer 242, correspondingly, institute
The thickness for stating the second nitrogenous layer 241 is less than the thickness of first nitrogenous layer 242.
The mass percentage content of nitrogen-atoms is higher, and the deposition capability of aluminium atom is poorer in work-function layer, by controlling
The mass percentage of nitrogen-atoms in the first nitrogenous layer 242 and the second nitrogenous layer 241 is stated, so as to further compensate for by first
151 and second opening 152 of opening it is vertical wide than the inconsistent influence brought, balance aluminium atom is in the described first opening 151 and the
Deposition capability in two openings 152.
In the present embodiment, the material of first nitrogenous layer 242 is TiN, correspondingly, the material of second nitrogenous layer 241
Material is also TiN.
It should be noted that the thickness of first nitrogenous layer 242 is unsuitable too small, also should not be too large.If described first
The thickness of nitrogenous layer 242 is too small, when being subsequently formed work-function layer, suppresses the effect unobvious that work-function layer is formed, so as to cause
It is difficult to make up by the vertical width of the first opening 151 and the second opening 152 than the inconsistent influence brought；If first nitrogenous layer
242 thickness is excessive, can accordingly occupy the space of second opening 152 too much, exist so as to be easily reduced subsequent metal layer
Filling capacity in second opening 152.For this reason, in the present embodiment, the thickness of first nitrogenous layer 242 isExtremely
In order to balance deposition capability of the aluminium atom in the described first opening 151 and the second opening 152, described second is nitrogenous
The thickness of the thickness and first nitrogenous layer 242 of layer 241 matches, and in order to avoid second nitrogenous layer 241 too much
The space of first opening 151 is occupied, in the present embodiment, the thickness of second nitrogenous layer 241 isExtremely
Specifically, the step of forming 242 and second nitrogenous layer 241 of the first nitrogenous layer includes：In the gate dielectric layer
Ti layers 240 (as shown in Figure 6) are formed on 230；Nitrating technique is carried out to the Ti layers 240, the Ti layers 240 of segment thickness are converted
Into TiN layer；Wherein, the TiN layer in the described first opening 151 is the second nitrogenous layer 241, positioned at the described second opening 152
In TiN layer be the first nitrogenous layer 242.
It should be noted that in order to ensure to be formed successional Ti layers 240, it is discontinuous to avoid the occurrence of the growth of Ti layers 240
Situation, the thickness of the Ti layers 240 are unsuitable excessively thin.In the present embodiment, the thickness of the Ti layers 240 is more than required formation first and contains
The thickness of nitrogen layer 242.Specifically, the thickness of the Ti layers 240 isExtremely
In the present embodiment, the technique for forming the Ti layers 240 is chemical vapor deposition method.Specifically, the chemical gas
The parameter of phase depositing operation includes：Reacting gas is TiCl4And H2, TiCl4Gas flow be 10sccm to 100sccm, H2's
Gas flow is 2000sccm to 4000scm, and reaction temperature is 400 DEG C to 600 DEG C, and power is 600W to 1000W, and pressure is
2Torr to 6Torr.
In other embodiments, it can also be atom layer deposition process or physical vapour deposition (PVD) to form technique Ti layers described
Technique.
In the present embodiment, the nitrating technique is plasma nitridation process, and the plasma nitridation process is used
Reacting gas be N2Or NH3, so as to form the first nitrogenous layer 242 and the second nitrogenous layer 241 that material is TiN.
The gas flow of the reacting gas influences to change into segment thickness Ti layers 240 into the effect of TiN layer, that is, influences institute
State nitrogen-atoms mass percentage content in the first nitrogenous layer 242 and the second nitrogenous layer 241, therefore the gas stream of the reacting gas
Amount is unsuitable too small, also should not be too large.In the present embodiment, the gas flow of the reacting gas is 500sccm to 1000sccm.
In addition, meet the first nitrogenous layer 242 of process requirements to form thickness and nitrogen-atoms mass percentage content
With the second nitrogenous layer 241, power, pressure and the process time of the plasma nitridation process also need control in zone of reasonableness
It is interior.In the present embodiment, the power of the plasma nitridation process is 600W to 1000W, and pressure is 2Torr to 6Torr, technique
Time is 2s to 6s.
It should be noted that during the plasma nitridation process, due to the opening size of the described first opening 151
Less than the opening size of the described second opening 152, the Ti layers in plasma nitridation process are exposed in second opening 152
240 surface area biggers, Ti layers 240 are easier to be influenced be subject to plasma in second opening 152, therefore the plasma
Body nitriding process is more preferable to the nitrating effect of Ti layers 240 in the described second opening 152, so as to fulfill nitrogen in the first nitrogenous layer 242
The mass percentage of atom is more than the effect of the mass percentage content of nitrogen-atoms in the second nitrogenous layer 241, and described first
The thickness of nitrogenous layer 242 is more than the thickness of second nitrogenous layer 241.
It should also be noted that, in the present embodiment, using remote plasma treatment (Remote Plasma
Treatment) to carry out nitrating.Its medium-long range refers to：Beyond the chamber of nitrating technique, reacting gas is set to form plasma
Body, that is to say, that form plasma and nitrating carries out in differential responses chamber, so as to avoid the formation of plasma
Technique produces harmful effect to nitrating effect.
In addition, include Ti elements and N element in the follow-up material for forming gate structure, therefore use TiN materials can be with
Avoid the introducing of impurity element, Ti materials and TiN materials and transistor that there is preferable processing compatibility, correspondingly, can keep away
Exempt to produce harmful effect to the electric property of semiconductor devices.
In the present embodiment, first area I and second area the II gate dielectric layer 220 is respectively formed on nitrogenous layer.Another
In embodiment, only nitrogenous layer can also be formed on the second area gate dielectric layer；Correspondingly, when forming the nitrogenous layer,
Not only it can also can directly form TiN layer by the way of nitrating is carried out to Ti layers.
In the present embodiment, formed with cap 230 on the gate dielectric layer 220, therefore first nitrogenous layer 242 is formed
In the step of the second nitrogenous layer 241, second nitrogenous layer 241 is formed in the first area I cap 230, in institute
State and first nitrogenous layer 242 is formed in second area II cap 230.
With reference to figure 8, material is formed on the first area I gate dielectric layers 220 and on first nitrogenous layer 242 and is contained
The work-function layer 250 of aluminium.
The work-function layer 250 is used for the threshold voltage for adjusting transistor.
In the present embodiment, the substrate includes being used for the first area I for forming the first N-type transistor and for forming the
The second area II of two N-type transistors, correspondingly, the first area I work-function layers 250 and second area II work-function layers
250 be N-type work function material, and N-type work function material workfunction range is 3.9eV to 4.5eV, be, for example, 4eV, 4.1eV or
4.3eV。
The material of the work-function layer 250 can be TiAl, TaAl, TiAlC, AlN, TiAlN or TaAlN.The present embodiment
In, the material of the work-function layer 250 is TiAl, and the work-function layer 250 can be formed using atom layer deposition process.At it
In his embodiment, chemical vapor deposition method or physical gas-phase deposition can also be used to form the work-function layer.
In the present embodiment, formed with the second nitrogenous layer 241 on the first area I gate dielectric layers 220, therefore described in formation
In the step of work-function layer 250, the work-function layer is formed on second nitrogenous layer 241 and first nitrogenous layer 242
250。
It should be noted that since second nitrogenous layer 241 and first nitrogenous layer 242 can make up and be opened by first
Mouthfuls 151 and second opening 152 vertical wide than the inconsistent influence brought, therefore the thickness of the first area I work-function layers 250
It is suitable with the thickness of the second area II work-function layers 250, and the aluminium content in the first area I work-function layers 250 with
Aluminium content in the second area II work-function layers 250 is suitable.
In the present embodiment, the thickness of the work-function layer 250 isExtremelyWork content in i.e. described first opening 151
Several layers 250 of thickness isExtremelyThe thickness of work-function layer 250 is in second opening 152Extremely
It should also be noted that, after forming the work-function layer 250, the forming method further includes：In the work function
Barrier layer (not shown) is formed on layer 250.
The barrier layer is used to play a protective role to the work-function layer 250.Subsequently in the described first opening 151 and the
When filling metal layer in two openings 152, it is described that the barrier layer can prevent that the easy diffusion ion in the metal layer from diffusing to
In work-function layer 250, so as to avoid causing harmful effect to the performance of the work-function layer 250.
In the present embodiment, the material on the barrier layer is TiN, can form the stop using atom layer deposition process
Layer.In other embodiments, the material on the barrier layer can also be TiSiN, and formation process can also be using physical vapor
Depositing operation or chemical vapor deposition method.
First opening, 151 and second opening 152 provides locus for follow-up filling metal layer, is ensureing the resistance
While barrier can play a protective role to the work-function layer 250, also need to avoid the barrier layer from excessively occupying described
The space of one opening 151 and the second opening 152, therefore the thickness on the barrier layer is unsuitable too small, also should not be too large.The present embodiment
In, the thickness on the barrier layer isExtremely
With reference to figure 9, full first opening, 151 (as shown in Figure 8) and second of filling are formed in the work-function layer 250
The metal layer 260 of 152 (as shown in Figure 8) of opening.
In the present embodiment, formed with barrier layer in the work-function layer 250, correspondingly, forming the step of the metal layer 260
In rapid, the metal layer 260 is formed on the barrier layer.
Specifically, forming the processing step of the metal layer 260 includes：In the described first opening 151 and the second opening 152
The interior full metal material of filling, the metal material top is higher than at the top of the barrier layer；Grinding, which removes, is higher than interlayer dielectric layer 150
The metal material at top forms the metal layer 260, and also grinding removes the barrier layer higher than the top of interlayer dielectric layer 150, work(
Function layer 250, the first nitrogenous layer 242, the second nitrogenous layer 241, Ti layers 240, cap 230 and gate dielectric layer 220.
Wherein, the boundary layer 211 positioned at the described first 151 bottoms of opening, on the boundary layer 211 and first opens
Gate dielectric layer 220 on mouthful 151 side walls, the cap 230 on the gate dielectric layer 220, in the cap 230
Ti layers 240, the second nitrogenous layer 241 on the Ti layers 240, the work-function layer on second nitrogenous layer 241
250, barrier layer in the work-function layer 250 and on the barrier layer and full first opening 151 of filling
Metal layer 260 be used to form the gate structure of first area I；Boundary layer 211, position positioned at the described second 152 bottoms of opening
In on the boundary layer 211 and second opening 152 side walls on gate dielectric layer 220, the lid on the gate dielectric layer 220
Cap layers 230, the Ti layers 240 in the cap 230, the first nitrogenous layer 242 on the Ti layers 240, positioned at institute
The work-function layer 250 on the first nitrogenous layer 242 is stated, barrier layer in the work-function layer 250 and positioned at the stop
On layer and gate structure of the metal layer 260 of second opening 152 for forming second area II is expired in filling.
In the present embodiment, the material of the metal layer 260 is W.In other embodiments, the material of the metal layer may be used also
Think Al, Cu, Ag, Au, Pt, Ni or Ti.
In the present embodiment, before work-function layer 250 (as shown in Figure 8) is formed, in the second area II gate dielectric layers
The first nitrogenous layer 242 (as shown in Figure 8) is formed on 220；Since the channel region length of first N-type transistor is less than described the
The channel region length of two N-type transistors, the i.e. opening size of first opening, 151 (as shown in Figure 8) are opened less than described second
The opening size of 152 (as shown in Figure 8) of mouth, correspondingly, first opening 151 is vertical wide than more than the described second opening 152
Vertical wide ratio, therefore when forming work-function layer 250 of the material containing aluminium, under the conditions of same process, aluminium atom is described first
Deposition capability in opening 151 is poor, the work-function layer 250 being open compared to second formed in 152, institute in the first opening 151
The thickness of formation work-function layer 250 is smaller and aluminium content is relatively low；But deposition capability of the aluminium atom on nitrogenous layer is also poor,
Therefore by forming the first nitrogenous layer 242 on second area II gate dielectric layers 220, to reduce aluminium atom in the described second opening
Sedimentation rate in 242, so as to reduce the thickness of formed second area II work-function layers 250, reduction forms second area
The mass percentage content of aluminium atom in II work-function layers 250.
So the formation of first nitrogenous layer 242, can make up by the described first opening 151 and the second opening 152
It is vertical wide than the inconsistent influence brought, the aluminium atom in the work-function layer 250 is opened in the described first opening 151 with second
Deposition capability in mouth 152 is suitable, so that 250 thickness of work-function layer of first N-type transistor and the second N-type transistor
Quite and aluminium content is suitable, and then makes the electric property of first N-type transistor and the second N-type transistor suitable, avoids institute
State the first N-type transistor because 250 thickness of work-function layer is smaller, aluminium content is relatively low cause threshold voltage higher the problem of.
With continued reference to Fig. 9, correspondingly, the present invention also provides a kind of semiconductor structure, including：
Substrate, the substrate include the first area I with the first transistor and the secondth area with second transistor
Domain II, the channel region length of the first transistor are less than the channel region length of the second transistor；
Interlayer dielectric layer 150 in the substrate, has in the interlayer dielectric layer 150 and exposes the first area
First 151 (as shown in Figure 8) of opening of I substrates and expose the second of the second area II substrates and be open 152 (such as Fig. 8 institutes
Show)；
First grid structure in the described first opening 151, including positioned at the described first 151 bottoms of opening and side wall
On gate dielectric layer 220, on the gate dielectric layer 220 and work-function layer 250 of the material containing aluminium, and positioned at the work content
On several layers 250 and the metal layer 260 of first opening 151 is expired in filling；
Second grid structure in the described second opening 152, including positioned at the described second 152 bottoms of opening and side wall
On gate dielectric layer 220, the first nitrogenous layer 242 on the gate dielectric layer 220, on first nitrogenous layer 242
And work-function layer 250 of the material containing aluminium, and in the work-function layer 250 and full second opening 152 of filling gold
Belong to layer 260.
In the present embodiment, the semiconductor structure is fin field effect pipe transistor, correspondingly, the substrate includes substrate
100 and discrete fin 110 on substrate 100.Specifically, the first transistor in the first area I substrates is to state
First N-type transistor, second transistor in the second area II substrates is states the second N-type transistor；First N-type is brilliant
Body pipe is short-channel transistor, and second N-type transistor is long channel MOSFET.
In other embodiments, the semiconductor structure can also be planar transistor, correspondingly, the substrate can be with
For planar substrates.
The first area I and second area II can be adjacent area, or non-conterminous region.The present embodiment
In, the first area I and second area II are non-conterminous area.
In the present embodiment, the substrate 100 is silicon substrate.In other embodiments, the material of the substrate can also be
Germanium, SiGe, carborundum, GaAs or gallium indium, the substrate can also be on silicon substrate or insulator on insulator
Germanium substrate.
The material identical of the material of the fin 110 and the substrate 100.In the present embodiment, the material of the fin 110
For silicon.In other embodiment, the material of the fin can also be germanium, SiGe, carborundum, GaAs or gallium indium.
It should be noted that the semiconductor structure further includes：Between the adjacent fin 110 on substrate 100
Isolation structure 101, the top of isolation structure 101 is less than the top of fin 110.The isolation structure 101 is used as semiconductor
The isolation structure of structure, for playing buffer action to adjacent devices.In the present embodiment, the material of the isolation structure 101 is
Silica.In other embodiments, the material of the isolation structure can also be silicon nitride or silicon oxynitride.
The semiconductor structure further includes：Source and drain doping area 140 in the first grid structure both sides fin 110
And the source and drain doping area 140 in the second grid structure both sides fin 110.Wherein, the semiconductor structure is N-type
Transistor, correspondingly, the Doped ions in the source and drain doping area 140 are N-type ion, it is, for example, P, As or Sb.
In the present embodiment, first opening 151 is through the first area I interlayer dielectric layers 150 and exposes described the
One region I fins 110, second opening 152 is through the second area II interlayer dielectric layers 150 and exposes secondth area
Domain II fins 110.
The material of the gate dielectric layer 220 is high-k gate dielectric material, wherein, high-k gate dielectric material refers to opposite Jie
Electric constant is more than the gate dielectric material of silica relative dielectric constant.In the present embodiment, the material of the gate dielectric layer 220 is
HfO2.In other embodiments, the material of the gate dielectric layer can also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO,
ZrO2Or Al2O3。
It should be noted that the semiconductor structure further includes：Interface between gate dielectric layer 220 and fin 110
Layer 211.On the one hand, the boundary layer 211 is as the first grid structure and a part for second grid structure, with the grid
Dielectric layer 220 forms the gate dielectric layer of laminated construction；On the other hand, the boundary layer 211 is used to improve the gate dielectric layer 220
Interface performance between substrate, is additionally operable to improve the formation quality of the gate dielectric layer 220.In the present embodiment, the interface
The material of layer 211 is silica.In other embodiments, the material of the boundary layer can also be silicon oxynitride.
242 layers of first nitrogenous layer has the function that suppressing work-function layer 250 forms, and first nitrogenous layer 242 can
To reduce the thickness of the second area II work-function layers 250, aluminium in the second area II work-function layers 250 can also be reduced
The mass percentage content of atom.
Due to the vertical wide vertical wide ratio than more than the described second opening 152 of the described first opening 151, in the work-function layer
In 250 forming process, under the conditions of same process, deposition capability of the aluminium atom in the described first opening 151 is poor, compares
Second area II work-function layers 250, the thickness of first area I work-function layers 250 is smaller and aluminium content is relatively low.But aluminium atom
Deposition capability on nitrogenous layer is poor, and the mass percentage content of nitrogen-atoms is higher, and the deposition capability of aluminium atom is poorer, because
This can reduce sedimentation rate of the aluminium atom in the described second opening 152, so as to reduce by first nitrogenous layer 242
The thickness of the second area II work-function layers, the mass percent for reducing aluminium atom in the second area II work-function layers contain
Amount.
Differed so first nitrogenous layer 242 can make up by the vertical wide ratio of the first opening 151 and the second opening 152
The influence that brings is caused, makes that the thickness of first area I and second area the II work-function layer 250 is suitable and aluminium content is suitable.
In the present embodiment, the first grid structure further includes：Positioned at the first area I gate dielectric layers 220 and work content
The second nitrogenous layer 241 between several layers 250, the material phase of the material of second nitrogenous layer 241 and first nitrogenous layer 242
Together, and the mass percentage content of nitrogen-atoms is less than nitrogen-atoms in first nitrogenous layer 242 in second nitrogenous layer 241
Mass percentage, correspondingly, the thickness of second nitrogenous layer 241 is less than the thickness of first nitrogenous layer 242.
The mass percentage content of nitrogen-atoms is higher, i.e. nitrating concentration is higher, and the deposition capability of aluminium atom is poorer, passes through control
The mass percentage of nitrogen-atoms in 242 and second nitrogenous layer 241 of the first nitrogenous layer is made, can be further compensated for by first
151 and second opening 152 of opening it is vertical wide than the inconsistent influence brought, balance aluminium atom is in the described first opening 151 and the
Deposition capability in two openings 152.
In the present embodiment, the material of first nitrogenous layer 242 is TiN, correspondingly, the material of second nitrogenous layer 241
Material is also TiN.
It should be noted that the thickness of first nitrogenous layer 242 is unsuitable too small, also should not be too large.If described first
The thickness of nitrogenous layer 242 is too small, correspondingly, the mass percentage content of nitrogen-atoms is less in first nitrogenous layer 242, suppresses
The effect unobvious that work-function layer 250 is formed, so as to cause first nitrogenous layer 242 to be difficult to make up by the first 151 Hes of opening
The vertical width of second opening 152 is than the inconsistent influence brought；If the thickness of first nitrogenous layer 242 is excessive, accordingly can mistake
The space of second opening 152 is occupied more, so as to be easily reduced the metal layer 260 in the described first opening 151 and the
Filling capacity in two openings 152.For this reason, in the present embodiment, the thickness of first nitrogenous layer 242 isExtremely
In order to balance deposition capability of the aluminium atom in the described first opening 151 and the second opening 152, described second is nitrogenous
The thickness of the thickness and first nitrogenous layer 242 of layer 241 matches, and in order to avoid second nitrogenous layer 241 too much
The space of first opening 151 is occupied, in the present embodiment, the thickness of second nitrogenous layer 241 isExtremely
In the present embodiment, the semiconductor structure further includes：Positioned at 220 and first nitrogenous layer 242 of gate dielectric layer it
Between, the Ti layers 240 between 220 and second nitrogenous layer 241 of gate dielectric layer；First nitrogenous layer 242 and second contains
Nitrogen layer 241 is transformed by the Ti layers 240 through nitrating technique.
It should be noted that include Ti elements and N element in the material of the gate structure, therefore use, Ti materials and
TiN materials can have preferable processing compatibility, phase to avoid the introducing of impurity element, Ti materials and TiN materials with transistor
Answer, harmful effect can be produced to avoid the electric property of double of conductor device.
In the present embodiment, the semiconductor structure further includes：Lid between the gate dielectric layer 220 and Ti layers 240
Cap layers 230, the cap 230 not only play a protective role the gate dielectric layer 220, avoid in the work-function layer 250
Metal ion diffuse in the gate dielectric layer 220；Also, it is also prevented from the expansion of the oxonium ion in the gate dielectric layer 220
It is dissipated in the work-function layer 250, so that the problem of improving Lacking oxygen content increase in the gate dielectric layer 220.
In the present embodiment, the material of the cap 230 is TiN, and the thickness of the cap 230 isExtremely
In other embodiments, the material of the cap can also be TiSiN or TaN.
The work-function layer 250 is used for the threshold voltage for adjusting transistor.
In the present embodiment, the semiconductor structure is N-type transistor；Correspondingly, the first area I work-function layers 250
Be N-type work function material with second area II work-function layers 250, N-type work function material workfunction range for 3.9eV extremely
4.5eV, is, for example, 4eV, 4.1eV or 4.3eV.In the present embodiment, the material of the work-function layer 250 is TiAl.In other realities
Apply in example, the material of the work-function layer can also be TaAl, TiAlC, AlN, TiAlN or TaAlN.
Need what is illustrated, under the action of 241 and first nitrogenous layer 242 of the second nitrogenous layer, the first area I work(
The thickness of function layer 250 is suitable with the thickness of the second area II work-function layers 250, and the first area I work-function layers
Aluminium content in 250 is suitable with the aluminium content in the second area II work-function layers 250.
In the present embodiment, the thickness of the work-function layer 250 isExtremelyI.e. described first area I work-function layers
250 thickness isExtremelyThe thickness of the second area II work-function layers 250 isExtremely
In the present embodiment, the material of the metal layer 260 is W.In other embodiments, the material of the metal layer may be used also
Think Al, Cu, Ag, Au, Pt, Ni or Ti.
It should also be noted that, the semiconductor structure further includes：Positioned at the work-function layer 250 and metal layer 260 it
Between barrier layer (not shown), the barrier layer be used for play a protective role to the work-function layer 250, prevent the metal layer
Easy diffusion ion in 260 is diffused in the work-function layer 250, so as to avoid causing the performance of the work-function layer 250
Harmful effect.
In the present embodiment, the material on the barrier layer is TiN, and the thickness on the barrier layer isExtremelyAt other
In embodiment, the material on the barrier layer can also be TiSiN.
In the present embodiment, the second grid structure includes first between gate dielectric layer 220 and work-function layer 250
Nitrogenous layer 242, first nitrogenous layer 242 advantageously reduce deposition capability of the aluminium atom in the described second opening 152, so that
It can make up vertical wide than the inconsistent influence brought by the described first opening 151 and the second opening 152, make aluminium atom described the
It is suitable with the deposition capability in the second opening 152 in one opening 151, therefore the work content of the first transistor and second transistor
Several layers 250 thickness is suitable and aluminium content is suitable, and then makes the electric property of the first transistor and second transistor suitable, keeps away
Exempt from the first transistor because 250 thickness of work-function layer is smaller, aluminium content is relatively low cause threshold voltage higher the problem of.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the scope of restriction.
Claims (20)
- A kind of 1. forming method of semiconductor structure, it is characterised in that including：Substrate is provided, the substrate includes being used to form the first area of the first transistor and for forming second transistor Second area, the channel region length of the first transistor are less than the channel region length of the second transistor；Interlayer dielectric layer is formed on the substrate；The first opening for exposing the first area substrate is formed in the interlayer dielectric layer and exposes the second area Second opening of substrate；Gate dielectric layer is formed on the bottom of the described first opening and side wall and on the bottom of the second opening and side wall；The first nitrogenous layer is formed on the second area gate dielectric layer；Work-function layer of the material containing aluminium is formed on the first area gate dielectric layer and on first nitrogenous layer；The metal layer of full first opening of filling and the second opening is formed in the work-function layer.
- 2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material of first nitrogenous layer is TiN。
- 3. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the thickness of first nitrogenous layer isExtremely
- 4. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that in the second area gate dielectric layer In the step of the first nitrogenous layer of upper formation, the second nitrogenous layer is formed on the first area gate dielectric layer, wherein described second The mass percentage content of nitrogen-atoms is less than the mass percentage of nitrogen-atoms in first nitrogenous layer in nitrogenous layer.
- 5. the forming method of semiconductor structure as claimed in claim 4, it is characterised in that the thickness of second nitrogenous layer isExtremely
- 6. the forming method of semiconductor structure as claimed in claim 4, it is characterised in that first nitrogenous layer and second contains The material of nitrogen layer is TiN；The step of forming first nitrogenous layer and the second nitrogenous layer includes：Ti layers are formed on the gate dielectric layer；To described Ti layers progress nitrating technique, the Ti layers of segment thickness are changed into TiN layer.
- 7. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that thickness Ti layers described isExtremely
- 8. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that form technique Ti layers described to change Learn gas-phase deposition.
- 9. the forming method of semiconductor structure as claimed in claim 8, it is characterised in that the chemical vapor deposition method Parameter includes：Reacting gas is TiCl4And H2, TiCl4Gas flow be 10sccm to 100sccm, H2Gas flow be 2000sccm to 4000scm, reaction temperature are 400 DEG C to 600, and power is 600W to 1000W, and pressure is 2Torr to 6Torr.
- 10. the forming method of semiconductor structure as claimed in claim 6, it is characterised in that the nitrating technique is plasma Body nitriding process.
- 11. the forming method of semiconductor structure as claimed in claim 10, it is characterised in that the plasma nitridation process Used reacting gas is N2Or NH3。
- 12. the forming method of semiconductor structure as claimed in claim 11, it is characterised in that the plasma nitridation process Parameter include：Power is 600W to 1000W, and pressure is 2Torr to 6Torr, and the process time is 2s to 6s, the gas of reacting gas Body flow is 500sccm to 1000sccm.
- 13. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that the material of the work-function layer is TiAl, TaAl, TiAlC, AlN, TiAlN or TaAlN.
- 14. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that form the work of the work-function layer Skill is atom layer deposition process.
- A kind of 15. semiconductor structure, it is characterised in that including：Substrate, the substrate include the first area with the first transistor and the second area with second transistor, institute The channel region length for stating the first transistor is less than the channel region length of the second transistor；Interlayer dielectric layer in the substrate, has in the interlayer dielectric layer and exposes the first of the first area substrate Second for being open and exposing the second area substrate is open；First grid structure in the described first opening, including the gate medium in first open bottom and side wall Layer, on the gate dielectric layer and work-function layer of the material containing aluminium, and in the work-function layer and filling is full described The metal layer of first opening；Second grid structure in the described second opening, including the gate medium in second open bottom and side wall Layer, the first nitrogenous layer on the gate dielectric layer, on first nitrogenous layer and work-function layer of the material containing aluminium, with And in the work-function layer and full second opening of filling metal layer.
- 16. semiconductor structure as claimed in claim 15, it is characterised in that the material of first nitrogenous layer is TiN.
- 17. semiconductor structure as claimed in claim 15, it is characterised in that the thickness of first nitrogenous layer isExtremely
- 18. semiconductor structure as claimed in claim 15, it is characterised in that the material of the work-function layer for TiAl, TaAl, TiAlC, AlN, TiAlN or TaAlN.
- 19. semiconductor structure as claimed in claim 15, it is characterised in that the first grid structure further includes：Positioned at institute The second nitrogenous layer between first area gate dielectric layer and work-function layer is stated, the material of second nitrogenous layer contains with described first The material identical of nitrogen layer, and the mass percentage content of nitrogen-atoms is less than nitrogen in first nitrogenous layer in second nitrogenous layer The mass percentage of atom.
- 20. semiconductor structure as claimed in claim 19, it is characterised in that the thickness of second nitrogenous layer isExtremely
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610884437.5A CN107919323B (en) | 2016-10-10 | 2016-10-10 | Semiconductor structure and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610884437.5A CN107919323B (en) | 2016-10-10 | 2016-10-10 | Semiconductor structure and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107919323A true CN107919323A (en) | 2018-04-17 |
| CN107919323B CN107919323B (en) | 2021-06-08 |
Family
ID=61892398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610884437.5A Active CN107919323B (en) | 2016-10-10 | 2016-10-10 | Semiconductor structure and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107919323B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110556337A (en) * | 2018-05-31 | 2019-12-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN110838488A (en) * | 2018-08-15 | 2020-02-25 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for forming the same |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020028544A1 (en) * | 2000-07-31 | 2002-03-07 | Etsuko Fujimoto | Semiconductor device and method of manufacturing the same |
| WO2006132172A1 (en) * | 2005-06-07 | 2006-12-14 | Nec Corporation | Fin type field effect transistor, semiconductor device and production method thereof |
| CN101322240A (en) * | 2005-12-02 | 2008-12-10 | 国立大学法人东北大学 | Semiconductor device |
| CN101546772A (en) * | 2008-03-25 | 2009-09-30 | 恩益禧电子股份有限公司 | Semiconductor device including capacitor element and method of manufacturing the same |
| CN102130057A (en) * | 2010-01-14 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Method for making complementary metal oxide semiconductor device, and structure of complementary metal oxide semiconductor device |
| US20120129310A1 (en) * | 2010-11-22 | 2012-05-24 | Weonhong Kim | Methods of fabricating a semiconductor device having a high-k gate dielectric layer and semiconductor devices fabricated thereby |
| CN104124169A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor and forming method thereof and CMOS transistor and forming method thereof |
| CN104218000A (en) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Transistor and formation method thereof |
| CN104241367A (en) * | 2013-06-24 | 2014-12-24 | 三星电子株式会社 | Semiconductor devices and methods of fabricating the same |
| CN105304565A (en) * | 2014-05-28 | 2016-02-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
| CN105914208A (en) * | 2015-02-25 | 2016-08-31 | 精工半导体有限公司 | Semiconductor integrated circuit device and method of manufacturing the same |
-
2016
- 2016-10-10 CN CN201610884437.5A patent/CN107919323B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020028544A1 (en) * | 2000-07-31 | 2002-03-07 | Etsuko Fujimoto | Semiconductor device and method of manufacturing the same |
| WO2006132172A1 (en) * | 2005-06-07 | 2006-12-14 | Nec Corporation | Fin type field effect transistor, semiconductor device and production method thereof |
| CN101322240A (en) * | 2005-12-02 | 2008-12-10 | 国立大学法人东北大学 | Semiconductor device |
| CN101546772A (en) * | 2008-03-25 | 2009-09-30 | 恩益禧电子股份有限公司 | Semiconductor device including capacitor element and method of manufacturing the same |
| CN102130057A (en) * | 2010-01-14 | 2011-07-20 | 中芯国际集成电路制造(上海)有限公司 | Method for making complementary metal oxide semiconductor device, and structure of complementary metal oxide semiconductor device |
| US20120129310A1 (en) * | 2010-11-22 | 2012-05-24 | Weonhong Kim | Methods of fabricating a semiconductor device having a high-k gate dielectric layer and semiconductor devices fabricated thereby |
| US8673711B2 (en) * | 2010-11-22 | 2014-03-18 | Samsung Electronics Co., Ltd. | Methods of fabricating a semiconductor device having a high-K gate dielectric layer and semiconductor devices fabricated thereby |
| CN104124169A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor and forming method thereof and CMOS transistor and forming method thereof |
| CN104218000A (en) * | 2013-06-05 | 2014-12-17 | 中芯国际集成电路制造(上海)有限公司 | Transistor and formation method thereof |
| CN104241367A (en) * | 2013-06-24 | 2014-12-24 | 三星电子株式会社 | Semiconductor devices and methods of fabricating the same |
| CN105304565A (en) * | 2014-05-28 | 2016-02-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
| CN105914208A (en) * | 2015-02-25 | 2016-08-31 | 精工半导体有限公司 | Semiconductor integrated circuit device and method of manufacturing the same |
Non-Patent Citations (1)
| Title |
|---|
| 裴智慧，等: "栅介质材料及尺寸对薄膜晶体管性能影响研究", 《南京大学学报（自然科学版）》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110556337A (en) * | 2018-05-31 | 2019-12-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN110556337B (en) * | 2018-05-31 | 2021-09-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN110838488A (en) * | 2018-08-15 | 2020-02-25 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107919323B (en) | 2021-06-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106684144B (en) | The manufacturing method of semiconductor structure | |
| TWI635535B (en) | Semiconductor process of forming metal gates with different threshold voltages and semiconductor structure thereof | |
| JP6218384B2 (en) | Manufacturing method of semiconductor device having tungsten gate electrode | |
| CN106158860B (en) | Semiconductor structure and its manufacturing method | |
| CN107958872A (en) | Semiconductor devices and forming method thereof | |
| US11387149B2 (en) | Semiconductor device and method for forming gate structure thereof | |
| TWI663656B (en) | Semiconductor device having metal gate and fabrication method thereof | |
| TWI591826B (en) | Semiconductor device with dual work function gate stacks and method for fabricating the same | |
| CN106653691A (en) | Production method of semiconductor structure | |
| CN108010884A (en) | Semiconductor structure and forming method thereof | |
| CN107346783A (en) | Semiconductor structure and its manufacture method | |
| CN106653605A (en) | Forming method of semiconductor structure | |
| CN108074815B (en) | Semiconductor structure and forming method thereof | |
| CN107516631A (en) | The forming method of semiconductor devices | |
| US20200066601A1 (en) | Method for forming semiconductor device and resulting device | |
| CN107591366A (en) | Semiconductor structure and forming method thereof | |
| CN108022882A (en) | Semiconductor structure and forming method thereof | |
| CN107293488A (en) | Semiconductor structure and its manufacture method | |
| CN107919323A (en) | Semiconductor structure and forming method thereof | |
| CN106876273B (en) | The manufacturing method of semiconductor structure | |
| CN108630751A (en) | Semiconductor structure and forming method thereof | |
| CN107481932A (en) | The manufacture method of semiconductor structure | |
| CN107437562A (en) | The forming method of semiconductor devices | |
| CN106469652A (en) | Semiconductor device and forming method thereof | |
| CN106653603B (en) | Improve the method for semiconductor structure leakage current |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |