CN107534061B - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
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- CN107534061B CN107534061B CN201580078952.8A CN201580078952A CN107534061B CN 107534061 B CN107534061 B CN 107534061B CN 201580078952 A CN201580078952 A CN 201580078952A CN 107534061 B CN107534061 B CN 107534061B
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- 239000010410 layer Substances 0.000 claims description 104
- 239000011229 interlayer Substances 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 35
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 25
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 24
- 238000007789 sealing Methods 0.000 claims description 21
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
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- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- 229910052737 gold Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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Abstract
将在向背面电极施加额定电压V[V]时从阱区域向半导体层的外周方向扩展的耗尽层的前端的、半导体层的表面处的位置设为x,将位置x和表面电极的外周端的外周方向的距离设为W1,将位置x和场绝缘膜的外周端的外周方向的距离设为W2,将场绝缘膜的膜厚设为t[μm],以使位置x处的场绝缘膜中的电场W2V/t(W1+W2)成为3MV/cm以下的方式规定终端部的布局。
Description
技术领域
本发明涉及碳化硅半导体器件等半导体器件。
背景技术
近年来,作为能够实现高耐压并且低损耗的下一代半导体器件,使用碳化硅(SiC)的半导体器件(以下称为“碳化硅半导体器件”)得到瞩目。相比于以往的半导体器件中所使用的硅(Si),SiC的绝缘击穿电场强度约为10倍,所以关于碳化硅半导体器件,特别期待向高耐压的功率用半导体器件展开。
已知在碳化硅半导体器件中,为了进一步提高耐压,通过在n型的碳化硅半导体层内的所谓终端区域(终端部(terminal part))设置p型的保护环区域(终端阱区域),利用由碳化硅半导体层和保护环区域的PN结形成的耗尽层来缓和被施加反向电压时的电场(例如专利文献1)。另外,在专利文献1记载的由SiC构成的肖特基势垒二极管(SiC-SBD、SiC-Schottky Barrier Diode)中,形成为在终端区域中的碳化硅半导体层上设置层间绝缘膜(场绝缘膜),使表面电极的外周端延伸到层间绝缘膜上。而且,以覆盖表面电极的一部分以及层间绝缘膜的方式,形成有聚酰亚胺作为保护膜。
现有技术文献
专利文献1:日本特开2013-211503号公报
发明内容
然而,在这样的半导体器件中,有时利用树脂对形成有聚酰亚胺等保护膜的结构进行密封。在该树脂是凝胶时,特别是在湿度高的状态下使用的情况下,有时凝胶、聚酰亚胺包含水分而形成从半导体芯片的外周部至层间绝缘膜(场绝缘膜)之上的表面电极的端部为止的泄漏路径。在这样的情况下,有时在层间绝缘膜(场绝缘膜)的下部的特别是保护环区域的外周附近与层间绝缘膜(场绝缘膜)的上部之间产生大的电位差,层间绝缘膜(场绝缘膜)发生绝缘击穿,而半导体芯片的品质变差。
本发明是为了解决如上所述的问题而完成的,其目的在于提供一种半导体器件,即使在湿度高的状态下使用用凝胶来密封的半导体芯片的情况下,半导体芯片的品质也不会变差。
本发明所涉及的半导体器件的特征在于,具备:半导体基板;第1导电类型的半导体层,形成于半导体基板上;场绝缘膜,形成于半导体层的表面上;表面电极,以比场绝缘膜靠内周侧并延伸到场绝缘膜上的方式形成于半导体层的表面上;第2导电类型的阱区域,与表面电极连接而形成于半导体层的表层部,比表面电极的外周端更向外周侧延伸;表面保护膜,以覆盖表面电极的外周端及场绝缘膜的外周端的方式形成于表面电极及场绝缘膜上,所述表面保护膜由绝缘材料构成;密封凝胶,形成于半导体层及表面保护膜上的半导体层的外周部;以及背面电极,形成于半导体基板的背面,将在向背面电极施加额定电压V[V]时从阱区域向半导体层的外周方向扩展的耗尽层的前端的位置设为x,将位置x和表面电极的外周端的外周方向的距离设为W1,将位置x和场绝缘膜的外周端的外周方向的距离设为W2,场绝缘膜的膜厚t[μm]是t≥W2V/300(W1+W2)。
根据本发明所涉及的半导体器件,即使在由于密封凝胶、表面保护膜吸收水分而在场绝缘膜的表面形成泄漏路径的情况下,也能够将对场绝缘膜等绝缘膜施加的电场抑制为一定的值以下,抑制半导体器件成为元件击穿。
附图说明
图1是示意性地示出本发明的实施方式1中的半导体器件的终端部的剖面图。
图2是示意性地示出本发明的实施方式1中的半导体器件的终端部中的截止(OFF)时的耗尽层的扩展(spread)的剖面图。
图3是示意性地示出本发明的实施方式1中的半导体器件的终端部的剖面图。
图4是示意性地示出本发明的实施方式1中的半导体器件的终端部中的截止时的耗尽层的扩展的剖面图。
图5是示意性地示出本发明的实施方式2中的半导体器件的终端部的剖面图。
图6是示意性地示出本发明的实施方式2中的半导体器件的终端部中的截止时的耗尽层的扩展的剖面图。
图7是示意性地示出本发明的实施方式3中的半导体器件的终端部的剖面图。
图8是示意性地示出本发明的实施方式3中的半导体器件的终端部中的截止时的耗尽层的扩展的剖面图。
图9是示意性地示出本发明的实施方式4中的半导体器件的终端部的剖面图。
图10是示意性地示出本发明的实施方式4中的半导体器件的终端部中的截止时的耗尽层的扩展的剖面图。
图11是示意性地示出本发明的实施方式4中的半导体器件的终端部中的截止时的耗尽层的扩展的剖面图。
(符号说明)
1a:半导体基板;1b:半导体层;2:终端阱区域;3:场绝缘膜;4:肖特基电极(第1表面电极);5:电极焊盘(第2表面电极);5a:锥形部;6:表面保护膜;7:背面电极;8:密封凝胶;9:活性阱区域;10:高浓度活性阱区域;11:源极区域;12:层间绝缘膜;13:栅电极;14:栅极绝缘膜;15:源电极(第3表面电极);16:栅极焊盘(控制电极);100、200、300、400:半导体器件。
具体实施方式
以下,参照附图,说明实施方式。此外,附图是示意性地示出的图,不同的附图分别所示出的图像的尺寸以及位置的相互关系未必被准确地记载,可被适当变更。另外,在以下的说明中,对同样的构成要素附加相同的符号来图示,它们的名称以及功能也是同样的。因此,有时省略有关它们的详细说明。另外,在本说明书中,在“~上”、“将~覆盖(覆盖~)”这样的情况下,并不妨碍在构成要素之间存在夹杂物的情况。例如,在记载为“在A上设置的B”、“A覆盖B”的情况下,包括在A与B之间设置有其它构成要素C以及未设置有其它构成要素C的情况。
实施方式1.
首先,说明本发明的实施方式1所涉及的半导体器件100的终端部的结构。以下,例示将第1导电类型设为n型并将第2导电类型设为p型的SiC-SBD来进行说明,但也可以是将第1导电类型设为p型并将第2导电类型设为n型的半导体器件,还可以并非是SBD而是PN结二极管、JBS(Junction Barrier Schottky,结势垒肖特基)二极管。
图1是示意性地示出实施方式1所涉及的半导体器件100的终端部的结构的剖面图。如图1所示,半导体器件100具备:半导体基板1a;半导体层1b,形成于半导体基板1a上;场绝缘膜3,以空出中央部的方式形成于半导体层1b上;作为第1表面电极的肖特基电极4,以从没有场绝缘膜3的中央部延伸到场绝缘膜3上的方式形成于半导体层1b上;作为第2表面电极的电极焊盘5,形成于肖特基电极4上;终端阱区域2,以比电极焊盘5的外周端更向外周侧延伸的方式形成于半导体层1b的表层部;表面保护膜6,以覆盖电极焊盘5的外周端及场绝缘膜3的外周端的方式形成于电极焊盘5及场绝缘膜3上;密封凝胶8,以使半导体层1b及表面保护膜6的表面不会露出的方式形成于半导体层1b的外周部;以及背面电极7,形成于半导体基板1a的背面。从肖特基电极4的外周端的内侧至比电极焊盘5的外周端更靠外周侧,环状地形成有终端阱区域2。
在图1中,右侧是半导体器件100的终端部侧,左侧是在接通(ON)状态下流过主电流的活性区域侧。
半导体基板1a和半导体层1b由4H型的碳化硅半导体构成,半导体基板1a是低电阻n型基板,半导体层1b是1×1014cm-3~1×1017cm-3的杂质浓度的n型。作为场绝缘膜3,能够使用氧化硅(SiO2)、氮化硅(SiN)等的无机绝缘膜,在本实施方式中使用厚度t[μm]的氧化硅。
另外,作为第1表面电极的肖特基电极4是与n型的碳化硅半导体进行肖特基接合的金属即可,能够使用钛、钼、镍、金、钨等,厚度例如能够设为30nm~300nm。在本实施方式中,使用厚度200nm的钛膜作为肖特基电极4。
而且,关于作为第2表面电极的电极焊盘5,能够使用包括铝、铜、钼、镍中的任意成分的金属、如Al-Si那样的铝合金等,厚度例如能够设为300nm~10μm。在本实施方式中,使用厚度5μm的Al层作为电极焊盘5。
表面保护膜6由绝缘材料构成,为了与外部端子进行连接,在电极焊盘5的中央部上具有开口。另外,为了缓和来自外部环境的应力,表面保护膜6优选为是树脂膜,在本实施方式中,使用聚酰亚胺作为表面保护膜6。
另外,背面电极7与半导体基板1a进行了欧姆连接。因此,背面电极7能够使用与作为半导体基板1a的n型碳化硅半导体进行欧姆连接的镍、铝、钼等金属。在本实施方式中使用镍。
密封凝胶8使用硅凝胶等凝胶。对电极焊盘5的一部分接合有由铝等材料形成的导线(未图示),经由密封凝胶8的内部而连接到外部端子。
在此,将在向背面电极7施加额定电压V[V]时从终端阱区域2向半导体层1b的外周方向延伸的耗尽层的前端的位置设为x,将x和表面电极(在此是作为第2表面电极的电极焊盘5)的外周端的外周方向的距离设为W1,将x和场绝缘膜3的外周端的外周方向的距离设为W2,场绝缘膜3的厚度t[μm]是
t≥W1V/300(W1+W2) (1)。
接下来,说明本发明的实施方式1的半导体器件100的制造方法。
首先,在具有倾斜角(off-angle)的n+型的低电阻碳化硅半导体的半导体基板1a上,使n型且杂质浓度为1×1014/cm3~1×1017/cm3的碳化硅的半导体层1b外延结晶生长。然后,在通过光刻工序等,按照预定的形状对抗蚀膜进行构图之后,从抗蚀膜之上离子注入Al、B等p型的杂质,在1500℃以上的高温下进行退火,从而在半导体层1b内的表层部形成p型的终端阱区域2(保护环区域)。
作为终端阱区域2的剂量(杂质浓度),优选为1×1013/cm2~1×1014/cm2,更优选为2×1013/cm2~5×1013/cm2。在本实施方式中为2.0×1013/cm2。在p型杂质的离子注入中,在注入Al的情况下,例如将注入能量设为100keV~700keV。在上述情况下,在将上述各区域中的p型杂质的剂量[cm-2]换算为杂质浓度[cm-3]时,终端阱区域2的杂质浓度为1×1017/cm3~1×1019/cm3。
接下来,例如通过CVD法,在半导体层1b的表面上堆积厚度t[μm]的氧化硅膜,之后通过光刻工序和蚀刻,去除半导体层1b的中央部的氧化硅膜,形成具有开口部的场绝缘膜3。场绝缘膜3的开口端形成为位于终端阱区域2上。接下来,在碳化硅基板1a的背面,通过溅射法等而形成背面电极7。
接下来,例如通过溅射法,在形成有场绝缘膜3的半导体层1b的表面上的整个面,形成成为肖特基电极4的金属膜,通过光刻工序和蚀刻来形成期望的形状的肖特基电极4。在金属膜的蚀刻中,能够使用干蚀刻或者湿蚀刻,但为了减轻对半导体器件的特性的影响,优选使用湿蚀刻,例如使用氢氟酸(HF)作为蚀刻液。
接下来,以覆盖肖特基电极4的方式,在场绝缘膜3以及肖特基电极4上形成电极焊盘5。与肖特基电极4的形成同样地,通过光刻工序和蚀刻来进行电极焊盘5的形成。例如通过使用磷酸系的蚀刻液的湿蚀刻来进行金属膜的蚀刻。
接下来,以覆盖电极焊盘5的方式形成表面保护膜6。通过涂敷感光性聚酰亚胺并曝光,使表面保护膜6成为期望的形状。接下来,在使导线形成于电极焊盘5之后,利用密封凝胶8进行密封,从而完成图1所示的本实施方式所涉及的半导体器件100。
此外,也可以在半导体基板1的表面侧的工序全部完成之后进行背面电极7的形成。另外,也可以在将背面电极7与其它导体连接之后,利用密封凝胶8进行密封。
接下来,使用图2,说明作为本实施方式的半导体器件100的SiC-SBD的动作。
在本实施方式的SiC-SBD中,在相对于表面电极(第1表面电极和第2表面电极)而向背面电极7施加负的电压时,从表面电极向背面电极7流过电流,半导体器件100成为导通状态(接通状态)。相反,在相对于表面电极而向背面电极7施加正的电压时,半导体器件100成为阻塞状态(截止状态)。
在半导体器件100成为截止状态的情况下,对半导体层1b的活性区域的表面、由半导体层1b和终端阱区域2形成的PN结界面附近施加大的电场,如果对背面电极7施加引起临界电场的电压则引起雪崩击穿。通常,在不引起雪崩击穿的范围中使用半导体器件100,确定额定电压V[V]。
在半导体器件100成为截止状态的情况下,如图2所示耗尽层从终端阱区域2向半导体层1b的外周方向和半导体基板1a的方向扩展。在此,用虚线表示的位置是耗尽层的前端位置。
在向相对表面电极的背面电极7施加作为额定电压的正的电压V[V]时,如图2所示,耗尽层在半导体层1b的表面向外周方向延伸至半导体层1b的表面的位置x。此时,将位置x和电极焊盘5的外周端的外周方向的距离设为W1,将位置x和场绝缘膜3的外周端的外周方向的距离设为W2。
在湿度高的状态下使用本实施方式的SiC-SBD的情况下等,认为密封凝胶8含有水分,该水分浸透至聚酰亚胺等的表面保护膜6。此时,在场绝缘膜3的表面,从半导体器件100的外周部(图2的右侧)向表面电极(电极焊盘5等)形成电流的泄漏路径。在形成这样的泄漏路径的情况下,在假设泄漏路径的电阻恒定时,对背面电极7施加额定电压V[V]时的位置x正上的场绝缘膜3的表面的电位为
W1V/(W1+W2) (2)
[V]。
另外,此时的位置x的电位与额定电压V[V]相同。因此,在位置x和位置x正上的场绝缘膜3的表面,发生
W2V/(W1+W2) (3)
[V]的电位差。
场绝缘膜3的厚度是t[μm],所以位置x处的场绝缘膜3中的电场为
W2V/t(W1+W2) (4)。
场绝缘膜3以氧化硅或者氮化硅为主成分,这些绝缘膜的绝缘击穿电场是5~10MV/cm程度,但有时由于在接近5MV/cm的高电压下由电场加速后的电子、空穴的注入,场绝缘膜3的绝缘特性降低,半导体器件100发生元件击穿。另外,还有如下报告例:即使在3MV/cm程度的情况下,如果以几十年这样的单位进行观察,则氧化膜劣化而导致击穿。
因此,在本发明的半导体器件100中,使对场绝缘膜3施加的电场成为3MV/cm以下。为了使对场绝缘膜3施加的电场成为3MV/cm以下,需要满足下面的式。
t≥W2V/300(W1+W2)…(5)
这样,根据本发明的实施方式1所涉及的半导体器件,即使在密封凝胶8、表面保护膜6含有水分而在场绝缘膜3表面形成泄漏路径的情况下,也由于能够使对场绝缘膜3施加的电场成为3MV/cm以下,所以能够抑制半导体器件成为元件击穿,能够提高半导体器件的可靠性。
此外,在本实施方式中,将半导体器件100设为SiC-SBD进行了说明,但即使半导体器件100是SiC-PN二极管,也起到同样的效果。
图3是半导体器件100为SiC-PN二极管的情况的剖面示意图。在图3中,第2导电类型的活性阱区域9形成于终端阱区域2的内周侧的半导体层1的表层部,未设置作为第1表面电极的肖特基电极4。在此,活性阱区域9由碳化硅半导体构成,作为第2表面电极的电极焊盘5与活性阱区域9进行了欧姆连接。
在如图3所示的SiC-PN二极管中,根据本发明的半导体器件,也起到与SiC-SBD同样的效果。
另外,虽然未图示,也可以在电极焊盘5与场绝缘膜3之间设置由Ti等构成的势垒金属。势垒金属例如是Ti、TiN、TiSi等含有Ti的金属薄膜,也可以设为将这些金属层叠多个而成的构造。
而且,在本实施方式中,说明了用作为第2表面电极的电极焊盘5来覆盖作为第1表面电极的肖特基电极4的端部,表面电极的外周端是作为第2表面电极的电极焊盘5的端部,但也可以未用第2表面电极的端部来覆盖第1表面电极的端部。
图4是半导体器件100的肖特基电极4的端部未被电极焊盘5的端部所覆盖的SiC-SBD的情况的剖面示意图。在图4中,肖特基电极4的端部从电极焊盘5的端部凸出,表面电极的外周端成为肖特基电极4的端部。即使是这样的半导体器件100,通过以满足式(5)的方式形成场绝缘膜3的厚度,也起到与上述同样的效果。
另外,在本实施方式中,以由碳化硅半导体构成的半导体器件为例进行了说明,但半导体的材料也可以是GaN、金刚石等其它材料,另外还可以是其它宽带隙半导体器件。宽带隙半导体的半导体器件在2000V以上、3000V以上的高电压下使用的情形较多,所以对场绝缘膜施加的电场变高。因此,在使用SiC等宽带隙半导体的半导体器件中,规定终端部的布局和场绝缘膜的厚度的效果特别大。
实施方式2.
在实施方式1中,说明了半导体器件是SiC-SBD、SiC-PN二极管等二极管的例子,但在本实施方式中,说明将本发明应用于开关元件的半导体器件的例子。以下,说明半导体器件200是将第1导电类型设为n型并将第2导电类型设为p型的n型SiC-MOSFET(Metal OxideSemiconductor Field Effect Transistor,金属氧化物半导体场效应晶体管)的情况,但也可以是将第1导电类型设为p型并将第2导电类型设为n型的半导体器件,还可以并非是MOSFET而是IGBT(Insulated Gate Bipolar Transistor,绝缘栅双极晶体管)、JFET(Junction Field Effect Transistor,结场效应晶体管)等开关元件。
图5是示意性地示出本发明的本实施方式所涉及的半导体器件200的终端部的结构的剖面图。如图5所示,半导体器件200具备:半导体基板1a;半导体层1b,形成于半导体基板1a上;场绝缘膜3,以空出中央部的方式形成于半导体层1b上;作为第3表面电极的源电极15,以从没有场绝缘膜3的中央部延伸到场绝缘膜3上的方式形成于半导体层1b上;终端阱区域2,以比源电极15的外周端更向外周侧延伸的方式形成于半导体层1b的表层部;表面保护膜6,以覆盖源电极15的外周端及场绝缘膜3的外周端的方式形成于源电极15及场绝缘膜3上;密封凝胶8,以使半导体层1b及表面保护膜6的表面不会露出的方式形成于半导体层1b的外周部;以及作为背面电极7的漏电极,形成于半导体基板1a的背面。
源电极15与设置于半导体层1b的表层部的第2导电类型的活性阱区域9连接,位于最外周的活性阱区域9与终端阱区域2在半导体层1b的表层部中连接。形成有多个活性阱区域9,在活性阱区域9的表层部,在从各个活性阱区域9的外周向内部进入预定的间隔的位置处形成有第1导电类型的源极区域11。另外,在从各个活性阱区域9的外周向内部进入预定的间隔的位置处,在与源电极15连接的位置形成有第2导电类型的杂质浓度比活性阱区域9高的第2导电类型的高浓度活性阱区域10。
在未形成有场绝缘膜3的活性阱区域9、半导体层1b、源极区域11、高浓度活性阱区域10等半导体材料的层上形成有栅极绝缘膜14,在活性阱区域9以及半导体层1b的上部,隔着栅极绝缘膜14形成有栅电极13。在栅极绝缘膜14、栅电极13的上部形成有层间绝缘膜12,在层间绝缘膜12以及栅极绝缘膜14中,形成有将高浓度活性阱区域10和源电极15进行连接的接触孔。源电极15在层间绝缘膜12上延伸。
在图5中,右侧是半导体器件200的终端部侧,左侧是在接通状态下流过主电流的活性区域侧。
在此,半导体基板1a和半导体层1b由4H型的碳化硅半导体构成,半导体基板1a是低电阻n型基板,半导体层1b是1×1014cm-3~1×1017cm-3的杂质浓度的n型。另外,栅极绝缘膜14、层间绝缘膜12由氧化硅构成,栅电极13由低电阻多晶硅构成。源电极15由Al等金属构成即可。
另外,虽然未图示,但也可以在源电极15与层间绝缘膜12以及场绝缘膜3之间,设置由Ti等构成的势垒金属。势垒金属例如是Ti、TiN、TiSi等含有Ti的金属薄膜,也可以设为将这些金属层叠多个而成的构造。
将在相对于表面电极(源电极15)而向背面电极7施加额定电压V[V]时从终端阱区域2在半导体层1b的表面、即场绝缘膜3与半导体层1b的界面中向半导体层1b的外周方向延伸的耗尽层的前端的位置设为x,将x和表面电极(在此是作为第3表面电极的源电极15)的外周端的外周方向的距离设为W1,将x和场绝缘膜3的外周端的外周方向的距离设为W2,场绝缘膜3的厚度t[μm]是
t≥W1V/300(W1+W2) (1)。
接下来,说明本实施方式的半导体器件200的制造方法。
首先,在具有倾斜角的n+型的低电阻碳化硅半导体的半导体基板1a上,使n型且杂质浓度是1×1014/cm3~1×1017/cm3的碳化硅的半导体层1b外延结晶生长。然后,在通过光刻工序等,按照预定的形状对抗蚀膜进行构图之后,从抗蚀膜之上离子注入Al、B等p型的杂质,在1500℃以上的高温下进行退火,从而在半导体层1b内的表层部形成p型的终端阱区域2(保护环区域)。
作为终端阱区域2的剂量(杂质浓度),优选为1×1013/cm2~1×1014/cm2,更优选为2×1013/cm2~5×1013/cm2。在本实施方式中是2.0×1013/cm2。在p型杂质的离子注入中,在注入Al的情况下,例如将注入能量设为100keV~700keV。在上述情况下,在将上述各区域中的p型杂质的剂量[cm-2]换算为杂质浓度[cm-3]时,终端阱区域2的杂质浓度为1×1017/cm3~1×1019/cm3。
另外,关于活性阱区域9、源极区域11、高浓度活性阱区域10,也与终端阱区域2同样地,在通过光刻工序等,按照预定的形状对抗蚀膜进行构图之后,从抗蚀膜之上离子注入Al、B等p型杂质、或者N、P等n型杂质而形成。与终端阱区域2的形成同时地进行离子注入后的活性化退火即可。
接下来,例如通过CVD法,在半导体层1b的表面上堆积厚度t[μm]的氧化硅膜,之后通过光刻工序和蚀刻来去除半导体层1b的中央部的氧化硅膜,形成具有开口部的场绝缘膜3。场绝缘膜3的开口端形成为位于活性阱区域9上。接下来,在碳化硅基板1a的背面形成背面电极7。
接下来,例如通过CVD法,在未形成有场绝缘膜3的活性区域,堆积成为栅极绝缘膜14的氧化硅膜。接着,在堆积成为栅电极13的低电阻多晶硅膜并构图之后,在栅极绝缘膜14、栅电极13的上部堆积成为层间绝缘膜12的氧化硅膜。在通过蚀刻使预定的位置的层间绝缘膜12、栅极绝缘膜14开口之后,在层间绝缘膜12、场绝缘膜3上例如通过溅射法来堆积金属层并构图,从而形成源电极15。
接下来,以覆盖源电极15、场绝缘膜3的方式,形成表面保护膜6。通过涂敷感光性聚酰亚胺并曝光,使表面保护膜6成为期望的形状。接下来,通过使导线(未图示)形成于源电极15之后,利用密封凝胶8来密封,从而完成图5所示的本实施方式所涉及的半导体器件200。
此外,也可以在半导体基板1的表面侧的工序全部完成之后进行背面电极7的形成。另外,也可以在将背面电极7与其它导体进行连接之后利用密封凝胶8来密封。
接下来,使用图6,说明作为本实施方式的半导体器件200的SiC-MOSFET的动作。
在本实施方式的SiC-MOSFET中,在相对于表面电极(第3表面电极)而向栅电极13施加阈值电压以上的正的预定的电压时,从背面电极7向表面电极流过电流,半导体器件200成为导通状态(接通状态)。相反,在相对于表面电极(第3表面电极)而向栅电极13施加阈值电压以下的预定的电压时,半导体器件200成为阻塞状态(截止状态)。
在半导体器件200是截止状态且相对于表面电极(第3表面电极)而向背面电极7施加正的高电压时,如图6所示耗尽层从终端阱区域2向半导体层1b的外周方向和半导体基板1a的方向扩展。在此,用虚线表示的位置是耗尽层的前端位置。
在向背面电极7施加作为针对表面电极的额定电压的正的电压V[V]时,如图6所示,耗尽层在半导体层1b的表面向外周方向延伸至半导体层1b的表面的位置x。此时,将位置x和源电极15的外周端的外周方向的距离设为W1,将位置x和场绝缘膜3的外周端的外周方向的距离设为W2。
在湿度高的状态下使用本实施方式的SiC-MOSFET的情况下等,在密封凝胶8含有水分而该水分浸透至聚酰亚胺等的表面保护膜6时,在场绝缘膜3的表面,从半导体器件200的外周部(图6的右侧)向表面电极(源电极15等)形成电流的泄漏路径。在形成这样的泄漏路径的情况下,在假设泄漏路径的电阻恒定时,对背面电极7施加额定电压V[V]时的位置x正上的场绝缘膜3的表面的电位为
W1V/(W1+W2) (2)
[V]。为了使对厚度t的场绝缘膜3施加的电场成为3MV/cm以下而需要满足上述式(1),这如在实施方式1中已说明那样,所以省略详细的说明。
在本实施方式中,即使在密封凝胶8、表面保护膜6含有水分而在场绝缘膜3表面形成泄漏路径的情况下,由于使对场绝缘膜3施加的电场成为3MV/cm以下,所以能够抑制半导体器件成为元件击穿,能够提高半导体器件的可靠性。
此外,在本实施方式中,说明与实施方式1不同的部分,省略与实施方式1同样的部分的详细的说明。
实施方式3.
在实施方式2中,说明了源电极15向最外周侧延伸的开关元件的例子,但也可以是与栅电极13连接的栅极焊盘向最外周侧延伸。在本实施方式中,作为栅极焊盘向最外周侧延伸的开关元件的例子,说明开关元件是SiC-MOSFET的情况。
图7是示意性地示出本发明的本实施方式所涉及的半导体器件300的终端部的结构的剖面图。如图7所示,在半导体器件300中,经由延伸至活性区域的周围的栅电极13的上部的层间绝缘膜12的开口,在栅电极13的上部的层间绝缘膜12上形成有栅极焊盘16。在此,场绝缘膜3和层间绝缘膜12的合计膜厚是t’[μm]。其它点与实施方式2相同,所以省略详细的说明。
在图7中,右侧是半导体器件300的终端部侧,左侧是在接通状态下流过主电流的活性区域侧。
接下来,使用图8,说明作为本实施方式的半导体器件300的SiC-MOSFET的动作。
在本实施方式的SiC-MOSFET中,在相对于源电极15(第3表面电极)而向栅极焊盘16(控制电极)施加阈值电压以上的正的预定的电压时,从背面电极7向源电极15流过电流,半导体器件300成为导通状态(接通状态)。相反,在相对于源电极15(第3表面电极)而向栅极焊盘16(控制电极)施加阈值电压以下的预定的电压Vgoff时,半导体器件300成为阻塞状态(截止状态)。
在向控制电极施加使半导体器件截止的电压Vgoff,并向相对表面电极的背面电极7施加作为额定电压的正的电压V[V]时,如图8所示,耗尽层在半导体层1b的表面向外周方向延伸至半导体层1b的表面的位置y。用虚线表示的位置是耗尽层的前端位置。此时,将位置y和栅极焊盘16的外周端的外周方向的距离设为W3,将位置y和场绝缘膜3的外周端的外周方向的距离设为W4。
在湿度高的状态下使用本实施方式的SiC-MOSFET的情况下等,在密封凝胶8含有水分而该水分浸透至聚酰亚胺等的表面保护膜6时,在层间绝缘膜12的表面,从半导体器件300的外周部(图7的右侧)向栅极焊盘16(控制电极)形成电流的泄漏路径。在形成这样的泄漏路径的情况下,在假设泄漏路径的电阻恒定时,向背面电极7施加额定电压V[V]时的位置y正上的层间绝缘膜12的表面的电位为
W3(V-Vgoff)/(W3+W4)+Vgoff (6)
[V]。
另外,此时的位置y的电位与额定电压V[V]相同。因此,在位置y和位置y正上的层间绝缘膜12的表面,发生
W4(V-Vgoff)/(W3+W4) (7)
[V]的电位差。
场绝缘膜3和层间绝缘膜12的合计膜厚是t’[μm],所以位置y处的场绝缘膜3、层间绝缘膜12中的平均电场为
W4(V-Vgoff)/t’(W3+W4) (8)。
场绝缘膜3和层间绝缘膜12以氧化硅或者氮化硅为主成分,所以这些绝缘膜的绝缘击穿电场是5~10MV/cm程度。但是,有时由于在接近5MV/cm的高电压下利用电场加速后的电子、空穴的注入,场绝缘膜3、层间绝缘膜12的绝缘特性降低,半导体器件300发生元件击穿。另外,还有如下报告例:即使在3MV/cm程度的情况下,如果以几十年这样的单位进行观察,则氧化膜劣化而导致击穿。
因此,在本发明的半导体器件300中,使对场绝缘膜3、层间绝缘膜12施加的电场成为3MV/cm以下。为了使对场绝缘膜3、层间绝缘膜12施加的电场成为3MV/cm以下,需要满足以下的式。
t’≥W4(V-Vgoff)/300(W3+W4) (9)
这样,根据本发明的实施方式3所涉及的半导体器件,即使在密封凝胶8、表面保护膜6含有水分而在层间绝缘膜12表面形成泄漏路径的情况下,也由于能够使对场绝缘膜3和层间绝缘膜12施加的平均电场成为3MV/cm以下,所以能够抑制半导体器件成为元件击穿,能够提高半导体器件的可靠性。
实施方式4.
在实施方式1~3中,说明了在终端部具有单一的终端阱区域2的情况的例子,但也可以将本发明应用于具有终端阱区域2和分离的多个分离阱区域2’的情况。因此,作为实施方式4,说明在具有多个分离阱区域2’的SiC-SBD中应用本发明的情况。
图9是示意性地示出实施方式4所涉及的半导体器件400的终端部的结构的剖面图。如图9所示,在半导体器件400的终端部,除了连接有作为第1表面电极的肖特基电极4的终端阱区域2以外,在半导体层1b的表层部的外周部的终端阱区域2的外周侧,从终端阱区域2分离地还形成有被分割为多个的分离阱区域2’。其它点与实施方式1相同,所以省略详细的说明。
在本实施方式中的作为半导体器件400的SiC-SBD中,在相对于表面电极(第1表面电极和第2表面电极)而向背面电极施加负的电压时,从表面电极向背面电极7流过电流,半导体器件400成为导通状态(接通状态)。
相反,在本实施方式的半导体器件400中,在相对于表面电极(第1表面电极和第2表面电极)而向背面电极7施加正的电压时,半导体器件400成为阻塞状态(截止状态)。
在半导体器件400成为截止状态的情况下,如图10所示耗尽层从与肖特基电极4连接的终端阱区域2向半导体层1b的外周方向和半导体基板1a的方向扩展。在此,用虚线表示的位置是耗尽层的前端位置。
在多个分离阱区域2’的浓度大、并且分离地形成的分离阱区域2’的间隔小的情况下,在向相对表面电极的背面电极7施加作为额定电压的正的电压时,如图10所示,耗尽层以包括从与肖特基电极4连接的终端阱区域2离散地形成的全部分离阱区域2’的方式,在半导体层1b的表面向外周方向延伸至半导体层1b的表面的位置x。此时,将位置x和电极焊盘5的外周端的外周方向的距离设为W1,将位置x和场绝缘膜3的外周端的外周方向的距离设为W2。
另外,在多个分离阱区域2’的浓度小、且分离地形成的分离阱区域2’的间隔大的情况下,在向相对表面电极的背面电极7施加作为额定电压的正的电压时,如图11所示,耗尽层以包括从与肖特基电极4连接的终端阱区域2离散地形成的一部分分离阱区域2’的方式,在半导体层1b的表面向外周方向延伸至半导体层1b的表面的位置x。
在图10、图11所示的任意情况下,针对从与肖特基电极4连接的终端阱区域2延伸的位置x,都与实施方式1的式(1)同样地,场绝缘膜3的厚度t[μm]被设定为满足
t≥W1V/300(W1+W2) (1)
的关系,这与实施方式1相同。
这样,在本实施方式的SiC-SBD中,即使在由于密封凝胶8、表面保护膜6含有水分等而在场绝缘膜3表面形成泄漏路径的情况下,也由于能够使对场绝缘膜3施加的电场成为3MV/cm以下,所以能够抑制半导体器件成为元件击穿,能够提高半导体器件的可靠性。
Claims (11)
1.一种半导体器件,具备:
半导体基板;
第1导电类型的半导体层,形成于所述半导体基板上;
场绝缘膜,形成于所述半导体层的表面上;
表面电极,以比所述场绝缘膜靠内周侧并延伸到所述场绝缘膜上的方式形成于所述半导体层的表面上;
第2导电类型的阱区域,与所述表面电极连接而形成于所述半导体层的表层部,比所述表面电极的外周端更向外周侧延伸;
表面保护膜,以覆盖所述表面电极的外周端及所述场绝缘膜的外周端的方式形成于所述表面电极及所述场绝缘膜上,所述表面保护膜由绝缘材料构成;
密封凝胶,形成于所述半导体层及所述表面保护膜上的所述半导体层的外周部;以及
背面电极,形成于所述半导体基板的背面,
将在向所述背面电极施加额定电压V[V]时从所述阱区域向所述半导体层的外周方向扩展的耗尽层的前端的、所述半导体层的表面处的位置设为x,
将位置x和所述表面电极的外周端的外周方向的距离设为W1,
将位置x和所述场绝缘膜的外周端的外周方向的距离设为W2,
将所述场绝缘膜的膜厚设为t[μm],
以使位置x处的所述场绝缘膜中的电场W2V/t(W1+W2)成为3MV/cm以下的方式规定终端部的布局。
2.根据权利要求1所述的半导体器件,其特征在于,
所述场绝缘膜以氧化硅为主成分。
3.根据权利要求1所述的半导体器件,其特征在于,
所述表面电极与所述半导体层进行肖特基连接。
4.一种半导体器件,具备:
半导体基板;
第1导电类型的半导体层,形成于所述半导体基板上;
场绝缘膜,形成于所述半导体层的表面上;
层间绝缘膜,形成于所述场绝缘膜的表面上;
表面电极,形成于所述层间绝缘膜上;
第2导电类型的阱区域,与所述表面电极连接而形成于所述半导体层的表层部;
控制电极,与所述表面电极分离地形成于所述层间绝缘膜上;
表面保护膜,以覆盖所述控制电极的外周端及所述层间绝缘膜的外周端的方式形成于所述控制电极及所述层间绝缘膜上,所述表面保护膜由绝缘材料构成;
密封凝胶,形成于所述半导体层及所述表面保护膜上的所述半导体层的外周部;以及
背面电极,形成于所述半导体基板的背面,
将在向所述背面电极施加额定电压V[V]并对所述控制电极施加使半导体器件截止的电压Vgoff时从所述阱区域向所述半导体层的外周方向扩展的耗尽层的前端的、所述半导体层的表面处的位置设为y,
将位置y和所述控制电极的外周端的外周方向的距离设为W3,
将位置y和所述场绝缘膜的外周端的外周方向的距离设为W4,
将所述场绝缘膜和所述层间绝缘膜的合计膜厚设为t’[μm],
以使位置y处的所述场绝缘膜以及所述层间绝缘膜中的电场W4(V-Vgoff)/t’(W3+W4)成为3MV/cm以下的方式规定终端部的布局。
5.根据权利要求4所述的半导体器件,其特征在于,
所述场绝缘膜以及所述层间绝缘膜以氧化硅为主成分。
6.根据权利要求1或者4所述的半导体器件,其特征在于,
所述表面保护膜是聚酰亚胺。
7.根据权利要求1或者4所述的半导体器件,其特征在于,
所述凝胶是硅凝胶。
8.根据权利要求1或者4所述的半导体器件,其特征在于,
所述半导体层的表层部的所述阱区域还具有:
第2导电类型的终端阱区域,形成于终端部;以及
第2导电类型的活性阱区域,与所述终端阱区域分离地设置于活性区域,
所述表面电极与所述阱区域进行欧姆连接。
9.根据权利要求1或者4所述的半导体器件,其特征在于,
除了所述阱区域以外,在所述阱区域的外周侧还具备相互分离的多个分离阱区域。
10.根据权利要求1或者4所述的半导体器件,其特征在于,
所述半导体基板以及所述半导体层由宽带隙半导体材料构成。
11.根据权利要求1或者4所述的半导体器件,其特征在于,
所述半导体基板以及所述半导体层由碳化硅半导体材料构成。
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