CN107527950A - 功率半导体装置及其制造方法 - Google Patents
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Abstract
本申请公开了功率半导体装置及其制造方法。提供了一种功率半导体装置,包括:一对栅电极,在衬底中分别设置在彼此间隔开的第一沟槽和第二沟槽中;具有第一导电类型的本体区域,设置在第一沟槽和第二沟槽之间;具有第一导电类型的一对浮置区域,其彼此间隔开并且分别包围第一沟槽和第二沟槽的底表面和至少一个侧表面;以及具有第二导电类型的漂移区域,其这对浮置区域的下方延伸穿过这对浮置区域之间的区域直至所述本体区域,其中,在所述漂移区域中,这对浮置区域之间的第二导电类型的掺杂浓度高于在这对浮置区域下方的第二导电类型的掺杂浓度。
Description
相关申请的交叉引用
本申请要求于2016年6月21日在韩国知识产权局提交的韩国专利申请No.10-2016-0077602的优先权和权益,其全部内容通过引证结合于此。
技术领域
本发明涉及功率半导体装置及其制造方法,更具体地,涉及一种绝缘栅双极型晶体管(IGBT)装置及其制造方法。
背景技术
绝缘栅双极型晶体管(IGBT)通过金属氧化物半导体(MOS)技术和双极物理学的功能集成而开发。其特点是具有低饱和电压和快速开关功能。其应用范围扩展到无法用晶闸管、双极晶体管、MOSFET等实现的应用。这也是下一代功率半导体装置,该装置主要用于在电压范围300V以上中广泛使用的高效率高速功率***中。自20世纪70年代的功率MOSFET的发展以来,MOSFET已在需要快速开关功能的领域中用作开关装置,而双极晶体管、晶闸管、GTO等已用于在中到高电压中需要大量电流传导的领域中。20世纪80年代初开发的IGBT在输出特性方面具有比双极晶体管更好的电流能力,并且在输入特性方面具有类似MOSFET的栅极驱动特性,因此,能够以约100KHz的高速进行开关。因此,IGBT用在从工业到家用电子的广泛应用中,因为该器件不仅用于替代MOSFET、双极晶体管和晶闸管,而且用于建立新的应用***。
韩国特许公开号20140057630(于2014年5月13日公开,题目为“IGBT andmanufacturing method thereof”)是相关的现有技术。
发明内容
本发明的目的在于提供一种能够降低电阻并改善短路和击穿电压特性的功率半导体装置及其制造方法。然而,这些问题是说明性的,因此本发明的范围不限于此。
根据本发明的一方面,提供了一种功率半导体装置,用于解决上述问题。该功率半导体装置包括:一对栅电极,分别设置在衬底中彼此间隔开的第一沟槽和第二沟槽中;具有第一导电类型的本体区域,其在衬底中设置在第一沟槽和第二沟槽之间;具有第一导电类型的一对浮置区域,在衬底中彼此间隔开并且分别包围第一沟槽和第二沟槽的底表面和至少一个侧表面;以及具有第二导电类型的漂移区域,其在衬底中从具有第一导电类型的一对浮置区域的下方延伸穿过具有第一导电类型的一对浮置区域之间的区域而到达具有第一导电类型的所述本体区域,其中,在所述漂移区域中,具有第一导电类型的这对浮置区域之间的第二导电类型的掺杂浓度高于具有第一导电类型的这对浮置区域下方的第二导电类型的掺杂浓度。
在功率半导体装置中,具有第一导电类型的本体区域的最大掺杂深度可以小于第一沟槽和第二沟槽的深度,并且具有第一导电类型的浮置区域的最大掺杂深度可以大于第一沟槽和第二沟槽的深度。在此处,在所述漂移区域中,具有第一导电类型的这对浮置区域之间的第二导电类型的掺杂浓度和所述第一沟槽与所述第二沟槽之间的第二导电类型的掺杂浓度可以大于具有第一导电类型的这对浮置区域下方的第二导电类型的掺杂浓度。
功率半导体装置还可以包括:在具有第一导电类型的这对浮置区域之间并且在所述第一沟槽和所述第二沟槽之间的基极电流路径,其中,在具有第一导电类型的这对浮置区域的底表面的区域中可以产生最大电场。
在功率半导体装置中,在从所述衬底的上表面穿过具有第一导电类型的这对浮置区域之间的区域到达所述衬底的下表面的电场的垂直分布中,最大电场所在的深度可以大于第一沟槽和第二沟槽的深度。
在功率半导体装置中,所述衬底可以包括晶片和在所述晶片上生长的外延层,并且具有第一导电类型的浮置区域的下部分可以包括晶片和外延层之间的边界面。
功率半导体装置还可以包括:一对源极区域,其彼此间隔开并在衬底中设置为分别邻近第一沟槽和第二沟槽。
在功率半导体装置中,第二导电类型和第一导电类型可以具有相反的导电类型,并且可各自是n型和p型中的一个。
根据本发明的另一方面,提供了一种用于制造功率半导体装置的方法。所述方法包括:将具有第一导电类型的杂质注入晶片上的第一区域;将具有第二导电类型的杂质注入晶片上的第二区域,所述杂质的掺杂浓度高于在晶片中具有第二导电类型的杂质的掺杂浓度;在晶片上形成外延层;在包括所述第一区域和所述第二区域之间的边界的区域中分别形成彼此间隔开的第一沟槽和第二沟槽,同时移除所述外延层的一部分;通过使杂质扩散,形成具有第一导电类型的一对浮置区域以及具有第二导电类型的漂移区域的至少一部分,所述浮置区域彼此间隔开并且包围所述第一沟槽和第二沟槽的底表面和至少一个侧表面,并且所述漂移区域从具有第一导电类型的这对浮置区域的下方延伸到具有第一导电类型的这对浮置区域之间的区域;通过将杂质注入第一沟槽和第二沟槽之间的区域中,形成具有第一导电类型的本体区域和一对源极区域,所述一对源极区域彼此间隔开并且设置为在具有第一导电类型的本体区域中与所述第一沟槽和第二沟槽相邻;并且通过用绝缘膜涂覆第一沟槽和第二沟槽的内壁并用栅电极材料填充第一沟槽和第二沟槽来形成栅电极。
在制造功率半导体装置的方法中,具有第一导电类型的浮置区域的下部可以包括晶片和外延层之间的边界面,其中在该下部中在基极电流路径中产生最大电场。
根据如上所述的本发明的实施例,提供了一种功率半导体装置,其中,即使沟槽之间的距离变窄,也形成基极电流供应路径,并提供丰富的基极电流,从而增强了鲁棒性。此外,在增加单元密度的同时,缓解了局部温度上升,改善了短路特性,并且可以减缓击穿电压的降低。当然,本发明的范围不受这些效果的限制。
附图说明
图1是示出根据本发明的实施例的功率半导体装置的单元结构的截面图;
图2是示出图1所示的根据本发明的实施例的功率半导体装置中的在G方向的电场的大小的曲线图;以及
图3是示出根据本发明的实施例的功率半导体装置的制造方法的截面图。
<附图标记说明>
1:衬底
10:漂移区域
20a、20b:沟槽
30a、30b:浮置区域
42:本体区域
44:源极区域
50a、50b:栅电极
具体实施方式
在下文中,将参考附图详细描述本发明的实施例。然而,应当理解,本发明不限于下面描述的实施例,而是可以以各种其他形式体现。以下实施例旨在给出本公开的更完整的描述,并且被提供以便向本领域技术人员充分地传达本公开的范围。此外,为了便于说明,至少一些部件的尺寸可被夸大或缩小。在附图中相同的附图标记表示相同的元件。
在本说明书中,第一导电类型和第二导电类型可以具有相反的导电类型,并且可以分别是n型和p型中的一个。例如,第一导电类型可以是p型,第二导电类型可以是n型,在附图中示意性地示出这些导电类型。然而,本发明的技术思想不限于此。例如,第一导电类型可以是n型,第二导电类型可以是p型。
图1是示出根据本发明的实施例的功率半导体装置的单元结构的截面图。
参考图1,根据本发明的实施例的功率半导体装置100包括分别设置在衬底1中彼此间隔开的第一沟槽20a和第二沟槽20b中的一对栅电极50a和50b。此处,衬底1可以被理解为包括晶片和在晶片上外延生长的外延层。
根据本发明的实施例的功率半导体装置100包括具有第一导电类型的本体区域42,在衬底1中设置在第一沟槽20a和第二沟槽20b之间;具有第二导电类型的一对源极区域44a和44b,彼此间隔开并在衬底1中设置为分别与第一沟槽20a和第二沟槽20b相邻。
根据本发明的实施例的功率半导体装置100包括:具有第一导电类型的浮置区域30a,该浮置区域30a包围衬底1中的第一沟槽20a的底表面和至少一个侧表面;以及具有第一导电类型的浮置区域30b,该浮置区域30b围绕第二沟槽20b的底表面和至少一个侧表面。具有第一导电类型的浮置区域30a和30b在衬底1中彼此间隔开。相对于衬底1的顶表面1s至浮置区域30a和30b的底表面的深度大于至第一沟槽20a和第二沟槽20b的底表面的深度。即,具有第一导电类型的浮置区域30a和30b的最大掺杂深度可以大于第一沟槽20a和第二沟槽20b的深度。
根据本发明的实施例的功率半导体装置100包括具有第二导电类型的漂移区域10,该漂移区域10在衬底1中从具有第一导电类型的一对浮置区域30a和30b的下方延伸穿过具有第一导电类型的浮置区域30a和30b之间的区域14而到达具有第一导电类型的本体区域42。具体地,在漂移区域10中,具有第一导电类型的这对浮置区域30a和30b之间的第二导电类型的掺杂浓度N1高于具有第一导电类型的这对浮置区域30a和30b下方的第二导电类型的掺杂浓度N2。
另一方面,具有第一导电类型的本体区域42的最大掺杂深度小于第一沟槽20a和第二沟槽20b的深度,并且具有第一导电类型的浮置区域30a和30b的最大掺杂深度可以大于第一沟槽20a和第二沟槽20b的深度。此处,在漂移区域10中,具有第一导电类型的这对浮置区域30a和30b之间的第二导电类型的掺杂浓度和第一沟槽20a和第二沟槽20b之间的第二导电类型的掺杂浓度可以大于具有第一导电类型的这对浮置区域30a和30b下方的第二导电类型的掺杂浓度。
电连接到栅电极50a和50b的导电图案64以及电连接到源极区域44a和44b以及本体区域42的导电图案68设置在衬底1的上部上。导电图案64和68用作电极或触点,并且可以利用***其间的绝缘图案62和66而电绝缘。另一方面,集电极72设置在衬底1的下方,虽然未图示,但是形成集电极72之前形成具有第二导电类型的缓冲层和/或具有第一导电类型的集电极层。
与上述根据本发明的实施例的功率半导体装置100相比,如果浮置区域30a和30b没有设置在第一沟槽20a和第二沟槽20b的底部,则问题在于,电场在第一沟槽20a和第二沟槽20b的底部增大。此外,如果浮置区域30a和30b仅设置在第一沟槽20a和第二沟槽20b的底部,则问题在于,当第一沟槽20a和第二沟槽20b之间的距离在提供IGBT的基极电流的MOSFET的G方向减小时,基极电流路径受到第一导电类型的杂质的扩散的限制,因此,单元节距不能降低在一定距离以下。
图2是示出图1所示的根据本发明的实施例的功率半导体装置中电场在G方向的大小的曲线图。
参考图1和图2,在根据本发明实施例的功率半导体装置中,具有第一导电类型的这对浮置区域30a和30b之间的第二导电类型的掺杂浓度N1大于具有第一导电类型的浮置区域30a和30b的下部区域12中的第二导电类型的掺杂浓度N2。因此,即使第一沟槽20a和第二沟槽20b之间的距离变窄,也形成基极电流供给路径,并提供充足的基极电流,形成N1和P1之间的平衡,使得在E表面上产生最大电场,从而增强鲁棒性。
即,N1区域的形成可以有助于减少或防止以下现象:当第一沟槽20a和第二沟槽20b之间的距离F在MOSFET供应IGBT的基极电流的G方向减小时,在浮置区域30a和30b中的具有第一导电类型的杂质扩散,以限制基极电流路径。在根据本发明的实施例的功率半导体装置100中,获得具有距离F的高单元密度,如果采用相同的跨导,则距离F更窄,使得G部分中的电流密度对于相同的总电流降低,并且防止局部温度上升,从而改善短路特性。
通过该原理改善了IGBT电阻和短路特性,并且区域14的第二导电类型的杂质浓度N1和浮置区域30a和30b的第一导电类型的杂质浓度P1的电荷的总量被控制为,使得在E表面上产生最大电场,从而提高鲁棒性。此处,产生最大电场G2的E表面是比第一沟槽20a、第二沟槽20b的底表面低的表面。另一方面,在修改实施例中,产生最大电场G3的表面可以具有与浮置区域30a和30b的底表面相同的高度。
如果将施加电压时的n型耗尽中的静电场与电荷量之间的关系简化为沿C方向的一个维度,则dE/dx=(1/ε)*n,这可以被认为是仅n型掺杂的函数。然而,在IGBT操作期间注入载流子时,由于注入电荷的量的影响,其将变为dE/dx=(1/ε)*(n+h-e),并且在传统结构中,当空穴密度在关断期间在G部分中处于过剩时,由于空穴浓度的变化引起的电场变化率的增加减小了相同最大电场下的电场面积,从而突然降低击穿电压。然而,在这种结构中,在第一沟槽20a和第二沟槽20b的底表面与本体区域42的底表面之间提供了一部分,其中,电场的变化率为负,使得电场梯度的增加增大了电场的面积,从而减轻了击穿电压的降低。
图3是示出根据本发明的实施例的功率半导体装置的制造方法的截面图。
参考图3的(a)和(b),具有第一导电类型的杂质注入到晶片A上的第一区域I内(P1注入),并且具有第二导电类型的杂质注入第二区域II(N1注入),具有比晶片中具有第二导电类型的杂质A的掺杂浓度高的掺杂浓度。
参考图3的(c),在晶片A上形成外延层B。可以理解,衬底1包括晶片A和在晶片上外延生长的外延层B。在生长外延层B之后,可以进行通过外延层B的上表面注入额外杂质的掺杂工艺。
参考图3的(d),去除外延层B的部分,并且可以在包括第一区域I和第二区域II之间的边界的区域中分别形成彼此间隔开的第一沟槽20a和第二沟槽20b。
参考图3的(e),通过诸如热处理等扩散处理,同时注入第一导电类型和第二导电类型的杂质,可以形成具有第一导电类型的一对浮置区域30a和30b,彼此间隔开并且包围第一沟槽20a和第二沟槽20b的底表面和至少一个侧表面。此外,可以形成具有第二导电类型的漂移区域10的至少一部分,其从具有第一导电类型的这对浮置区域30a和30b下方延伸到具有第一导电类型的这对浮置区域30a和30b之间的区域。在此处,具有第一导电类型的浮置区域30a和30b的下部分可以包括晶片A和外延层B之间的边界面F。
参考图3的(f),杂质注入到第一沟槽20a和第二沟槽20b之间的区域内,以形成具有第一导电类型的本体区域42和一对源极区域44a和44b,这对源极区域44a和44b彼此间隔开并且在具有第一导电类型的本体区域42中设置为邻近第一沟槽20a和第二沟槽20b。随后,第一沟槽20a和第二沟槽20b的内壁可以涂布(line)绝缘膜,并且第一沟槽20和第二沟槽20b可以填充有栅电极材料,以形成栅电极50a和50b。
参考图3的(g),图1所示的功率半导体装置的单元结构可以通过另外形成绝缘图案66和金属布线图案68来实现。
在通过包括这些步骤的根据本发明的实施例的制造方法实现的功率半导体装置100中,在基极电流路径G中产生最大电场的位置可以是具有第一导电类型的浮置区域30a和30b下方的区域,该区域包括在晶片A和外延层B之间的边界面F。
虽然已经参考示例性实施例描述了本发明,但是应当理解,本发明不限于所公开的示例性实施例,而是相反,旨在覆盖包括在所附权利要求的精神和范围内的各种修改和等同设置。因此,本发明的真实范围应由所附权利要求的技术思想确定。
Claims (10)
1.一种功率半导体装置,包括:
一对栅电极,分别设置在衬底中彼此间隔开的第一沟槽和第二沟槽中;
具有第一导电类型的本体区域,在所述衬底中设置在所述第一沟槽和所述第二沟槽之间;
具有第一导电类型的一对浮置区域,在所述衬底中彼此间隔开并且分别包围所述第一沟槽和所述第二沟槽的底表面和至少一个侧表面;以及
具有第二导电类型的漂移区域,在所述衬底中从具有第一导电类型的所述一对浮置区域的下方延伸穿过具有第一导电类型的所述一对浮置区域之间的区域而直至具有第一导电类型的所述本体区域,
其中,在所述漂移区域中,具有第一导电类型的所述一对浮置区域之间的第二导电类型的掺杂浓度高于具有第一导电类型的所述一对浮置区域下方的第二导电类型的掺杂浓度。
2.根据权利要求1所述的功率半导体装置,
其中,具有第一导电类型的所述本体区域的最大掺杂深度小于所述第一沟槽和所述第二沟槽的深度,并且具有第一导电类型的浮置区域的最大掺杂深度大于所述第一沟槽和所述第二沟槽的深度。
3.根据权利要求2所述的功率半导体装置,
其中,在所述漂移区域中,在有第一导电类型的所述一对浮置区域之间的第二导电类型的掺杂浓度和在所述第一沟槽与所述第二沟槽之间的第二导电类型的掺杂浓度大于具有第一导电类型的所述一对浮置区域下方的第二导电类型的掺杂浓度。
4.根据权利要求1所述的功率半导体装置,还包括:
在具有第一导电类型的所述一对浮置区域之间并且在所述第一沟槽和所述第二沟槽之间的基极电流路径,
其中,在具有第一导电类型的所述一对浮置区域的底表面的区域中产生最大电场。
5.根据权利要求1所述的功率半导体装置,
其中,在从所述衬底的上表面穿过具有第一导电类型的所述一对浮置区域之间的区域到所述衬底的下表面的电场的垂直分布中,最大电场所在的深度大于所述第一沟槽和所述第二沟槽的深度。
6.根据权利要求1所述的功率半导体装置,
其中,所述衬底包括晶片和在所述晶片上生长的外延层,并且
其中,具有第一导电类型的浮置区域的下部包括所述晶片和所述外延层之间的边界面。
7.根据权利要求1所述的功率半导体装置,还包括:
一对源极区域,在所述衬底中彼此间隔开并设置为分别邻近所述第一沟槽和所述第二沟槽。
8.根据权利要求1至7中任一项所述的功率半导体装置,
其中,第二导电类型和第一导电类型具有相反的导电类型,并且分别是n型和p型中的一个。
9.一种用于制造功率半导体装置的方法,所述方法包括:
将具有第一导电类型的杂质注入晶片上的第一区域;
将具有第二导电类型的杂质注入所述晶片上的第二区域,具有第二导电类型的所述杂质的掺杂浓度高于在所述晶片中的具有第二导电类型的杂质的掺杂浓度;
在所述晶片上形成外延层;
在包括所述第一区域和所述第二区域之间的边界的区域中分别形成彼此间隔开的第一沟槽和第二沟槽,同时移除所述外延层的一部分;
通过使杂质扩散,形成具有第一导电类型的一对浮置区域以及具有第二导电类型的漂移区域的至少一部分,所述一对浮置区域彼此间隔开并且分别包围所述第一沟槽和所述第二沟槽的底表面和至少一个侧表面,并且所述漂移区域从具有第一导电类型的所述一对浮置区域的下方延伸到具有第一导电类型的所述一对浮置区域之间的区域;
通过将杂质注入所述第一沟槽和所述第二沟槽之间的区域内,形成具有第一导电类型的本体区域和一对源极区域,所述一对源极区域彼此间隔开并且设置为在具有第一导电类型的所述本体区域中与所述第一沟槽和所述第二沟槽相邻;并且
通过用绝缘膜涂布所述第一沟槽和所述第二沟槽的内壁并用栅电极材料填充所述第一沟槽和所述第二沟槽来形成栅电极。
10.根据权利要求9所述的方法,
其中,在基极电流路径中产生最大电场所在的位置是具有第一导电类型的浮置区域的下部,具有第一导电类型的浮置区域的下部包括所述晶片和所述外延层之间的边界面。
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CN110634947B (zh) * | 2018-06-21 | 2023-06-27 | 现代摩比斯株式会社 | 功率半导体器件及其制造方法 |
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DE102017210257A1 (de) | 2017-12-21 |
CN107527950B (zh) | 2020-10-27 |
US9905681B2 (en) | 2018-02-27 |
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