CN107452707A - 含热、电性能改善的再分布结构的芯片载体及半导体器件 - Google Patents
含热、电性能改善的再分布结构的芯片载体及半导体器件 Download PDFInfo
- Publication number
- CN107452707A CN107452707A CN201710398130.9A CN201710398130A CN107452707A CN 107452707 A CN107452707 A CN 107452707A CN 201710398130 A CN201710398130 A CN 201710398130A CN 107452707 A CN107452707 A CN 107452707A
- Authority
- CN
- China
- Prior art keywords
- groove
- dielectric layer
- filled
- layer
- chip carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/24246—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
一种芯片载体包括再分布结构,其中,所述再分布结构包括:沿水平方向延伸的介电层;布置在介电层之上并沿水平方向延伸的第一导电层;布置在介电层中并沿水平方向延伸的沟槽;以及填充沟槽的填充材料,其中,填充材料不同于介电层的材料。
Description
技术领域
本公开总体上涉及芯片载体和半导体器件。具体地,本公开涉及包括具有改善的热和电性能的再分布结构的芯片载体和半导体器件。
背景技术
电子器件可包括构造成能够提供电流的路线选择和再分布的结构。形成这种再分布结构的部件的设计和尺寸可能与在电子器件的操作期间产生的电流的强度有关。电子器件的制造者寻求提供具有改善的热和电性能的解决方案。
发明内容
多个方面涉及一种芯片载体,所述芯片载体包括再分布结构,所述再分布结构包括:沿水平方向延伸的介电层;布置在介电层之上并沿水平方向延伸的第一导电层;布置在介电层中并沿水平方向延伸的沟槽;以及填充沟槽的填充材料,其中,所述填充材料不同于介电层的材料。
根据本发明的一个可选实施例,所述填充材料是导电的并且电耦接至第一导电层,其中,被填充的沟槽形成导电线路。
根据本发明的一个可选实施例,填充材料包括下述中的至少一种:碳;铜;金;镍;锡;铝;碳、铜、金、镍、锡、铝的合金。
根据本发明的一个可选实施例,填充材料是导热的,被填充的沟槽形成导热线路。
根据本发明的一个可选实施例,填充材料包括氮化硅、氮化硼、氧化铝和氮化铝中的至少一种。
根据本发明的一个可选实施例,被填充的沟槽构造成能够将第一电子部件热耦接至热传感器和散热器中的至少一个。
根据本发明的一个可选实施例,被填充的沟槽构造成能够使热能的传导路线绕过或远离第二电子部件。
根据本发明的一个可选实施例,所述芯片载体还包括:竖直地延伸穿过介电层的导电的过孔连接部,其中,第一导电层电耦接至所述过孔连接部。
根据本发明的一个可选实施例,所述芯片载体还包括:沿水平方向延伸并电耦接至第一导电层的第二导电层,其中,介电层布置在第一导电层与第二导电层之间,第一导电层和第二导电层构造成能够沿相同的水平方向传导电流。
根据本发明的一个可选实施例,所述芯片载体还包括:布置在介电层中并沿水平方向延伸的平行的多个沟槽,其中,所述多个沟槽中的每一个都填充有填充材料。
根据本发明的一个可选实施例,所述芯片载体包括:构造成能够安装半导体芯片的主表面;以及与所述主表面相反的构造成能够安装电接触元件的相反表面,其中,芯片载体构造成能够将半导体芯片电耦接至所述电接触元件。
多个方面涉及一种半导体器件,所述半导体器件包括:材料层;嵌入材料层中的半导体芯片;以及电耦接至半导体芯片的再分布结构。所述再分布结构包括:沿水平方向延伸的介电层;布置在介电层之上并沿水平方向延伸的导电层;布置在介电层中并沿水平方向延伸的沟槽;以及填充沟槽的填充材料,其中,所述填充材料不同于介电层的材料。
根据本发明的一个可选实施例,半导体芯片嵌入的材料层包括层合材料、环氧树脂、填充式环氧树脂、玻璃纤维填充式环氧树脂、酰亚胺、热塑性塑料、热固性塑料聚合物和共混聚合物中的至少一种。
根据本发明的一个可选实施例,填充材料是导电的并且电耦接至导电层,其中,被填充的沟槽形成导电线路。
根据本发明的一个可选实施例,填充材料是导热的,被填充的沟槽形成导热线路。
多个方面涉及一种制造再分布结构的方法,其中,所述方法包括下述行为:形成介电层,其中,所述介电层沿水平方向延伸;在介电层中形成沟槽,其中,所述沟槽沿水平方向延伸;用与介电层的材料不同的填充材料填充沟槽;以及在介电层之上形成导电层。
根据本发明的一个可选实施例,所述方法还包括:在介电层中形成过孔,其中,所述过孔竖直地延伸穿过介电层;以及用导电材料填充过孔,其中,导电层电耦接至被填充的过孔。
根据本发明的一个可选实施例,填充材料是导热的和导电的中的至少一种。
根据本发明的一个可选实施例,利用相同的成形工艺形成过孔和沟槽。
根据本发明的一个可选实施例,填充过孔、填充沟槽和形成导电层的行为中的至少两个是基于相同的工艺。
根据本发明的一个可选实施例,形成沟槽包括激光钻孔、等离子蚀刻、光刻、步冲、布线中的至少一种。
根据本发明的一个可选实施例,填充沟槽包括下述中的至少一种:水电镀;直接电镀;保形电镀;超保形电镀;平版印刷结构化;双镶嵌工艺;填充和固化焊膏、烧结膏、导电胶和焊膏、烧结膏、导电胶的组合中的至少一种。
附图说明
附图被列入以提供对多个方面的进一步理解,并且被并入且构成本说明书的一部分。附图示出了多个方面,并与说明书一起用于解释多个方面的原理。参照下文的详细说明,其他方面和方面的许多预期优势将更好地被理解进而将更易于领会。附图的元件不一定相对于彼此成比例地绘制。相同的附图标记可表示相应的相似部件。
图1示意性地示出了根据本公开的芯片载体100的侧剖视图。芯片载体100包括具有介电层、可选的过孔连接部和导电层的再分布结构。另外,被填充的沟槽布置在介电层中。
图2示意性地示出了根据本公开的半导体器件200的侧剖视图。半导体器件200包括材料层、嵌入材料层中的半导体芯片和类似于图1的再分布结构。
图3包括图3A至3F,示意性地示出了根据本公开的制造再分布结构300的方法的侧剖视图。制造好的再分布结构300可类似于图1和图2。
图4示意性地示出了包括导电层、布置在中间的介电层、和过孔连接部的再分布结构400的细节的透视图。
图5示意性地示出了根据本公开的类似于图4的再分布结构500的细节的透视图。此外,被填充的沟槽布置在介电层中。
图6示意性地示出了根据本公开的包括芯片载体的电子器件600的侧剖视图。
图7示意性地示出了根据本公开的包括芯片载体的电子器件700的侧剖视图。
图8示意性地示出了根据本公开的包括半导体芯片和再分布结构的半导体器件800的侧剖视图。
图9示意性地示出了根据本公开的包括半导体芯片和再分布结构的半导体器件900的侧剖视图。
图10示意性地示出了根据本公开的包括半导体芯片和再分布结构的半导体器件1000的侧剖视图。
图11示意性地示出了根据本公开的包括半导体芯片和再分布结构的半导体器件1100的侧剖视图。
图12示意性地示出了根据本公开的包括再分布结构的电子器件1200的俯视图。
具体实施方式
下文的详细描述参照附图,可实践本公开的特定方面在附图中示例性地示出。在这方面,方向术语、例如“上”、“下”、“前”、“后”等可参照所描述的附图的方位来使用。由于所描述的器件的部件可以以多个不同的方位布置,所以方向术语可用于说明的目的,而绝不是限制性的。在不脱离本公开的概念的情况下,可利用其他方面并且可进行结构或逻辑改变。因此,以下详细描述不应理解为限制性的,本公开的概念由所附权利要求限定。
本文描述的器件可包括或可对应于芯片载体。例如,芯片载体可包括在半导体器件、例如倒装芯片器件或BGA(球栅阵列,Ball Grid Array)器件中。芯片载体可构造成能够借助于包括在芯片载体中的如下所述的再分布结构来提供芯片载体内的或者通过芯片载体的电信号和电流的再分布。芯片载体可用作其上可安装一个或一个以上的电子部件的载体。在这方面,芯片载体可提供具有可接近所安装的部件的热膨胀系数(CTE:Coefficientof Thermal Expansion)的CTE的稳定平台,以便避免由CTE错配引起的机械应力。芯片载体可提供安装的部件至例如印刷电路板(PCB:Printed Circuit Board)的电连接和/或热连接。
本文描述的器件可包括一个或一个以上的半导体芯片。所述半导体芯片可以是不同类型的,并且可通过不同的技术来制造。通常,半导体芯片可包括集成电路、无源电子部件、有源电子部件等。集成电路可设计成逻辑集成电路、模拟集成电路、混合信号集成电路、功率集成电路等。半导体芯片不需要由特定的半导体材料制造,并且可包含不是半导体的无机和/或有机材料,例如绝缘体、塑料、金属等。在一示例中,半导体芯片可由元素半导体材料、例如Si等制成。在另一示例中,半导体芯片可由化合物半导体材料、例如GaN、SiC、SiGe、GaAs等制成。
本文描述的器件可包括再分布结构。例如,再分布结构可包括在芯片载体或半导体器件中。下面提供根据本公开的再分布结构的各种应用。
再分布结构可包括一个或多个导电层。特别地,所述导电层可以是平坦的并且可沿水平方向延伸。导电层可用作布线层并且构造成能够提供器件的电子部件之间的电互连和/或热互连。在一示例中,布线层可提供安装在包括再分布结构的芯片载体上的半导体芯片与耦接至芯片载体的PCB之间的互连。在另一示例中,布线层可提供包括再分布结构的半导体器件的半导体芯片之间的互连。由此,导电层可构造成能够使得器件的电子部件(例如半导体芯片)的I/O焊盘在器件的其他位置可用。
再分布结构的导电层可以以任何期望的几何形状和/或任何期望的材料组分制造。例如,导电层可被结构化并且可具有导体线路(或导体迹线)的形状,但也可成覆盖一个区域的层的形式。特别地,导电层可以是金属化层。任何合适的金属,例如铝、镍、钯、钛、钛钨、银、锡、金、钼、钒、铜和相关金属合金中的至少一种可用于制造金属化层。
再分布结构可包括一个或多个介电层。特别地,介电层可以是平坦的并且可沿水平方向延伸。介电层可尤其布置在导电层之间并且构造成能够使导电层彼此电绝缘。介电层可包括聚合物、聚酰亚胺、环氧树脂、硅树脂、层合材料等中的至少一种或可由聚合物、聚酰亚胺、环氧树脂、硅树脂、层合材料等中的至少一种制成。
再分布结构可包括一个或多个过孔连接部(或通孔连接部),所述过孔连接部可构造成能够使布置在不同层面上的导电层电耦接,由此提供不同的导电层之间的电互连。特别地,过孔连接部可沿竖直方向延伸通过水平介电层。也就是说,过孔连接部尤其可沿基本上垂直于导电层的方向延伸。例如,再分布结构的过孔连接部和导电层可由类似的材料制造。
再分布结构可包括布置在介电层中并沿水平方向延伸的一个或多个沟槽。在一示例中,沟槽可竖直地延伸穿过整个介电层,即从介电层的下水平表面延伸至介电层的上水平表面。在另一示例中,沟槽可仅部分地延伸至相应的介电层中。沟槽的深度可以是恒定的,或者可在沟槽的尺度上变化。根据所考虑的应用,沟槽可以以任何期望的几何形状制造。
再分布结构可包括填充材料,所述填充材料可至少部分地填充沟槽,在一示例中,被填充的沟槽可具有线路(或迹线)的形状。在另外的示例中,被填充的沟槽可具有条、带、矩形等形式。被填充的沟槽可与相邻的导电层直接接触或者不与相邻的导电层直接接触。填充材料尤其可不同于介电层的材料。
填充材料可以是导电的并且可与再分布结构的导电层中的一个或一个以上相接触。被填充的沟槽可由此电耦接至导电层,其中,被填充的沟槽可形成导电线路。也就是说,被填充的沟槽可支持或增强通过导电层的电流的传导。导电填充材料例如可包括碳、铜、金、镍、锡、铝、其合金等中的至少一种。
填充材料可以是导热的并且可形成导热线路。在此,被填充的沟槽可与再分布结构的导电层相接触或不接触。在一示例中,这种导热线路可构造成能够将第一电子部件热耦接至热传感器和散热器中的至少一个。在另一示例中,导热线路可构造成能够引导热能绕过或远离可能热敏的电子部件。导热的填充材料可包括碳、氮化硅、氮化硼、氧化铝、氮化铝等中的至少一种。
本文描述的器件可包括可至少部分地嵌有根据本公开的器件的一个或一个以上的半导体芯片的材料层。材料层可包括层合材料、环氧树脂、填充式环氧树脂、玻璃纤维填充式环氧树脂、酰亚胺、热塑性塑料、热固性塑料聚合物(duroplast polymer)、共混聚合物中的至少一种。
图1示意性地示出了根据本公开的芯片载体100的侧剖视图。芯片载体100以概括的方式示出,以便定性地说明本公开的多个方面。芯片载体100可包括为了简单起见而未示出的另外的部件。例如,芯片载体100还可包括其他根据本公开的器件的一个或一个以上的部件。
芯片载体100可包括再分布结构10。再分布结构10可包括介电层12,所述介电层12可沿水平方向延伸。再分布结构10还可包括可选的导电的过孔连接部14,所述过孔连接部14可竖直地延伸穿过介电层12。再分布结构10还可包括布置在介电层12之上并沿水平方向延伸的导电层16。导电层16可电耦接至可选的过孔连接部14。再分布结构10还可包括布置在介电层12中并沿水平方向延伸的沟槽18。再分布结构10还可包括填充沟槽18的填充材料20,其中,填充材料20不同于介电层12的材料。
在图1的示例中,填充材料20被示为与过孔连接部14分开。在另外的示例中,填充材料20也可与过孔连接部14相接触。此外,应注意,再分布结构10可被扩展以包括任意数量的另外的介电层、另外的过孔连接部、另外的被填充的沟槽和/或另外的导电层。在此,介电层中的一个或一个以上可布置在相邻的导电层之间。过孔连接部可延伸穿过介电层中的一个或一个以上,以便电耦接布置在不同层面上的导电层。
在包括再分布结构的电子器件的操作期间,电流和电信号可流过再分布结构的过孔连接部和导电层。在此,导电层的厚度可能必须在层的期望的低电阻与层的期望的低制造成本和高布线密度之间折中考虑,所述低电阻可通过选择增大的层厚度来实现,所述低制造成本和高布线密度可通过选择减小的层厚度来实现。通常,导电层的电阻可限制应用领域和待实施的应用的效率。在许多应用中,可能需要增大导电层的厚度,这可能导致较差的设计规则、即更宽的层和受限的逻辑布线能力,或者导致因更复杂的制造工艺(例如图案电镀)或者甚至需要额外的布线层而导致的更高成本。
根据本公开的再分布结构尤其可包括结合图1所描述的被填充的沟槽20。如果填充沟槽18的填充材料20是导电的,则被填充的沟槽20可表示附加的导电迹线,并且可充当沿着再分布结构10的导电层16延伸的电流路径的增补。由于施加被填充的沟槽20,因此可无需增大导电层16的厚度,以便避免上述技术问题。特别地,根据本公开的再分布结构可避免位于芯片载体100的可能需要高布线密度的逻辑区域中的导电层16的厚度增加。包括被填充的沟槽20的根据本公开的再分布结构由此可优于不包括所述被填充的沟槽的常规的再分布结构。
此外,被填充的沟槽20可使得热能可沿着期望的路线传递。换句话说,被填充的沟槽20也可充当热管。通过强制热传递能力沿着被填充的沟槽20的方向,热能可从热源、例如功率半导体芯片传递至散热器和热传感器中的至少一个。填充沟槽18的导热材料的施加可由此降低热阻,并且可用于避免芯片载体100中或芯片载体100上的热敏感区域处、例如芯片载体100上的可能安装有传感器或高密度半导体芯片的位置处的温度升高。例如,提供增大的热容的被填充的沟槽20可应用于功率半导体应用中。为了热能的经由被填充的沟槽20的期望的路线,填充材料可以是导电且导热的,但也可仅提供导热性能。
图2示意性地示出了根据本公开的半导体器件200的侧剖视图。半导体器件200以概括的方式示出,以便定性地说明本公开的多个方面。半导体器件200可包括为了简单起见而未示出的另外的部件。例如,半导体器件200还可包括根据本公开的其他器件的一个或一个以上的部件。
半导体器件200可包括材料层22和嵌入材料层22中的半导体芯片24。半导体器件200还可包括再分布结构10,所述再分布结构10可类似于图1的再分布结构10,从而提供类似的技术特征。再分布结构10可电耦接至半导体芯片24。再分布结构10可包括沿水平方向延伸的介电层12。再分布结构10还可包括竖直地延伸穿过介电层12的可选的导电的过孔连接部14。再分布结构10还可包括布置在介电层12之上并沿水平方向延伸的导电层16。导电层16可电耦接至可选的过孔连接部14。再分布结构10还可包括布置在介电层12中并沿水平方向延伸的沟槽18。填充材料20可填充沟槽18,其中,填充材料20不同于介电层12的材料。
图3包括图3A至图3F,示意性地示出了制造根据本公开的再分布结构300的方法的侧剖视图,所述再分布结构300的剖视图如图3F所示。制造好的再分布结构300可类似于结合图1和图2描述的再分布结构。
在图3A中,可形成介电层12,其中,介电层12可沿水平方向延伸。特别地,形成的介电层12的上表面和下表面可以是大致平坦的。在一示例中,介电层12可沉积在半导体芯片和/或材料层之上,例如如图2所示。在另一示例中,介电层12可沉积在之后可被去除的临时载体的表面上。介电层12可以以各种方式制造。例如,介电层12可由气相或溶液沉积,或者可层合至表面上。附加地或替代地,薄膜技术可用于施加介电层12。介电层12可由聚合物、例如聚降冰片烯、聚酰亚胺、聚对二甲苯、光阻材料、酰亚胺、环氧树脂、热固性塑料聚合物、硅树脂制造,或由无机陶瓷类材料、例如硅碳化合物、氮化硅、氧化硅制造。
介电层12的(竖直)厚度可与待制造的再分布结构的应用有关。通常,厚度可在约2微米至约250微米的范围内。对于再分布结构提供逻辑信号的路线选择的情况,厚度可在约2微米至约50微米的范围内。对于再分布结构提供功率电流的再分布的情况,厚度可在约20微米至约250微米的范围内。特别地,介电层12的厚度可以是基本恒定的。
在图3B中,过孔(或微过孔)26可以可选地形成在介电层12中,其中,可选的过孔26可竖直地延伸穿过介电层12。形成过孔26可包括下述中的至少一个:钻孔、尤其是激光钻孔;蚀刻、尤其是等离子蚀刻;光刻;步冲;布线。
在图3C中,沟槽18可形成在介电层12中,其中,沟槽18可沿水平方向延伸。特别地,过孔26和沟槽18可利用类似的成形工艺形成。在一示例中,过孔26和沟槽18可相继地形成。在另一示例中,过孔26和沟槽18可同时形成。在图3C的示例中,沟槽18可延伸穿过介电层12的整个厚度。在另外的示例中,沟槽18可仅部分地延伸至介电层12中,使得可减小介电层12的厚度。沟槽18的深度可以是恒定的,或者可在沟槽18的尺度上变化。
在图3D中,可选的过孔26可以可选地填充有导电材料28,使得填充的过孔26可构造成能够沿竖直方向传导电流。导电材料28可包括下述中的至少一种:铜、铝、镍、钯、钛、钛钨、银、锡、金、钼、钒和所指定的金属的合金。
在图3E中,沟槽18可填充有填充材料20,所述填充材料20尤其可不同于介电层12的材料。沟槽18可以以各种方式填充。特殊地,填充沟槽18可包括下述中的至少一种:水电镀(galvanic plating);直接电镀;保形镀;超保形镀;平版印刷结构化;双镶嵌工艺;填充和固化焊膏、烧结膏、导电胶及其组合中的至少一种。应注意,填充过孔26(参见图3D)可基于类似的工艺,并且可同时执行。
在一示例中,填充材料20可以是导电的,由此可构造成能够提供沿水平方向的电流传导。合适的导电的填充材料例如可包括碳、铜、金、镍、锡、铝、其合金等中的至少一种。在另一示例中,填充材料20可以是导热的,由此可构造成能够提供沿水平方向的热能传导。合适的导热填充材料可包括上文所述的导电材料中的一种和/或碳、氮化硅、氮化硼、氧化铝、氮化铝等中的至少一种。
在图3F中,导电层16可形成在介电层12之上,其中,导电层16可沿水平方向延伸并且可电耦接至可选的被填充的过孔28。形成导电层16和/或填充过孔26(见图3D)和/或填充沟槽18(见图3E)可基于类似的工艺。特别地,导电层16可以是沉积的金属化层,其中,金属化层的上表面和下表面可以是大致平坦的。导电层16可被结构化并且可具有导体线路(或导体迹线)的形状,但是也可以是根据所考虑的应用覆盖具有任意形状的区域的层的形式。任何合适的金属,例如铝、镍、钯、钛、钛钨、银、锡、金、钼、钒和铜中的至少一种或相关金属合金可用于制造金属化层16。
导电层16的(竖直)厚度可与待制造的再分布结构的应用有关。通常,厚度可在约5微米至约50微米的范围内。对于再分布结构提供逻辑信号的路线选择的情况,厚度可在约5微米至约10微米的范围内。对于再分布结构提供功率电流的再分布的情况,厚度可在约20微米至约50微米的范围内。然而,应当注意,再分布结构也可应用于其中可能出现高达200A或甚至更大的电流峰值的应用中。在此,导电层16的厚度可能需要大约200微米至甚至约2000微米的值。特别地,导电层16的厚度可以是基本恒定的。
在图3的示例中,填充过孔26(参见图3D)、填充沟槽18(参见图3E)和形成导电层16(参见图3F)的行为以单独的图示出。上文已经说明了用于执行这些行为的示例性工艺。应当注意,这三个行为中的至少两个可利用类似的工艺执行。此外,可相继地或同时地执行至少所述行为中的至少两个。另外,填充过孔26的材料28、填充沟槽18的材料20和导电层16的材料可类似。
图3的方法示出了示例性和非限制性再分布层300的制造。所述方法以概括的方式示出,以便定性地说明本公开的多个方面。应当理解,图3的方法可扩展到包括任意数量的多个介电层、多个过孔连接部、多个被填充的沟槽和/或多个导电层的再分布层的制造。此外,图3的方法可通过附加的行为和特征来扩展。例如,图3A中的介电层12可设有位于介电层12的主表面中的一个或两个上的附加的导体箔。进而也可在所述导体箔中形成并填充过孔26和沟槽18。在填充过程中,可加厚先前提供的导体箔。
图4示意性地示出了再分布结构400的细节的透视图。再分布层400可包括布置在第一(上)层面上的第一导电层16A和布置在第二(下)层面上的第二导电层16B。导电层16A、16B可大致彼此平行并且可沿水平方向延伸。再分布结构400还可包括构造成能够电耦接导电层16A、16B的大致竖直的导电的第一多个过孔连接部14A和大致竖直的导电的第二多个过孔连接部14B。过孔连接部的数量可以是任意的。再分布结构400还可包括布置在导电层16A、16B之间的介电层,所述介电层出于展示的原因未在图4的示例中示出。
在图4的示例中,相应的多个过孔连接部14A、14B可以以并排等距的方式布置在虚构的直线上。在另外的示例中,过孔连接部14A、14B之间的距离可不相同,并且过孔连接部14A、14B的位置可偏离虚构的直线。此外,在图4的示例中,导电层16A、16B可以是覆盖延伸的区域的平坦的层。在另一示例中,导电层16A、16B中的每一个可包括多个导电线路(或导电迹线),每个导电线路从第一多个过孔连接部14A中的一个过孔连接部延伸至第二多个过孔连接部14B中的一个过孔连接部。
在包括再分布结构400的器件的操作期间,电流可沿水平方向在导电层16A、16B中流动。在图4的示例中,这种电流“I”的示例性方向由箭头指示。由于导电层16A、16B可通过过孔连接部14A、14B电耦接,层16A、16B可构造成能够沿相同的水平方向传导电流。通过使层16A、16B电耦接,该布置的载流容量由此可大致加倍。电耦接导电层16A、16B的过孔连接部14A、14B的合适的数量可与所产生的电流的大小有关。通常,较高的电流可能需要更多数量的过孔连接部并需要导电层16A、16B具有增大的表面积。例如,与功率应用电流的分布相比,逻辑信号的路线选择可能需要较少数量的过孔连接部和层16A、16B的减小的表面积。在另外的示例中,可根据所产生的电流的大小来选择过孔连接部的尺寸和形式。
图5示意性地示出了根据本公开的再分布结构500的细节的透视图。再分布结构500可看作是图1至图3所示的再分布结构的更详细的实施方案。
再分布结构500可包括导电层16A、16B和布置在中间的介电层(未示出)。再分布结构500还可包括构造成能够电耦接导电层16A、16B的大致竖直的导电的第一多个过孔连接部14A和大致竖直的导电的第二多个过孔连接部14B。提到的部件可类似于图4的再分布结构400的对应部件。与图4相比,图5的再分布结构500可附加地包括布置在介电层中的多个被填充的沟槽20。被填充的沟槽20中的每一个可在不同的多个过孔连接部14A、14B中的两个过孔连接部之间延伸。在图5的示例中,被填充的沟槽20的厚度被示为小于过孔连接部14A、14B的粗度。在另外的示例中,被填充的沟槽20的厚度可等于或可大于过孔连接部14A、14B的粗度。应注意,在另外的示例中,再分布结构500可不必包括过孔连接部14A、14B,使得在相应的图中可省略位于被填充的沟槽20的端部处的过孔连接部14A、14B。
在图5的示例中,被填充的沟槽20可完全延伸穿过介电层(未示出)并且可与导电层16A、16B中的每一个相接触。在另一示例中,被填充的沟槽20可不完全延伸穿过介电层,由此可仅与导电层16A、16B中的一个相接触。在又一示例中,被填充的沟槽20可与导电层16A、16B中的至少一个相接触,但是可与过孔连接部14A、14B分开。
图6示意性地示出电子器件600的侧剖视图。器件600可对应于BGA器件,并且可包括根据本公开的芯片载体30。半导体芯片32可安装在芯片载体30的上主表面之上,并且可经由焊线34电耦接至位于芯片载体30的上主表面上的电触点。半导体芯片32可嵌入封装材料38中,所述封装材料38可包括层合材料、环氧树脂、填充式环氧树脂、玻璃纤维填充式环氧树脂、酰亚胺、热塑性塑料、热固性塑料聚合物、共混聚合物中的至少一种。器件600还可包括外接触元件36、例如焊料沉积物,所述外接触元件36可施加至位于芯片载体30的下主表面上的电触点。
芯片载体30可包括再分布结构,所述再分布结构可构造成能够将半导体芯片32电耦接至外接触元件36。再分布结构可包括第一导电层16A、第二导电层16B、布置在中间的介电层12和电耦接导电层16A、16B的过孔连接部14。半导体芯片32可例如通过布置在中间的另外的介电层(未示出)与第一导电层16A电绝缘。
再分布结构可包括布置在介电层12中的一个或多个被填充的沟槽20A、20B。在图6的示例中,第一被填充的沟槽20A可沿水平的x方向延伸,并且可经由第二导电层16B电耦接至外接触元件36中的多个。也就是说,在图6的示例中,外接触元件36中的多个可处于相同的电位。第二被填充的沟槽20B可类似于第一被填充的沟槽20A,但是可沿水平的z方向延伸。应当理解,器件600的再分布结构可包括任意数量的另外的导电层、介电层、过孔连接部和被填充的沟槽。
图7示意性地示出了电子器具700的侧剖视图。器件700可根据倒装芯片技术制造。器件700可至少部分地类似于图6的器件600,并且可具有相似的部件。半导体芯片32可经由接触元件40(例如焊料凸起、柱凸起、铜柱)电耦接至芯片载体30的上主表面,所述接触元件40可布置在半导体芯片32的下主表面上。类似于图6,芯片载体30可包括再分布结构,所述再分布结构包括被填充的沟槽20,并且构造成能够将半导体芯片32电耦接至布置在芯片载体30的下表面上的外接触元件36。
图8示意性地示出了根据本公开的半导体器件800的侧剖视图。半导体器件800以概括的方式示出,以便定性地说明本公开的多个方面。半导体器件800可包括为了简单起见而未示出的另外的部件。
半导体器件800可包括第一功率晶体管42、第二功率晶体管44和逻辑半导体芯片46。第一功率晶体管42可具有垂直结构,即,第一功率晶体管42可制造成使得电流可大致沿垂直于半导体芯片的主表面的方向流动。栅电极和源电极可布置在第一功率晶体管42的上主表面上,漏电极可布置在第一功率晶体管42的相反的下主表面上。第二功率晶体管44可类似于第一功率晶体管42,但上下颠倒地布置。逻辑半导体芯片46可包括布置在逻辑半导体芯片46的下主表面上的多个接触电极。
半导体芯片42、44、46可嵌入材料层22中,材料层22可包括层合材料、环氧树脂、填充式环氧树脂、玻璃纤维填充式环氧树脂、酰亚胺、热塑性塑料、热固性塑料聚合物、共混聚合物中的至少一种。此外,如图8的示例所示,半导体芯片42、44、46可通过多个导电层16和多个过孔连接部14电互连。导电层16可通过材料层22的多个部分而彼此分开。逻辑半导体芯片46的上主表面、第一功率晶体管42的下主表面和第二功率晶体管44的上主表面可相应地附接至电绝缘层48A、48B、48C。功率晶体管42、44的漏极触点相应地可经由延伸穿过电绝缘层48B、48C的导电材料而可电接入。
半导体芯片42、44、46可电互连以形成半桥电路。在此,第一功率晶体管42和第二功率晶体管44可相应地对应于半桥电路的低压侧开关和高压侧开关。逻辑半导体芯片46可构造成能够控制和/或驱动第一功率晶体管42和第二功率晶体管44中的至少一个。特别地,逻辑半导体芯片46可包括驱动电路,所述驱动电路构造成能够驱动半桥电路的高压侧开关和低压侧开关。半导体器件800还可包括布置在半导体器件800的下主表面上并提供至半导体芯片42、44、46的电接入途径的外接触焊盘50。特别地,外接触焊盘50可用于将半导体器件800安装和电耦接至PCB(未示出)。
半导体器件800还可包括可电耦接至半导体芯片42、44、46的再分布结构10。再分布层10可包括布置在导电层之间、例如布置在材料层22中的被填充的沟槽20A、20B。第一被填充的沟槽20A尤其可包括导热材料,所述导热材料可提供用于热传导的热连接。例如,第一被填充的沟槽20A可构造成能够支持至传感器的热传导,所述传感器可包括在逻辑半导体芯片46中。第二被填充的沟槽20B尤其可包括导电材料,所述导电材料可减小功率晶体管42与44之间的电连接的欧姆电阻。
图9示意性地示出了根据本公开的半导体器件900的侧剖视图。半导体器件900以概括的方式示出,以便定性地说明本公开的多个方面。半导体器件900可包括为了简单起见而未示出的另外的部件。
半导体器件900可包括嵌入材料层22中的第一功率晶体管42、第二功率晶体管44和逻辑半导体芯片46。这些部件可类似于图8的相似部件。半导体芯片42、44、46可安装在芯片载体、例如引线框架52的下主表面上。介电层54可布置在引线框架52的上主表面上。
半导体器件900可包括再分布结构10,所述再分布结构10可包括第一导电层16A、第二导电层16B和布置在中间的介电层12。导电层16A、16B可通过竖直的过孔连接部14电耦接。再分布结构10还可包括布置在介电层12中并电耦接至导电层16A、16B的被填充的沟槽20。被填充的沟槽20可包括导电材料,以便增大再分布结构10在水平方向上的载流容量。再分布结构10可构造成能够将半导体芯片42、44、46电耦接至第二导电层16B。第二导电层16B可暴露在半导体器件900的下主表面上,使得层16B的暴露部分可用作外接触焊盘,尤其用于将半导体器件900安装和电耦接至PCB(未示出)。
图10示意性地示出了根据本公开的半导体器件1000的侧剖视图。半导体器件1000可至少部分地类似于图9的半导体器件900,并且可包括类似的部件。与图9不同,半导体芯片42、44、46可以不安装在引线框架上,而是安装在直接铜结合(DCB:Direct Copper Bond)或直接结合铜(DBC:Direct Bond Copper)基体56上。DCB基体56可包括陶瓷芯58和布置在陶瓷芯58的主表面中的一个或两个上的铜层60。例如,陶瓷材料可包括氧化铝(Al2O3)、氮化铝(AlN)、氧化铍(BeO)等中的至少一种。
图11示意性地示出了根据本发明的半导体器件1100的侧剖视图。半导体器件1100可包括嵌入封装材料38中的半导体芯片62,所述封装材料38可类似于图6的封装材料38。特别地,封装材料38的上主表面与半导体芯片62的上主表面可大致共面。接触元件64可布置在半导体芯片62的上主表面上。接触元件64可提供至半导体芯片62的内部电子结构的电接入途径。半导体器件1100还可包括布置在半导体芯片62的上主表面之上的再分布结构10和布置在再分布结构10之上的外接触元件66、例如焊料沉积物。半导体器件1100可对应于嵌入式晶片级(eWLB)封装体或扇出型晶片级封装体(FOWLP)。在此,术语“扇出”可表示:当沿与半导体芯片62的主表面垂直的方向观察时,外接触元件66中的一个或一个以上可布置在半导体芯片62的轮廓之外。
再分布结构10可构造成能够将半导体芯片62的接触元件64电耦接至外接触元件66。再分布结构10可包括至少一个介电层12和至少一个导电层16。此外,再分布结构10可包括布置在介电层12中并电耦接至导电层16的至少一个被填充的沟槽20。被填充的沟槽20尤其可包括导电材料,由此可增大再分布结构10在水平方向上的载流容量。
图12示意性地示出了根据本公开的电子器件1200的俯视图。器件1200可包括芯片载体68。第一电子部件70、第二电子部件72、散热器74和热传感器76可布置在芯片载体68处。第一电子部件70可构造成在电子器件1200的操作期间产生热能,由此可视为热源。在这方面,在一示例中,第一电子部件70可以是功率半导体芯片。第二电子部件72可以是热敏器件,即,第二电子部件72的操作可能受到例如可由第一电子部件70产生的热量引起的高温的不利影响。
器件1200还可包括一个或多个导热线路78。导热线路78中的一个或多个可从第一电子部件70延伸至热传感器76,并从热传感器76延伸至散热器74。导热线路78可包括或可对应于填充有结合前面的示例所描述的导热材料的沟槽。在这方面,应注意,导热线路78尤其可布置在芯片载体68中,而不是布置在芯片载体68的暴露表面上。也就是说,在图12的示例中,为了展示的目的而明确地示出了导热线路78,但是导热线路78不一定在器件1200的实际俯视图中可见。
导热线路78可构造成能够将第一电子部件70热耦接至热传感器76和散热器74中的至少一个。特别地,导热线路78可布置成能够绕开第二电子部件72,使得由第一电子部件70产生的热能的路线可绕过或者远离热敏的第二电子部件74。在器件1200的操作期间,由此可减小第二电子部件72的位置处的温度。应注意,器件1200是示例性的,并且示出了由如上所述的导热线路78提供的各种技术特征。在另外的示例中,可以仅实现这些技术特征中的一个或选择的多个,而非全部。
如本说明书中所使用的,术语“连接的”、“耦接的”、“电连接的”和/或“电耦接的”不一定表示元件必须直接连接或耦接在一起。可在“连接的”、“耦接的”、“电连接的”或“电耦接的”元件之间设置中间元件。
此外,关于例如形成或定位在物体的表面“之上”的材料层而使用的词语“之上”在此可用于表示材料层可定位(例如形成、沉积等)在相关表面的“直接上方”、例如与相关表面直接接触。关于例如形成或定位在一表面之上的材料层所使用的词语“之上”在此也可用于表示材料层可定位(例如形成、沉积等)在相关表面的“间接上方”且在相关的表面与所述材料层之间布置有例如一个或一个以上的附加的层。
此外,在说明书或权利要求书中使用术语“具有”、“包含”、“含有”,“带有”或其变体,这些术语旨在以类似于术语“包括”的方式包括在内。也就是说,如本文所使用的,术语“具有”、“包含”、“含有”、“带有”、“包括”等是开放式术语,其表示所述的元件或特征的存在,但不排除还有附加元件或特征。冠词“一个”、“该”旨在包括复数和单数,除非上下文另有明确说明。
此外,词语“示例性”在本文中用于表示用作示例、实例或展示。本文“示例性”描述的任何方面或设计不一定理解为优于其他方面或设计。而是,使用词语“示例性”旨在以具体的方式呈现概念。如本申请中所使用的,术语“或”旨在表示包容性的“或”而不是排他性的“或”。也就是说,除非另有说明或者从上下文中显然可见,“X使用A或B”旨在表示任何自然包括的排列。也就是说,如果X使用A;X使用B;或者X使用A和B,则在任何前述情况下,“X使用A或B”都是满足的。此外,本申请和所附权利要求中使用的冠词“一个”通常可理解为表示“一个或一个以上”,除非另有说明或从上下文中显然可见地指向单数形式。此外,A和B中的至少一个等通常意味着A或B或者A和B两者。
本文描述了器件和用于制造器件的方法。与所描述的器件相关的解释对于相应的方法也可能是正确的,反之亦然。例如,如果描述了器件的特定部件,则用于制造器件的相应方法可包括以合适的方式提供所述部件的行为,即使这些行为未作明确描述或未在图中示出。此外,除非另有明确说明,否则本文所述的各种示例性方面的特征可彼此组合。
尽管已经就一个或一个以上的实施方式示出和描述了本公开,但至少部分地基于对本说明书和附图的阅读和理解,本领域技术人员将想到等同的改变和修改。本公开包括所有这些修改和改变,并且仅受所附权利要求的概念的限制。特别是关于由上述部件(例如元件、资源等)执行的各种功能,除非另有说明,用于描述这些部件的术语旨在对应于执行所述部件的特定功能的(例如,功能上等效的)即使结构上不等同于本公开的在本文所示的示例性实施方式中执行所述功能的所公开的结构的任何部件。此外,虽然本公开的特定特征可能仅针对多个实施方式中的一个而公开,但是,如可能对于任何给定的或特别的应用而言期望的或有利的那样,这样的特征可与其他实施方式的其他特征中的一个或一个以上组合。
Claims (22)
1.一种芯片载体,其包括再分布结构,所述再分布结构包括:
沿水平方向延伸的介电层;
布置在介电层之上并沿水平方向延伸的第一导电层;
布置在介电层中并沿水平方向延伸的沟槽;以及
填充沟槽的填充材料,其中,所述填充材料不同于介电层的材料。
2.根据权利要求1所述的芯片载体,其特征在于,所述填充材料是导电的并且电耦接至第一导电层,其中,被填充的沟槽形成导电线路。
3.根据权利要求1或2所述的芯片载体,其特征在于,填充材料包括下述中的至少一种:碳;铜;金;镍;锡;铝;碳、铜、金、镍、锡、铝的合金。
4.根据前述权利要求中任一项所述的芯片载体,其特征在于,填充材料是导热的,被填充的沟槽形成导热线路。
5.根据权利要求4所述的芯片载体,其特征在于,填充材料包括氮化硅、氮化硼、氧化铝和氮化铝中的至少一种。
6.根据前述权利要求中任一项所述的芯片载体,其特征在于,被填充的沟槽构造成能够将第一电子部件热耦接至热传感器和散热器中的至少一个。
7.根据前述权利要求中任一项所述的芯片载体,其特征在于,被填充的沟槽构造成能够使热能的传导路线绕过或远离第二电子部件。
8.根据前述权利要求中任一项所述的芯片载体,其特征在于,所述芯片载体还包括:
竖直地延伸穿过介电层的导电的过孔连接部,其中,第一导电层电耦接至所述过孔连接部。
9.根据前述权利要求中任一项所述的芯片载体,其特征在于,所述芯片载体还包括:
沿水平方向延伸并电耦接至第一导电层的第二导电层,
其中,介电层布置在第一导电层与第二导电层之间,
第一导电层和第二导电层构造成能够沿相同的水平方向传导电流。
10.根据前述权利要求中任一项所述的芯片载体,其特征在于,所述芯片载体还包括:
布置在介电层中并沿水平方向延伸的平行的多个沟槽,其中,所述多个沟槽中的每一个都填充有填充材料。
11.根据前述权利要求中任一项所述的芯片载体,其特征在于,所述芯片载体包括:
构造成能够安装半导体芯片的主表面;以及
与所述主表面相反的构造成能够安装电接触元件的相反表面,其中,芯片载体构造成能够将半导体芯片电耦接至所述电接触元件。
12.一种半导体器件,其包括:
材料层;
嵌入材料层中的半导体芯片;以及
电耦接至半导体芯片的再分布结构,其中,所述再分布结构包括:
沿水平方向延伸的介电层;
布置在介电层之上并沿水平方向延伸的导电层;
布置在介电层中并沿水平方向延伸的沟槽;以及
填充沟槽的填充材料,其中,所述填充材料不同于介电层的材料。
13.根据权利要求12所述的半导体器件,其特征在于,半导体芯片嵌入的材料层包括层合材料、环氧树脂、填充式环氧树脂、玻璃纤维填充式环氧树脂、酰亚胺、热塑性塑料、热固性塑料聚合物和共混聚合物中的至少一种。
14.根据权利要求12或13所述的半导体器件,其特征在于,填充材料是导电的并且电耦接至导电层,其中,被填充的沟槽形成导电线路。
15.根据权利要求12至14中任一项所述的半导体器件,其特征在于,填充材料是导热的,被填充的沟槽形成导热线路。
16.一种制造再分布结构的方法,所述方法包括:
形成介电层,其中,所述介电层沿水平方向延伸;
在介电层中形成沟槽,其中,所述沟槽沿水平方向延伸;
用与介电层的材料不同的填充材料填充沟槽;以及
在介电层之上形成导电层。
17.根据权利要求16所述的方法,其特征在于,所述方法还包括:
在介电层中形成过孔,其中,所述过孔竖直地延伸穿过介电层;以及
用导电材料填充过孔,其中,导电层电耦接至被填充的过孔。
18.根据权利要求16或17所述的方法,其特征在于,填充材料是导热的和导电的中的至少一种。
19.根据权利要求17或18所述的方法,其特征在于,利用相同的成形工艺形成过孔和沟槽。
20.根据权利要求17至19中任一项所述的方法,其特征在于,填充过孔、填充沟槽和形成导电层的行为中的至少两个是基于相同的工艺。
21.根据权利要求16至20中任一项所述的方法,其特征在于,形成沟槽包括激光钻孔、等离子蚀刻、光刻、步冲、布线中的至少一种。
22.根据权利要求16至21中任一项所述的方法,其特征在于,填充沟槽包括下述中的至少一种:水电镀;直接电镀;保形电镀;超保形电镀;平版印刷结构化;双镶嵌工艺;填充和固化焊膏、烧结膏、导电胶和焊膏、烧结膏、导电胶的组合中的至少一种。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102016109853.1 | 2016-05-30 | ||
DE102016109853.1A DE102016109853B4 (de) | 2016-05-30 | 2016-05-30 | Chipträger und Halbleitervorrichtung mit Umverteilungsstrukturen sowie Verfahren zur Herstellung einer Umverteilungsstruktur |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107452707A true CN107452707A (zh) | 2017-12-08 |
CN107452707B CN107452707B (zh) | 2020-12-08 |
Family
ID=60269136
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710398130.9A Active CN107452707B (zh) | 2016-05-30 | 2017-05-31 | 含热、电性能改善的再分布结构的芯片载体及半导体器件 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10366924B2 (zh) |
CN (1) | CN107452707B (zh) |
DE (1) | DE102016109853B4 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112309879A (zh) * | 2020-11-02 | 2021-02-02 | 江苏纳沛斯半导体有限公司 | 一种预埋式rdl封装成形方法 |
CN112510003A (zh) * | 2020-11-30 | 2021-03-16 | 杰华特微电子(杭州)有限公司 | 一种半导体封装结构及其制作方法 |
CN113097200A (zh) * | 2021-03-09 | 2021-07-09 | 中国电子科技集团公司第二十九研究所 | 一种倒装热源芯片及其制备方法和应用方法 |
CN113496903A (zh) * | 2020-03-20 | 2021-10-12 | 南茂科技股份有限公司 | 半导体封装结构及其制造方法 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10602039B2 (en) * | 2016-09-19 | 2020-03-24 | Microsoft Technology Licensing, Llc | Ultra-compact image sensor assembly for thin profile devices |
CN107706286B (zh) * | 2017-09-27 | 2019-10-11 | 开发晶照明(厦门)有限公司 | Led发光装置和led支架 |
WO2019160570A1 (en) * | 2018-02-15 | 2019-08-22 | Didrew Technolgy (Bvi) Limited | System and method of fabricating tim-less hermetic flat top his/emi shield package |
JP7119842B2 (ja) * | 2018-09-27 | 2022-08-17 | Tdk株式会社 | Mosトランジスタ内蔵基板及びこれを用いたスイッチング電源装置 |
DE102019115369A1 (de) * | 2019-06-06 | 2020-12-10 | Infineon Technologies Ag | Verfahren zur herstellung eines halbleiter-flip-chip-package |
EP3761357A1 (en) * | 2019-07-04 | 2021-01-06 | Infineon Technologies Austria AG | Semiconductor device |
CN116207074A (zh) | 2019-07-29 | 2023-06-02 | 群创光电股份有限公司 | 电子装置 |
EP3907760A1 (en) * | 2020-05-08 | 2021-11-10 | Infineon Technologies Austria AG | Semiconductor module |
DE102020119611A1 (de) * | 2020-07-24 | 2022-01-27 | Infineon Technologies Ag | Schaltungsanordnung und verfahren zum bilden einer schaltungsanordnung |
DE102020119849A1 (de) * | 2020-07-28 | 2022-02-03 | Infineon Technologies Ag | Halbleitergehäuse und verfahren zur herstellung eines halbleitergehäuses |
EP3975225A1 (en) | 2020-09-24 | 2022-03-30 | Infineon Technologies Austria AG | Semiconductor module |
EP3982404A1 (en) * | 2020-10-07 | 2022-04-13 | Infineon Technologies Austria AG | Semiconductor module |
CN220509968U (zh) * | 2020-11-18 | 2024-02-20 | 日立能源有限公司 | 半导体模块 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61231745A (ja) * | 1985-04-08 | 1986-10-16 | Hitachi Ltd | 半導体装置 |
US20060017174A1 (en) * | 2004-06-22 | 2006-01-26 | Ralf Otremba | Semiconductor device |
US20100078783A1 (en) * | 2008-09-30 | 2010-04-01 | Infineon Technologies Ag | Device including two mounting surfaces |
US20100320601A1 (en) * | 2009-06-17 | 2010-12-23 | Reza Argenty Pagaila | Integrated circuit packaging system with through via die having pedestal and recess and method of manufacture thereof |
CN102789981A (zh) * | 2012-07-18 | 2012-11-21 | 启东吉莱电子有限公司 | 一种可控硅的生产工艺 |
CN103378266A (zh) * | 2012-04-24 | 2013-10-30 | 新世纪光电股份有限公司 | 基板结构 |
CN104347577A (zh) * | 2013-08-08 | 2015-02-11 | 英飞凌科技股份有限公司 | 重新分布板、电子组件和模块 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3969192B2 (ja) * | 2002-05-30 | 2007-09-05 | 株式会社デンソー | 多層配線基板の製造方法 |
DE102005045056B4 (de) | 2005-09-21 | 2007-06-21 | Infineon Technologies Ag | Integrierte Schaltungsanordnung mit mehreren Leitstrukturlagen und Kondensator |
KR100772109B1 (ko) * | 2006-06-30 | 2007-11-01 | 주식회사 하이닉스반도체 | 반도체 소자의 소자분리막 형성방법 |
DE102007039536B4 (de) | 2007-08-21 | 2009-08-13 | W.C. Heraeus Gmbh | Mehrfach-Bonddrahtverbund und simultanes Bonden |
US8507320B2 (en) * | 2008-03-18 | 2013-08-13 | Infineon Technologies Ag | Electronic device including a carrier and a semiconductor chip attached to the carrier and manufacturing thereof |
DE102008024480A1 (de) * | 2008-05-21 | 2009-12-03 | Epcos Ag | Elektrische Bauelementanordnung |
US8003515B2 (en) | 2009-09-18 | 2011-08-23 | Infineon Technologies Ag | Device and manufacturing method |
US8120158B2 (en) * | 2009-11-10 | 2012-02-21 | Infineon Technologies Ag | Laminate electronic device |
US9190389B2 (en) | 2013-07-26 | 2015-11-17 | Infineon Technologies Ag | Chip package with passives |
-
2016
- 2016-05-30 DE DE102016109853.1A patent/DE102016109853B4/de active Active
-
2017
- 2017-05-09 US US15/590,520 patent/US10366924B2/en active Active
- 2017-05-31 CN CN201710398130.9A patent/CN107452707B/zh active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61231745A (ja) * | 1985-04-08 | 1986-10-16 | Hitachi Ltd | 半導体装置 |
US20060017174A1 (en) * | 2004-06-22 | 2006-01-26 | Ralf Otremba | Semiconductor device |
US20100078783A1 (en) * | 2008-09-30 | 2010-04-01 | Infineon Technologies Ag | Device including two mounting surfaces |
US20100320601A1 (en) * | 2009-06-17 | 2010-12-23 | Reza Argenty Pagaila | Integrated circuit packaging system with through via die having pedestal and recess and method of manufacture thereof |
CN103378266A (zh) * | 2012-04-24 | 2013-10-30 | 新世纪光电股份有限公司 | 基板结构 |
CN102789981A (zh) * | 2012-07-18 | 2012-11-21 | 启东吉莱电子有限公司 | 一种可控硅的生产工艺 |
CN104347577A (zh) * | 2013-08-08 | 2015-02-11 | 英飞凌科技股份有限公司 | 重新分布板、电子组件和模块 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113496903A (zh) * | 2020-03-20 | 2021-10-12 | 南茂科技股份有限公司 | 半导体封装结构及其制造方法 |
CN112309879A (zh) * | 2020-11-02 | 2021-02-02 | 江苏纳沛斯半导体有限公司 | 一种预埋式rdl封装成形方法 |
CN112510003A (zh) * | 2020-11-30 | 2021-03-16 | 杰华特微电子(杭州)有限公司 | 一种半导体封装结构及其制作方法 |
CN112510003B (zh) * | 2020-11-30 | 2023-07-18 | 杰华特微电子股份有限公司 | 一种半导体封装结构及其制作方法 |
CN113097200A (zh) * | 2021-03-09 | 2021-07-09 | 中国电子科技集团公司第二十九研究所 | 一种倒装热源芯片及其制备方法和应用方法 |
Also Published As
Publication number | Publication date |
---|---|
US10366924B2 (en) | 2019-07-30 |
CN107452707B (zh) | 2020-12-08 |
US20170345714A1 (en) | 2017-11-30 |
DE102016109853B4 (de) | 2021-08-12 |
DE102016109853A1 (de) | 2017-11-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN107452707A (zh) | 含热、电性能改善的再分布结构的芯片载体及半导体器件 | |
CN103782381B (zh) | 包括在衬底上的管芯以及在管芯上具有开窗的散热器的电子组件 | |
US11791256B2 (en) | Package substrate and method of fabricating the same | |
EP3355349B1 (en) | Efficient heat removal from component carrier with embedded diode | |
CN104064551B (zh) | 一种芯片堆叠封装结构和电子设备 | |
CN104716109B (zh) | 具有降低热串扰的热管理部件的封装件及其形成方法 | |
CN104377172B (zh) | 具有嵌入式无源部件的芯片封装件 | |
KR101277429B1 (ko) | 스택 다이 bga 또는 lga 컴포넌트 어셈블리 | |
TWI431759B (zh) | 可堆疊式功率mosfet、功率mosfet堆疊及其製備方法 | |
US9064869B2 (en) | Semiconductor module and a method for fabrication thereof by extended embedding technologies | |
CN104051376A (zh) | 功率覆盖结构及其制作方法 | |
CN104051377A (zh) | 功率覆盖结构及其制作方法 | |
CN103811356A (zh) | 将cpu/gpu/逻辑芯片嵌入堆叠式封装结构的衬底的方法 | |
CN104051395A (zh) | 芯片堆叠封装及其方法 | |
US9397060B2 (en) | Package on package structure | |
CN105637633A (zh) | 具有预形成过孔的嵌入式封装 | |
CN103378017A (zh) | 高密度3d封装 | |
EP1155448A1 (en) | Leadless chip carrier design and structure | |
CN103000619A (zh) | 具有低的互连寄生的有高功率芯片和低功率芯片的*** | |
US20190393196A1 (en) | Vertically stacked multichip modules | |
CN103915405B (zh) | 半导体器件和制造半导体器件的方法 | |
CN103811436A (zh) | 改进堆叠式封装结构中的逻辑芯片的热性能 | |
CN107689357A (zh) | 芯片附接方法和基于这种方法制造的半导体装置 | |
US20190333850A1 (en) | Wiring board having bridging element straddling over interfaces | |
CN104051363A (zh) | 芯片封装和用于制造该芯片封装的方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |