CN107393894A - 整合扇出型封装 - Google Patents

整合扇出型封装 Download PDF

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Publication number
CN107393894A
CN107393894A CN201610630898.XA CN201610630898A CN107393894A CN 107393894 A CN107393894 A CN 107393894A CN 201610630898 A CN201610630898 A CN 201610630898A CN 107393894 A CN107393894 A CN 107393894A
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CN
China
Prior art keywords
conductive
hole
integrated circuit
layer
line structure
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Pending
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CN201610630898.XA
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English (en)
Inventor
邱铭彦
张兢夫
黄信杰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN107393894A publication Critical patent/CN107393894A/zh
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Abstract

本发明实施例提供一种整合扇出型封装，其整合扇出型封装，包括集成电路、绝缘包封体、多个导电通孔以及重布线路结构。集成电路包括多个导电端子。绝缘包封体包覆集成电路的侧壁。导电通孔贯穿绝缘包封体。重布线路结构被配置于集成电路、导电通孔以及绝缘包封体上。重布线路结构电连接导电端子以及导电通孔。导电端子的多个第一接触表面以及导电通孔的多个第二接触表面与重布线路结构接触，且第一接触表面以及第二接触表面的粗糙度介于100埃到500埃之间。本发明实施例的制造成本低，具有好的可靠度以及良率。

Description

整合扇出型封装
技术领域
本发明实施例涉及一种半导体结构，尤其涉及一种整合扇出型封装。
背景技术
由于不同电子组件(例如是晶体管、二极管、电阻、电容等)的积体密度持续地增进，半导体工业经历了快速成长。大部分而言，积体密度的增进是来自于最小特征尺寸(feature size)上不断地缩减，这允许更多的较小组件整合到一给定区域内。较小的电子组件会需要面积比以往的封装更小的较小封装。半导体组件的其中一部分较小型式的封装包括有四面扁平封装(quad flat packages，QFPs)、接脚栅格数组(pin grid array，PGA)封装、球栅数组(ball grid array，BGA)封装等等。
目前，整合扇出型封装由于其密实度(compactness)而趋于热门。在整合扇出型封装中，形成在封装胶体上的重布线路结构的可靠度是集成电路封装过程中重要的课题。
发明内容
本发明实施例提供一种整合扇出型封装及其制造方法。
本发明实施例提供一种整合扇出型封装，其包括集成电路、绝缘包封体、多个导电通孔以及重布线路结构。集成电路包括多个导电端子。绝缘包封体包覆所述集成电路的侧壁。导电通孔贯穿绝缘包封体。重布线路结构被配置于集成电路、导电通孔以及绝缘包封体上。重布线路结构电连接导电端子以及导电通孔。导电端子的多个第一接触表面以及导电通孔的多个第二接触表面与重布线路结构接触，且第一接触表面以及第二接触表面的粗糙度介于100埃到500埃之间。
本发明实施例提供一种形成整合扇出型封装的方法，其包括下列步骤。提供多个导电通孔以及具有多个导电端子的集成电路。导电通孔、导电端子以及集成电路的多个侧壁被绝缘材料所包覆。对绝缘材料进行机械研磨直到导电端子的多个第一接触表面以及导电通孔的多个第二接触表面被暴露出来，以形成绝缘包封体。在集成电路、导电通孔以及绝缘包封体的第一表面上形成重布线路结构。重布线路结构电连接导电端子以及导电通孔。
本发明实施例提供一种形成整合扇出型封装的方法，其包括下列步骤。提供其上设置有剥离层以及介电层的载板，其中剥离层位于载板以及介电层之间。提供集成电路以及多个在介电层上的导电通孔于介电层上，其中集成电路包括多个导电端子。导电通孔、导电端子以及集成电路的多个侧壁被绝缘材料所包覆。对绝缘材料进行机械研磨直到导电端子的多个第一接触表面以及导电通孔的多个第二接触表面被暴露出来，以形成绝缘包封体。在集成电路、导电通孔以及绝缘包封体的第一表面上形成重布线路结构，其中重布线路结构电连接导电端子以及导电通孔。载板被从介电层上剥离下来。
在前述的实施例中，整合扇出型封装的制造成本低。此外，整合扇出型封装具有好的可靠度以及良率。
为让本发明实施例的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1至图11为依照一些实施例所显示的一种形成整合扇出型封装的工艺流程；
图12为依照一些实施例所显示的一种堆栈式封装(package-on-package,POP)结构的剖面图。
附图标记：
A1：宽度
A2：宽度
B1：宽度
B2：宽度
C：载板
C1：宽度差
C2：宽度差
DB：剥离层
DI：介电层
O：接触开口
S1：第一表面
S2：第二表面
TV：导电通孔
100：芯片
100’：薄化芯片
110：半导体衬底
110a：半导体衬底
110’：半导体衬底
120：导电垫
130：钝化层
130a：钝化层
132：接触开口
140：后钝化层
140a：后钝化层
142：接触开口
150：导电柱或导电孔
160：保护层
160a：保护层
160a’：保护层
200：集成电路
210：绝缘材料
210’：绝缘包封体
220：重布线路结构
222：内介电层
224：重布线导电层
224a：球底金属层图案
224b：连接垫
230：导电球
240：被动组件
250：导电球
300：封装
具体实施方式
以下发明内容提供用于实施所提供的目标的不同特征的许多不同实施例或实例。以下所描述的构件及设置的具体实例是为了以简化的方式传达本发明实施例为目的。当然，这些仅仅为实例而非用以限制。举例来说，于以下描述中，在第一特征上方或在第一特征上形成第二特征可包括第二特征与第一特征形成为直接接触的实施例，且亦可包括第二特征与第一特征之间可形成有额外特征使得第二特征与第一特征可不直接接触的实施例。此外，本发明实施例在各种实例中可使用相同的组件符号和/或字母来指代相同或类似的部件。组件符号的重复使用是为了简单及清楚起见，且并不表示所欲讨论的各个实施例和/或设置本身之间的关系。
另外，为了易于描述附图中所绘示的一个构件或特征与另一组件或特征的关系，本文中可使用例如“在...下”、“在...下方”、“下部”、“在…上”、“在…上方”、“上部”及类似术语的空间相对术语。除了附图中所显示的定向之外，所述空间相对术语意欲涵盖组件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向)，而本文所用的空间相对术语相应地作出解释。
图1至图11为依照一些实施例所显示的一种形成整合扇出型封装的工艺流程，而图12为依照一些实施例所显示的一种堆栈式封装结构的剖面图。
参照图1，提供一芯片100包括数组排列的多个晶粒(dies)或集成电路200。在对芯片100进行芯片切割工艺前，芯片100中的集成电路200彼此相连。在一些实施例中，芯片100包括半导体衬底110、形成于半导体衬底110上的多个导电垫120以及钝化层130。钝化层130形成于半导体衬底110上以部分覆盖导电垫120，并且钝化层130包括多个接触开口132。换言之，在衬底110上的导电垫120被钝化层130的接触开口132所部分暴露。举例来说，半导体衬底110可以是其中形成有主动组件(例如晶体管等)以及被动组件(例如电阻、电容器、电感器等)的硅衬底；导电垫120可以是铝垫、铜垫或其他合适的金属垫；且钝化层130可以是氧化硅层、氮化硅层、氮氧化硅层或由其他合适的介电材料所形成的介电层。
如图1所示，在一些实施例中，芯片100可还包括形成于钝化层130上的后钝化层(post passivation)140。后钝化层140覆盖钝化层130并具有多个接触开口142。被钝化层130的接触开口132所暴露的导电垫120被后钝化层140所部分所覆盖。换言之，导电垫120被后钝化层140的接触开口142所部分暴露。举例来说，后钝化层140可以是聚酰亚胺(polyimide,PI)层、聚苯二唑(polybenzoxazole,PBO)层、或由其他合适的聚合物所形成的介电层。
参照图2，形成多个导电柱(conductive pillars)或导电孔(conductive vias)150于导电垫120上。在一些实施例中，导电柱或导电孔150是藉由电镀方式形成在导电垫120上。举例来说，首先，籽晶层被溅镀于被接触开口142所暴露出的后钝化层140以及导电垫120上；以光刻(photolithography)方式于籽晶层上形成用以暴露出导电垫120的图案化光刻胶层(未显示)；接着，将已形成有图案化光刻胶层的芯片100浸入电镀溶液中，以使导电柱或导电孔150藉由电镀的方式形成于对应导电垫120的籽晶层上。在完成导电柱或导电孔150的电镀之后，剥除图案化光刻胶层。之后，以导电柱或导电孔150作为硬掩膜(hardmask)，将部分未被导电柱或导电孔150所覆盖的籽晶层移除，直到后钝化层140被暴露。籽晶层例如是被蚀刻而移除。
在一些实施例中，导电柱或导电孔150为铜柱(copper pillars)或铜通孔(coppervias)。
参照图3，在形成导电柱或导电孔150之后，在后钝化层140上形成保护层160以覆盖导电柱或导电孔150。在一些实施例中，保护层160可以是聚苯二唑层、聚酰亚胺层或其他合适的聚合物。在另一些实施例中，保护层160可以是由无机材料所形成。
参照图4，在保护层160形成后，对芯片100的后表面进行背面研磨工艺。在进行背面研磨工艺时，半导体衬底110被研磨而形成具有半导体衬底110’的薄化芯片100’。
参照图5，在进行背面研磨工艺后，对薄化芯片100’进行芯片切割工艺以使芯片100中的集成电路200彼此分离。如图5所示，经过切割后的各个集成电路200分别包括半导体衬底110a、形成在半导体衬底110a上的导电垫120、钝化层130a、后钝化层140a、导电柱或导电孔150以及保护层160a。导电垫120以及导电孔150的电连接可以被视为是集成电路200的导电端子。半导体衬底110a、钝化层130a、后钝化层140a以及保护层160a的材料与半导体衬底100、钝化层130、后钝化层140以及保护层160的材料相似。因此，此处省略了关于半导体衬底110a、钝化层130a、后钝化层140a以及保护层160a的详细描述。
如图4以及图5所示，在进行背面研磨以及芯片切割工艺个过程中，保护层160以及160a可保护集成电路200的导电端子(例如导电垫120以及导电孔150)。此外，集成电路200的导电垫120以及导电孔150可被保护而免于被接下来进行的工艺损害，例如集成电路200的转移工艺(pick-up and placing process)、模制工艺(molding process)等。
参照图6，在集成电路200被从薄化芯片100’单体化之后，提供具有剥离层DB及介电层DI形成于其上的载板C，其中剥离层DB位于载板C以及介电层DI之间。在一些实施例中，载板C例如是玻璃衬底，剥离层DB例如是形成于玻璃衬底上的光热转换(light-to-heatconversion,LTHC)释放层，且介电层DI例如为形成于剥离层DB上的聚苯二唑层。
在提供具有剥离层DB及介电层DI形成于其上的载板C之后，于介电层DI上形成多个导电通孔TV。在一些实施例中，多个导电通孔TV是以光刻、电镀以及光刻胶移除工艺所形成。举例来说，导电通孔TV包括铜柱。
如图6所示，在一些实施例中，可将具有导电端子(例如导电垫120以及导电孔150)以及保护层160a形成于其上的一个集成电路200转移到介电层DI上。集成电路200藉由晶粒附着膜、黏附膏等附着或黏附在介电层DI上。在另一些实施例中，可将多个集成电路200转移到介电层DI上，其中被转移而设置于介电层DI上的集成电路200可排列成数组。当被设置于介电层DI上的集成电路200被排列成数组时，导电通孔TV可被分成多个群组。集成电路200的数目对应于导电通孔TV的群组数目。
如图6所示，保护层160a的顶表面例如是低于导电通孔TV的顶表面，且保护层160a的顶表面例如是高于导电柱或导电孔150的顶表面。然而，本发明实施例并不仅限于此。在另一些实施例中，保护层160a的顶表面可以实质上对齐导电通孔TV的顶表面，且保护层160a的顶表面可高于导电柱或导电孔150的顶表面。
如图6所示，一个或多个集成电路200可在导电通孔TV形成之后才被转移到介电层DI上。然而，本发明实施例并不仅限于此。在另一些实施例中，一个或多个集成电路200可在导电通孔TV形成之前被转移到介电层DI上。
参照图7，于介电层DI上形成绝缘材料210以覆盖集成电路200以及导电通孔TV。在一些实施例中，绝缘材料210是由模制工艺所形成的封装胶体。集成电路200的导电柱或导电孔150以及保护层160a被绝缘材料210所覆盖。换言之，集成电路200的导电柱或导电孔150以及保护层160a并不会被显露出来，且被绝缘材料210所保护。在一些实施例中，绝缘材料210包括环氧化合物或其他合适的树脂。
参照图8，接着，对绝缘材料210进行机械研磨直到导电柱或导电孔150(例如是导电端子)的第一接触表面(例如是顶表面)、导电通孔TV的第二接触表面(例如是顶表面)以及保护层160a的顶表面被暴露出来。在绝缘材料210被机械研磨之后，绝缘包封体210’会形成于介电层DI上，且导电孔150的第一接触表面以及导电通孔TV的第二接触表面的粗糙度(Ra,平均粗糙度)介于100埃到500埃之间。在一些实施例中，导电孔150的第一接触表面以及导电通孔TV的第二接触表面的粗糙度可介于250埃到400埃之间，例如是300埃。在一些实施例中，在绝缘材料210被机械研磨之后，导电孔150的第一接触表面以及导电通孔TV的第二接触表面上会形成多个研磨记号(grinding marks)。举例来说，形成在导电孔150的第一接触表面以及导电通孔TV的第二接触表面上的研磨记号的深度可以介于100埃到500埃之间。在一些实施例中，研磨记号的宽度介于约300埃到1000埃之间。举例来说，研磨记号的宽度介于约500埃到800埃之间。
在对绝缘材料210进行研磨工艺期间，部分的保护层160a会被研磨而形成保护层160a’。在一些实施例中，在对绝缘材料210以及保护层160a进行研磨工艺期间，部分的导电通孔TV也被研磨。
如图8所示，绝缘包封体210’包覆集成电路200的侧壁，且绝缘包封体210’被导电通孔TV所贯穿。换言之，集成电路200以及导电通孔TV嵌于绝缘包封体210’中。导电通孔TV可还包括多个相对于第二接触表面(例如顶表面)的第三接触表面(例如底表面)。绝缘包封体210’可包括第一表面S1以及相对于第一表面S1的第二表面S2。导电孔150的第一接触表面以及导电通孔TV的第二接触表面在绝缘包封体210’的第一表面S1被暴露出来，而导电通孔TV的第三接触表面与介电层DI接触。导电孔150的第一接触表面以及导电通孔TV的第二接触表面实质上与绝缘包封体210’的第一表面S1共平面。导电通孔TV的第三接触表面实质上与绝缘包封体210’的第二表面S2共平面。值得注意的是，导电通孔TV的接触表面、绝缘包封体210’的第一表面S1(例如顶表面)以及导电孔150的接触表面实质上与保护层160a’的顶表面共平面。
值得注意的是，本实施例的绝缘包封体210’是经由机械研磨后形成，不需要更进一步进行化学机械研磨(chemical mechanical polishing,CMP)。因此，导电孔150的第一接触表面、导电通孔TV的第二接触表面、绝缘包封体210’的第一表面S1以及保护层160a’的顶表面具有足够的粗糙度，以提升研磨表面以及后续所形成的膜层之间的附着力。
前述的研磨记号不只存在于导电孔150的第一接触表面以及导电通孔TV的第二接触表面上，还存在于绝缘包封体210’的第一表面S1以及保护层160a’的顶表面上。
参照图9，在形成绝缘包封体210’以及保护层160a’之后，于导电通孔TV的第一接触表面、绝缘包封体210’的第一表面S1、导电孔150的第二接触表面以及保护层160a’的顶表面上形成与集成电路200的导电柱或导电孔150电连接的重布线路结构220。重布线路结构220被形成来电连接一个或多个位于其下的连接端子。此处，前述的连接端子可以是集成电路200的导电柱或导电孔150和/或被嵌于绝缘包封体210’中的导电通孔TV。以下将搭配图9，针对重布线路结构220仅行详细的说明。
参照图9，重布线路结构220包括彼此交替堆栈的多个内介电层(inter-dielectric layers)222以及多个重布线导电层224，且重布线导电层224与集成电路200的导电孔150以及嵌于绝缘包封体210’的导电通孔TV电连接。如图9所示，在一些实施例中，导电孔150的第一接触表面以及导电通孔TV的第二接触表面会与重布线路结构220接触。导电孔150的第一接触表面以及导电通孔TV的第二接触表面被最底层的内介电层222所部分覆盖。此外，最顶层的重布线导电层224包括多个接垫。在一些实施例中，前述的接垫包括用来植球(ball mount)的多个球底金属层(under-ball metallurgy,UBM)图案224a和/或用来设置被动组件的至少一个连接垫224b。本发明实施例并不限制球底金属层图案224a以及连接垫224b的数目。
由于研磨记号是形成于导电孔150的第一接触表面、导电通孔TV的第二接触表面、绝缘包封体210’的第一表面S1以及保护层160a’的顶表面上，因此前述的研磨表面以及重布线路结构220之间的附着力可被有效地提升。因此，重布线路结构220的制造良率以及可靠度可被提升。
请参照图9的放大部分，最底层的内介电层222可具有多个暴露出导电通孔TV的第一接触开口以及多个暴露出导电孔150的第二接触开口，其中暴露出导电通孔TV的第一接触开口的宽度A1例如介于10微米至50微米之间，且暴露出导电孔150的第二接触开口的宽度A2例如介于10微米至20微米之间。如图9的放大部分所示，导电通孔TV的宽度B1例如介于60微米至250微米之间，且导电孔150的宽度B2例如介于50微米至100微米之间。宽度差C1(例如第一宽度差C1)例如介于宽度A1以及宽度B1之间，且另一宽度差C2(例如第二宽度差C2)例如介于宽度A2以及宽度B2之间。在导电通孔TV以及最底层的内介电层222之间的对准误差(mis-alignment)可被宽度差C1所补偿，且在导电孔150以及最底层的内介电层222之间的对准误差可被宽度差C2所补偿。在一些实施例中，宽度差C1大于宽度差C2。举例来说，宽度差C1例如介于20微米至120微米之间，且宽度差C2例如介于10微米至45微米之间。在另一些实施例中，宽度差C1以及宽度差C2之间的比值可以介于约0.44至约12之间。
如图9所示，在形成重布线路结构220后，将多个导电球230置于球底金属层图案224a上，并将多个被动组件240设置于连接垫224b上。在一些实施例中，导电球230可以植球工艺的方式被置于球底金属层图案224a上，且被动组件240可设置于连接垫240上，并且藉由焊料与连接垫240电连接。
参照图9以及图10，在将导电球230以及被动组件240设置于重布线路结构220之后，将形成于绝缘包封体210’的第二表面S2上的介电层DI从剥离层DB上剥离，以使介电层DI与载板C分离。在一些实施例中，剥离层DB(例如光热转换释放层)可被紫外光激光照射而使介电层DI从载板C上剥离。如图10所示，介电层DI接着被图案化而形成多个接触开口O来暴露出导电通孔TV的第三接触表面(例如底表面)。接触开口O的数目对应于导电通孔TV的数目。在一些实施例中，介电层DI的接触开口O是由激光钻孔工艺所形成。
参照图11，在形成接触开口O于介电层DI中之后，将多个导电球250设置于被接触开口O所暴露出来的导电通孔TV的第三接触表面上。并且，导电球250例如是藉由回焊的方式与导电通孔TV的第三接触表面连接。如图11所示，在形成导电球230与导电球250之后，具有双边端子设计的集成电路200的整合扇出型封装便已完成。
参照图12，提供另一个封装300。在一些实施例中，封装300例如是内存或其他电子组件的封装。如图11所显示，封装300可藉由导电球250而堆栈在整合扇出型封装上，并与其电连接，从而形成堆栈式封装结构(POP)。
在前述的实施例中，整合扇出型封装的制造成本低。此外，整合扇出型封装具有好的可靠度以及良率。
以上概述了多个实施例的特征，使本领域普通技术人员可更佳了解本发明实施例的态样。本领域普通技术人员应理解，其可轻易地使用本发明实施例作为设计或修改其他工艺与结构的依据，以实行本文所介绍的实施例的相同目的和/或达到相同优点。本领域普通技术人员还应理解，这种等效的设置并不悖离本发明实施例的精神与范畴，且本领域普通技术人员在不悖离本发明实施例的精神与范畴的情况下可对本文做出各种改变、置换以及变更。

Claims (1)

1.一种整合扇出型封装，其特征在于，包括：
集成电路，包括多个导电端子；
绝缘包封体，包覆所述集成电路的侧壁；
多个导电通孔，贯穿所述绝缘包封体；以及
重布线路结构，设置于所述集成电路、所述多个导电通孔以及所述绝缘包封体上，所述重布线路结构电连接所述多个导电端子以及所述多个导电通孔，其中所述多个导电端子的多个第一接触表面以及所述多个导电通孔的多个第二接触表面与所述重布线路结构接触，且所述多个第一接触表面以及所述多个第二接触表面的粗糙度介于约100埃到约500埃之间。
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