TW201911502A - 整合扇出型封裝 - Google Patents
整合扇出型封裝 Download PDFInfo
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- TW201911502A TW201911502A TW106129928A TW106129928A TW201911502A TW 201911502 A TW201911502 A TW 201911502A TW 106129928 A TW106129928 A TW 106129928A TW 106129928 A TW106129928 A TW 106129928A TW 201911502 A TW201911502 A TW 201911502A
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- conductive
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- flux
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- 230000004907 flux Effects 0.000 claims abstract description 112
- 238000005538 encapsulation Methods 0.000 claims abstract description 26
- 229910000679 solder Inorganic materials 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 130
- 238000000034 method Methods 0.000 description 53
- 239000000463 material Substances 0.000 description 49
- 230000008569 process Effects 0.000 description 48
- 239000004593 Epoxy Substances 0.000 description 25
- 238000002161 passivation Methods 0.000 description 24
- 239000011241 protective layer Substances 0.000 description 23
- 239000004065 semiconductor Substances 0.000 description 21
- 239000011229 interlayer Substances 0.000 description 19
- 239000000758 substrate Substances 0.000 description 19
- 230000009477 glass transition Effects 0.000 description 12
- 239000011810 insulating material Substances 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000000227 grinding Methods 0.000 description 7
- 238000012360 testing method Methods 0.000 description 7
- 238000009413 insulation Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229920002577 polybenzoxazole Polymers 0.000 description 6
- 238000000465 moulding Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 239000000523 sample Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000012629 purifying agent Substances 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 150000008065 acid anhydrides Chemical class 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012459 cleaning agent Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000012628 flowing agent Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
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Abstract
一種整合扇出型封裝,所述整合扇出型封裝包括積體電路元件、絕緣包封體、重佈線路結構及多個導電端子。所述絕緣包封體在側向上包封所述積體電路元件的側壁。所述重佈線路結構設置在所述絕緣包封體及所述積體電路元件上。所述重佈線路結構電連接到所述積體電路元件且所述重佈線路結構包括多個球接墊。所述導電端子中的每一者包括導電球及環形助焊劑結構,其中所述導電球中的每一者設置在所述球接墊中的一個上且電連接到所述球接墊中的所述一個。所述環形助焊劑結構中的每一者設置在所述重佈線路結構上。所述環形助焊劑結構中的每一者圍繞所述導電球的底部部分設置且接觸所述導電球的所述底部部分。還提供一種製作整合扇出型封裝的方法。
Description
本發明的實施例是有關於一種整合扇出型封裝。
由於各種電子元件(即,電晶體、二極體、電阻器、電容器等)的集成密度的持續提高,半導體行業已經歷快速發展。在很大程度上,集成密度的此種提高來自於最小特徵大小(minimum feature size)的持續減小,此使得更多較小的元件能夠集成到給定區域中。這些較小的電子元件也需要與先前的封裝相比利用較小區域的較小的封裝。半導體元件的一些較小類型的封裝包括方形扁平封裝(quad flat package,QFP)、引腳柵陣列(pin grid array,PGA)封裝、球柵陣列(ball grid array,BGA)封裝等等。
當前,整合扇出型封裝因其緊湊性而正變得日漸流行。在包括被模制化合物(molding compound)包封的至少一個晶圓的整合扇出型封裝中,製作在模制化合物上的重佈線路結構與形成在所述重佈線路結構上的導電端子之間的電連接的可靠性可能因在所述重佈線路結構中的導電層與介電層之間的介面處發生的層離(delamination)而劣化。如何提高整合扇出型封裝的製作良率(yield rate)受到高度關注。
根據本發明的一些實施例,提供一種整合扇出型封裝,所述整合扇出型封裝包括積體電路元件、絕緣包封體、重佈線路結構及多個導電端子。所述絕緣包封體在側向上包封所述積體電路元件的側壁。所述重佈線路結構設置在所述絕緣包封體及所述積體電路元件上。所述重佈線路結構電連接到所述積體電路元件且所述重佈線路結構包括多個球接墊。所述導電端子中的每一者包括導電球及環形助焊劑結構,其中所述導電球中的每一者設置在所述球接墊中的一個上且電連接到所述球接墊中的所述一個。所述環形助焊劑結構中的每一者設置在所述重佈線路結構上。所述環形助焊劑結構中的每一者圍繞所述導電球的底部部分設置且接觸所述導電球的所述底部部分。
根據本發明的替代性實施例,提供一種整合扇出型封裝,所述整合扇出型封裝包括積體電路元件、絕緣包封體、重佈線路結構及多個導電端子。所述絕緣包封體在側向上包封所述積體電路元件的側壁。所述重佈線路結構設置在所述絕緣包封體及所述積體電路元件上。所述重佈線路結構電連接到所述積體電路元件。所述重佈線路結構包括交替堆疊的多個重佈線導電層與多個層間介電層,所述重佈線導電層中的最頂部的一個重佈線導電層被所述層間介電層中的最頂部的一個層間介電層覆蓋,所述重佈線導電層中的所述最頂部的一個重佈線導電層包括多個球接墊,且所述層間介電層中的所述最頂部的一個層間介電層包括與所述球接墊對應的多個接觸開口。所述導電端子中的每一者包括導電球環形助焊劑結構。所述導電球中的每一者設置在所述球接墊中的一個上且電連接到所述球接墊中的所述一個。所述環形助焊劑結構中的每一者圍繞所述導電球的底部部分設置。所述環形助焊劑結構中的每一者填充所述導電球的所述底部部分與所述重佈線路結構之間的空間。所述環形助焊劑結構中的每一者包括第一接合表面及第二接合表面,所述第一接合表面接觸所述導電球的所述底部部分,所述第二接合表面接觸所述重佈線路結構。
根據本發明的又一些替代性實施例,提供一種製作整合扇出型封裝的方法。所述方法包括以下步驟。在載體上提供積體電路元件。在所述載體上形成絕緣包封體,以包封所述積體電路元件的側壁。在所述積體電路元件及所述絕緣包封體上形成重佈線路結構,其中所述重佈線路結構電連接到所述積體電路元件,且所述重佈線路結構包括多個球接墊。在所述重佈線路結構上形成助焊劑材料,其中所述助焊劑材料是圍繞所述球接墊形成。將多個導電球放置在所述球接墊上。藉由執行回焊製程將所述導電球與所述球接墊進行接合,以從所述助焊劑材料形成多個環形助焊劑結構,其中所述環形助焊劑結構設置在所述重佈線路結構上,所述環形助焊劑結構中的每一者分別圍繞所述導電球中的一個的底部部分設置且接觸所述導電球中的所述一個的所述底部部分。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述元件及配置的具體實例以簡化本揭露內容。當然,該些僅為實例且不旨在進行限制。舉例而言,以下說明中將第一特徵形成於第二特徵「上方」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例,且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、以使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外,本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的,但自身並不指示所論述的各種實施例及/或配置之間的關係。
另外,為易於說明,本文中可使用例如「在...之下」、「在...下麵」、「下部」、「在…上方」、「上部」等空間相對性用語來闡述圖中所示一個元件或特徵與另一(其他)元件或特徵的關係。除了圖中所繪示的定向之外,所述空間相對性用語旨在涵蓋裝置在使用或操作中的不同定向。設備可被另外定向(旋轉90度或處於其他定向),且本文所用的空間相對性描述詞可同樣相應地進行解釋。
還可包括其他特徵及製程。舉例來說,可包括測試結構,以説明對三維(3D)封裝或三維積體電路(3DIC)裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基材上形成的測試墊,所述測試墊使得能夠對三維封裝或三維積體電路進行測試、對探針及/或探針卡(probe card)進行使用等。可對中間結構以及最終結構執行驗證測試。另外,本文中所公開的結構及方法可結合包括對已知良好晶粒進行中間驗證的測試方法而使用,以提高良率(yield)並降低成本。
圖1至圖13說明製作根據一些實施例的整合扇出型封裝的製程,且圖14是說明根據一些實施例的疊層封裝(POP)結構的剖視圖。
參照圖1,提供包括排列成陣列的多個晶粒(die)或積體電路200的晶圓100。在對晶圓100執行晶圓切割製程(wafer dicing process)之前,晶圓100中的積體電路200是彼此實體連接的。在一些實施例中,晶圓100包括半導體基材110、形成在半導體基材110上的多個導電接墊120及鈍化層(passivation layer)130。鈍化層130形成在半導體基材110之上且具有多個接觸開口132,進而使得導電接墊120被鈍化層130的接觸開口132局部地暴露出。舉例來說,半導體基材110可為矽基材,所述矽基材包括形成在所述矽基材中的主動元件(例如,電晶體等)及被動元件(例如,電阻器、電容器、電感器等);導電接墊120可為鋁接墊、銅接墊或其他適合的金屬接墊;且鈍化層130可為氧化矽層、氮化矽層、氮氧化矽層或由其他適合的介電材料形成的介電層。
如圖1中所示,在一些實施例中,晶圓100可視情況包括形成在鈍化層130之上的後鈍化層(post-passivation layer)140。後鈍化層140覆蓋鈍化層130且具有多個接觸開口142。被鈍化層130的接觸開口132所局部地暴露出的導電接墊120會被後鈍化層140的接觸開口142局部地暴露出。舉例來說,後鈍化層140可為聚醯亞胺(polyimide,PI)層、聚苯並惡唑(polybenzoxazole,PBO)層或由其他適合的介電聚合物形成的介電層。
參照圖2,在晶圓100的導電接墊120上形成多個導電柱150。在一些實施例中,藉由導電材料的電鍍製程(plating process)在導電接墊120上形成導電柱150。以下詳細闡述導電柱150的電鍍製程。首先,將晶種層沉積(例如,藉由濺鍍(sputtering))到後鈍化層140及被接觸開口142所暴露出的導電接墊120上。接著藉由旋轉塗佈(spin coating)光阻材料層、烘烤(baking)所述光阻材料層及微影(photolithography)(即,曝光製程(exposure process)與顯影製程(development process))在晶種層之上形成具有預定圖案的圖案化光阻層(圖中未示出)。晶種層與導電接墊120對應的部分被圖案化光阻層暴露出。接著,將包括形成在晶圓100上的圖案化光阻層的晶圓100浸入至電鍍槽(plating bath)中,進而使得導電柱150電鍍在晶種層與導電接墊120對應的所述部分上且被圖案化光阻層顯露出。在形成導電柱150之後,藉由例如蝕刻(etching)、灰化(ash)或其他適合的移除製程剝除圖案化光阻層。此後,利用導電柱150作為硬罩幕,例如藉由刻蝕移除晶種層未被導電柱150所覆蓋的另一部分直至暴露出後鈍化層140為止。
在一些實施例中,導電柱150為經電鍍銅柱或其他適合的金屬柱。在一些替代性實施例中,導電柱150為被焊料頂蓋(solder cap)(例如,不含鉛的焊料頂蓋)所覆蓋的銅柱或其他適合的金屬柱。
參照圖3,在形成導電柱150之後,在晶圓100的後鈍化層140上形成保護層160,進而使得導電柱150被保護層160覆蓋。在一些實施例中,保護層160可為具有足以包封及保護導電柱150的厚度的聚合物層。在一些實施例中,保護層160可為聚苯並惡唑(PBO)層、聚醯亞胺(PI)層或其他適合的聚合物層。在一些替代實施例中,保護層160可由無機材料製成。如圖3中所示,保護層160具有實質上平坦的頂表面且保護層160的最大厚度大於導電柱150的高度。
參照圖4,在形成保護層160之後,可視需要對晶圓100的背表面執行背側研磨製程(back side grinding process)。在所述背側研磨製程期間,可局部地研磨半導體基材110,進而使得形成包括薄化半導體基材110’的薄化晶圓100’。在一些實施例中,可藉由機械研磨或其他適合的研磨製程或拋光製程(polishing process)研磨晶圓100的背表面。
參照圖5,在執行背側研磨製程之後,對薄化晶圓100’執行晶圓切割製程,進而使得薄化晶圓100’中的積體電路200彼此單體化。經單體化的積體電路200中的每一者可包括半導體基材110a、形成在半導體基材110a上的導電接墊120、鈍化層130a、後鈍化層140a、導電柱150及保護層160a。如圖4及圖5中所示,半導體基材110a、鈍化層130a、後鈍化層140a及保護層160a的材料及特性與半導體基材110、鈍化層130、後鈍化層140及保護層160的材料及特性相同。因此,為簡潔起見,本文中不再對半導體基材110a、鈍化層130a、後鈍化層140a及保護層160a予以贅述。
如圖4及圖5中所示,在背側研磨製程及晶圓切割製程期間,保護層160及160a可妥善地保護積體電路200的導電柱150。另外,保護層160及160a可保護積體電路200的導電柱150不被例如積體電路200的拾取及放置製程(pick-up and placing process)、模制製程(molding process)等依序執行的製程損壞。
參照圖6,在積體電路200從薄化晶圓100’(在圖4中示出)被單體化之後,提供上面形成有剝離層(de-bonding layer)DB及介電層DI的載體C,其中剝離層DB位於載體C與介電層DI之間。在一些實施例中,載板C可為玻璃基材,剝離層DB可為形成在所述玻璃基材上的光-熱轉換(light-to-heat conversion,LTHC)釋放層,且介電層DI可為形成在剝離層DB上的聚苯並惡唑(PBO)層。
在提供上面形成有剝離層DB及介電層DI的載體C之後,在介電層DI上形成多個導電穿孔TV。在一些實施例中,藉由旋轉塗佈光阻材料層、烘烤所述光阻材料層、微影(即,曝光製程與顯影製程)、電鍍(例如,有電電鍍(electro-plating)或無電電鍍(electro-less plating))及光阻剝除製程形成所述多個導電穿孔TV。舉例來說,導電穿孔TV包括銅柱(copper post)或其他適合的金屬柱。
在一些實施例中,在形成導電穿孔TV之前,可在由載體C所承載的介電層DI上形成背側重佈線路結構(圖中未示出),且導電穿孔TV可形成在所述背側重佈線路結構上且電連接到所述背側重佈線路結構。
如圖6中所示,在一些實施例中,拾取積體電路200中包括形成於其上的導電接墊120、導電柱150及保護層160a的一個積體電路200並且放置在由載體C所承載的介電層DI上。藉由晶粒貼合膜(die attach film,DAF)(圖中未示出)、黏合膏(adhesion paste)等將積體電路200貼合或黏合在介電層DI上。在一些替代實施例中,拾取積體電路200中的兩個或更多個積體電路200並且放置在由載體C所承載的介電層DI上,其中放置在介電層DI上的積體電路200可排列成陣列。在一些實施例中,當放置在介電層DI上的積體電路200排列成陣列時,可將導電穿孔TV分類成多個群組。積體電路200的數目對應於導電穿孔TV的群組的數目。
如圖6中所示,保護層160a的頂表面低於導電穿孔TV的頂表面。然而,本發明並不僅限於此。在一些替代性實施例中,保護層160a的頂表面可與導電穿孔TV的頂表面實質上對齊。在又一些替代性實施例中,保護層160a的頂表面可高於導電穿孔TV的頂表面,且導電柱150的頂表面可低於、高於導電穿孔TV的頂表面或與導電穿孔TV的所述頂表面實質上對齊。
如圖6中所示,在形成導電穿孔TV之後將積體電路200拾取及放置在介電層DI上。然而,本發明並不僅限於此。在一些替代性實施例中,在形成導電穿孔TV之前將積體電路200拾取及放置在介電層DI上。
參照圖7,在介電層DI上形成絕緣材料210以覆蓋積體電路200及導電穿孔TV。在一些實施例中,絕緣材料210是藉由模制製程而形成的模制化合物。積體電路200的導電柱150及保護層160a被絕緣材料210覆蓋。換句話說,積體電路200的導電柱150及保護層160a不被絕緣材料210顯露出且被絕緣材料210妥善地保護。在一些實施例中,絕緣材料210包括環氧樹脂或其他適合的介電材料。
參照圖8,接著研磨絕緣材料210直至暴露出導電柱150的頂表面、導電穿孔TV的頂表面及保護層160a的頂表面為止。在一些實施例中,藉由機械研磨製程及/或化學機械拋光(chemical mechanical polishing,CMP)製程研磨絕緣材料210。在研磨絕緣材料210之後,在介電層DI之上形成絕緣包封體210’。在絕緣材料210的研磨製程期間,研磨保護層160a的部分以形成保護層160a’。在一些實施例中,在絕緣材料210及保護層160a的研磨製程期間,也會略微研磨導電穿孔TV的部分及導電柱150的部分。
如圖8中所示,絕緣包封體210’在側向上包封積體電路200的側壁,且絕緣包封體210’被導電穿孔TV穿透。換句話說,積體電路200及導電穿孔TV嵌於絕緣包封體210’中。應注意,導電穿孔TV的頂表面、絕緣包封體210’的頂表面及導電柱150的頂表面與保護層160a’的頂表面實質上共面。
參照圖9,在形成絕緣包封體210’及保護層160a’之後,在導電穿孔TV的頂表面、絕緣包封體210’的頂表面、導電柱150的頂表面及保護層160a’的頂表面上形成與積體電路200的導電柱150以及導電穿孔TV電連接的前側重佈線路結構220。所製作出的將前側重佈線路結構220與位於其下方的一個或多個連接件電連接。此處,前述連接件可為上述背側重佈線路結構、積體電路200的導電柱150及/或嵌於絕緣包封體210’中的導電穿孔TV。將結合圖9來詳細闡述前側重佈線路結構220。
參照圖9,前側重佈線路結構220包括交替堆疊的多個層間介電層(inter-dielectric layer)222與多個重佈線導電層224,且重佈線導電層224電連接到積體電路200的導電柱150及嵌於絕緣包封體210’中的導電穿孔TV。導電柱150的頂表面及導電穿孔TV的頂表面被層間介電層222中的最底部的一個層間介電層222局部地覆蓋。重佈線導電層224中的最頂部的一個重佈線導電層224會被層間介電層222中的最頂部的一個層間介電層222局部地覆蓋,其中重佈線導電層224中的最頂部的一個重佈線導電層224包括多個球接墊P1且層間介電層222中的最頂部的一個層間介電層222包括與球接墊P1對應的多個接觸開口222a。
參照圖10,在形成前側重佈線路結構220之後,執行植球製程(ball placement process)。在執行植球製程之前,可不需要事先在球接墊P1上形成球下金屬(under-ball metallurgy)。因此,整合扇出型封裝的製作複雜度及製作成本可降低。以下將詳細闡述植球製程。
植球製程可包括以下步驟。在前側重佈線路結構220上形成助焊劑材料F1,接著將多個導電球240(例如,焊料球)放置在球接墊P1上。在一些實施例中,可在將導電球240放置在球接墊P1上之前形成助焊劑材料F1。在一些替代性實施例中,可在將導電球240放置在球接墊P1上之後形成助焊劑材料F1。如圖10中所示,助焊劑材料F1形成在重佈線導電層224中的最頂部的一個的頂表面上且圍繞球接墊P1分佈;助焊劑材料F1可在接觸開口222a外部分佈且助焊劑材料F1可藉由助焊劑分配製程(flux dispensing process)、助焊劑印刷製程(flux printing process)或其他適合的製程形成在前側重佈線路結構220上;並且導電球240的位置可由接觸開口222a來限定。在一些實施例中,助焊劑材料F1可為不含氮化物的環氧系助焊劑膏且助焊劑材料F1中的固含量可介於約10%至約50%範圍內。舉例來說,助焊劑材料F1可為包括酚醛樹脂、酸酐樹脂等的環氧系助焊劑。在一些替代性實施例中,助焊劑材料F1可為液態的不含氮化物的環氧系助焊劑且助焊劑材料F1中的固含量可介於約10%至約50%範圍內。
在一些替代性實施例中,重佈線導電層224中的最頂部的一個重佈線導電層224可進一步包括多個連接接墊P2,層間介電層222中的最頂部的一個層間介電層222可進一步包括與連接接墊P2對應的多個接觸開口222b,且另一助焊劑材料F3可形成在前側重佈線路結構220上且圍繞接觸開口222b分佈。舉例來說,助焊劑材料F1與助焊劑材料F3是相同的材料且可藉由同一種製程形成。如圖10中所示,在連接接墊P2上提供至少一個表面安裝裝置250(例如,被動元件)。舉例來說,表面安裝裝置250包括電極E及形成在表面安裝裝置250的電極E上的焊料S。
參照圖11,執行熱製程(thermal process)或回焊製程(reflow process)來加熱助焊劑材料F1及導電球240,進而使得導電球240與球接墊P1進行接合。在上述熱製程或回焊製程期間,助焊劑材料F1被加熱且充當化學清潔劑(chemical cleaning agent)、流動劑(flowing agent)及/或淨化劑(purifying agent),以促進導電球240與球接墊P1之間的金屬接合。此外,執行熱製程來加熱助焊劑材料F3及焊料S,進而使得表面安裝裝置250的電極E與連接接墊P2藉由焊料S進行接合。在上述熱製程期間,助焊劑材料F3被加熱且充當化學清潔劑、流動劑及/或淨化劑,以促進焊料S與連接接墊P2之間的金屬接合。
在執行上述熱製程或回焊製程之後,助焊劑材料F1轉變成多個環形助焊劑結構F2且助焊劑材料F3轉變成環形助焊劑結構F4。如圖11中所示,環形助焊劑結構F2中的每一者的外輪廓可為圓形的。然而,環形助焊劑結構F2中的每一者的外輪廓並不限於此。儘管環形助焊劑結構F2是由助焊劑材料F1製成,但環形助焊劑結構F2的組成不同於助焊劑材料F1的組成。在一些實施例中,環形助焊劑結構F2的材料包括不含氮化物的環氧系助焊劑(例如,酚醛樹脂);不含氮化物的環氧系助焊劑的玻璃轉變溫度(Tg)可介於約60攝氏度到約180攝氏度範圍內;及/或不含氮化物的環氧系助焊劑的楊氏模量可介於約4 GPa到約10 GPa範圍內。在此種實施例中,不含氮化物的環氧系助焊劑在低於玻璃轉變溫度(Tg)的第一溫度下所測量的熱膨脹係數(a1-CTE)可介於約30到約60範圍內,而環氧系助焊劑在高於玻璃轉變溫度(Tg)的第二溫度下所測量的熱膨脹係數(a2-CTE)可介於約100到約160範圍內。
如圖11中所示,在執行植球製程之後,形成與球接墊P1進行接合的多個導電端子。導電端子中的每一者包括導電球240及環形助焊劑結構F2中的一者,其中環形助焊劑結構F2中的每一者分別圍繞導電球240的底部部分設置且接觸導電球240的所述底部部分。在一些實施例中,環形助焊劑結構F2中的每一者填充對應導電球240的底部部分與前側重佈線路結構220之間的空間,其中環形助焊劑結構F2中的每一者包括第一接合表面BS1及第二接合表面BS2,第一接合表面BS1接觸對應導電球240的底部部分,第二接合表面BS2接觸前側重佈線路結構220。舉例來說,環形助焊劑結構F2中的每一者可對應地延伸至其中一個接觸開口222a(在圖10中示出)。由於環形助焊劑結構F2中的每一者填充對應導電球240的底部部分與前側重佈線路結構220之間的空間,因此可增強導電球240的接合可靠性且可防止最頂部的重佈線導電層224與最頂部的層間介電層222之間發生層離。
如圖11中所示,環形助焊劑結構F4包封焊料S且局部地覆蓋表面安裝裝置250的電極E。
在一些實施例中,可將環形助焊劑結構F2稱作助焊劑材料F1的殘留物,且環形助焊劑結構F2是在熱製程期間藉由助焊劑材料F1與導電球240的反應而形成。可將環形助焊劑結構F4稱作助焊劑材料F3的殘留物,且環形助焊劑結構F4是在熱製程期間藉由助焊劑材料F3與焊料S的反應而形成。
參照圖11及圖12,在前側重佈線路結構220上安裝導電球240及表面安裝裝置250之後,使形成在介電層DI的所得產物從剝離層DB剝離,進而使得所得產物及介電層DI從載體C分離。在一些實施例中,可藉由紫外(UV)雷射照射剝離層DB(例如,所述光-熱轉換釋放層),進而使得介電層DI從載體C脫落(peel)。
如圖12中所示,接著將介電層DI圖案化以形成多個接觸開口O,進而暴露出導電穿孔TV的底表面。接觸開口O的數目及位置對應於導電穿孔TV的數目。在一些實施例中,藉由雷射鑽孔製程(laser drilling process)或其他適合的圖案化製程形成介電層DI的接觸開口O。
參照圖13,在介電層DI中形成接觸開口O之後,將多個導電球260放置在導電穿孔TV被接觸開口O暴露出的底表面上。並且,舉例來說,對導電球260進行回焊以使導電球260與導電穿孔TV的底表面進行接合。如圖13中所示,在形成導電球240及導電球260之後,具有雙側端子設計(即,導電球240及260)的積體電路200的整合扇出型封裝便已初步製作完成。
參照圖14,接著提供另一半導體裝置300(例如,表面安裝型封裝)。在一些實施例中,半導體裝置300為例如記憶體裝置或其他適合的半導體裝置。半導體裝置300堆疊在圖12中所示整合扇出型封裝之上並藉由導電球260電連接到所述整合扇出型封裝,進而製作出疊層封裝(POP)結構。
在上述實施例中,環形助焊劑結構F2及環形助焊劑結構F4會增強導電球240與球接墊P1之間的接合強度。因此,整合扇出型封裝的可靠性增強。
根據本發明的一些實施例,提供一種整合扇出型封裝,所述整合扇出型封裝包括積體電路元件、絕緣包封體、重佈線路結構及多個導電端子。所述絕緣包封體在側向上包封所述積體電路元件的側壁。所述重佈線路結構設置在所述絕緣包封體及所述積體電路元件上。所述重佈線路結構電連接到所述積體電路元件且所述重佈線路結構包括多個球接墊。所述導電端子中的每一者包括導電球及環形助焊劑結構,其中所述導電球中的每一者設置在所述球接墊中的一個上且電連接到所述球接墊中的所述一個。所述環形助焊劑結構中的每一者設置在所述重佈線路結構上。所述環形助焊劑結構中的每一者圍繞所述導電球的底部部分設置且接觸所述導電球的所述底部部分。
根據本發明的一些實施例,所述重佈線路結構包括交替堆疊的多個重佈線導電層與多個層間介電層,所述層間介電層中的最頂部的一個層間介電層包括與所述球接墊對應的多個接觸開口,所述導電端子的所述環形助焊劑結構設置在所述層間介電層中的所述最頂部的一個層間介電層上且接觸所述層間介電層中的所述最頂部的一個層間介電層。
根據本發明的一些實施例,所述導電球的材料包括焊料。
根據本發明的一些實施例,所述環形助焊劑結構的材料包括不含氮化物的環氧系助焊劑。
根據本發明的一些實施例,所述環氧系助焊劑的玻璃轉變溫度(Tg)介於約60攝氏度到約180攝氏度範圍內。
根據本發明的一些實施例,所述環氧系助焊劑的楊氏模量介於約4 GPa到約10 GPa範圍內。
根據本發明的一些實施例,所述環氧系助焊劑的第一熱膨脹係數(a1-CTE)介於約30到約60範圍內,所述環氧系助焊劑的第二熱膨脹係數(a2-CTE)介於100到180範圍內,所述第一熱膨脹係數(a1-CTE)是在低於所述玻璃轉變溫度的溫度下測量,且所述第二熱膨脹係數(a2-CTE)是在高於所述玻璃轉變溫度的溫度下測量。
根據本發明的替代性實施例,提供一種整合扇出型封裝,所述整合扇出型封裝包括積體電路元件、絕緣包封體、重佈線路結構及多個導電端子。所述絕緣包封體在側向上包封所述積體電路元件的側壁。所述重佈線路結構設置在所述絕緣包封體及所述積體電路元件上。所述重佈線路結構電連接到所述積體電路元件。所述重佈線路結構包括交替堆疊的多個重佈線導電層與多個層間介電層,所述重佈線導電層中的最頂部的一個重佈線導電層被所述層間介電層中的最頂部的一個層間介電層覆蓋,所述重佈線導電層中的所述最頂部的一個重佈線導電層包括多個球接墊,且所述層間介電層中的所述最頂部的一個層間介電層包括與所述球接墊對應的多個接觸開口。所述導電端子中的每一者包括導電球環形助焊劑結構。所述導電球中的每一者設置在所述球接墊中的一個上且電連接到所述球接墊中的所述一個。所述環形助焊劑結構中的每一者圍繞所述導電球的底部部分設置。所述環形助焊劑結構中的每一者填充所述導電球的所述底部部分與所述重佈線路結構之間的空間。所述環形助焊劑結構中的每一者包括第一接合表面及第二接合表面,所述第一接合表面接觸所述導電球的所述底部部分,所述第二接合表面接觸所述重佈線路結構。
根據本發明的一些實施例,所述環形助焊劑結構接觸所述層間介電層中的所述最頂部的一個層間介電層並延伸到所述接觸開口中。
根據本發明的一些實施例,所述導電球的材料包括焊料。
根據本發明的一些實施例,所述環形助焊劑結構的材料包括不含氮化物的環氧系助焊劑。
根據本發明的一些實施例,所述環氧系助焊劑的玻璃轉變溫度(Tg)介於約60攝氏度到約180攝氏度範圍內。
根據本發明的一些實施例,所述環氧系助焊劑的楊氏模量介於約4 GPa到約10 GPa範圍內。
根據本發明的一些實施例,所述環氧系助焊劑的第一熱膨脹係數(a1-CTE)介於約30到約60範圍內,所述環氧系助焊劑的第二熱膨脹係數(a2-CTE)介於100到180範圍內,所述第一熱膨脹係數(a1-CTE)是在低於所述玻璃轉變溫度的溫度下測量,且所述第二熱膨脹係數(a2-CTE)是在高於所述玻璃轉變溫度的溫度下測量。
根據本發明的又一些替代性實施例,提供一種製作整合扇出型封裝的方法。所述方法包括以下步驟。在載體上提供積體電路元件。在所述載體上形成絕緣包封體,以包封所述積體電路元件的側壁。在所述積體電路元件及所述絕緣包封體上形成重佈線路結構,其中所述重佈線路結構電連接到所述積體電路元件,且所述重佈線路結構包括多個球接墊。在所述重佈線路結構上形成助焊劑材料,其中所述助焊劑材料是圍繞所述球接墊形成。將多個導電球放置在所述球接墊上。藉由執行回焊製程將所述導電球與所述球接墊進行接合,以從所述助焊劑材料形成多個環形助焊劑結構,其中所述環形助焊劑結構設置在所述重佈線路結構上,所述環形助焊劑結構中的每一者分別圍繞所述導電球中的一個的底部部分設置且接觸所述導電球中的所述一個的所述底部部分。
根據本發明的一些實施例,所述助焊劑材料包括不含氮化物的環氧系助焊劑,且所述助焊劑材料中的固含量介於約10%到約50%範圍內。
根據本發明的一些實施例,所述環形助焊劑結構的材料包括不含氮化物的環氧系助焊劑。
根據本發明的一些實施例,所述環氧系助焊劑的玻璃轉變溫度(Tg)介於約60攝氏度到約180攝氏度範圍內。
根據本發明的一些實施例,所述環氧系助焊劑的楊氏模量介於約4 GPa到約10 GPa範圍內。
根據本發明的一些實施例,所述環氧系助焊劑的第一熱膨脹係數(a1-CTE)介於約30到約60範圍內,所述環氧系助焊劑的第二熱膨脹係數(a2-CTE)介於100到180範圍內,所述第一熱膨脹係數(a1-CTE)是在低於所述玻璃轉變溫度的溫度下測量,且所述第二熱膨脹係數(a2-CTE)是在高於所述玻璃轉變溫度的溫度下測量。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100‧‧‧晶圓
100’‧‧‧薄化晶圓
110‧‧‧半導體基材
110a‧‧‧半導體基材
110’‧‧‧薄化半導體基材
120‧‧‧導電接墊
130、130a‧‧‧鈍化層
132‧‧‧接觸開口
140、140a‧‧‧後鈍化層
142‧‧‧接觸開口
150‧‧‧導電柱
160、160a、160a’‧‧‧保護層
200‧‧‧積體電路
210‧‧‧絕緣材料
210’‧‧‧絕緣包封體
220‧‧‧前側重佈線路結構
222‧‧‧層間介電層
222a、222b‧‧‧接觸開口
224‧‧‧重佈線導電層
240、260‧‧‧導電球
250‧‧‧表面安裝裝置
300‧‧‧半導體裝置
BS1‧‧‧第一接合表面
BS2‧‧‧第二接合表面
C‧‧‧載體
DB‧‧‧剝離層
DI‧‧‧介電層
E‧‧‧電極
F1、F3‧‧‧助焊劑材料
F2‧‧‧環形助焊劑結構
F4‧‧‧環形助焊劑結構
O‧‧‧接觸開口
P1‧‧‧球接墊
P2‧‧‧連接接墊
S‧‧‧焊料
TV‧‧‧導電穿孔
結合附圖閱讀以下詳細說明,會最好地理解本發明的各個方面。應注意,各種特徵並非按比例繪製。事實上,爲論述清晰起見,可任意增大或減小各種特徵的尺寸。 圖1至圖13說明製作根據一些實施例的整合扇出型封裝的製程。 圖14是說明根據一些實施例的疊層封裝(package-on-package,POP)結構的剖視圖。
Claims (1)
- 一種整合扇出型封裝,包括: 積體電路元件; 絕緣包封體,在側向上包封所述積體電路元件的側壁; 重佈線路結構,設置在所述絕緣包封體及所述積體電路元件上,所述重佈線路結構電連接到所述積體電路元件,所述重佈線路結構包括多個球接墊; 多個導電端子,所述導電端子中的每一者包括: 導電球,設置在所述球接墊中的一個上且電連接到所述球接墊中的所述一個;以及 環形助焊劑結構,設置在所述重佈線路結構上,其中所述環形助焊劑結構圍繞所述導電球的底部部分設置且接觸所述導電球的所述底部部分。
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US15/662,266 | 2017-07-27 |
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US11031342B2 (en) | 2017-11-15 | 2021-06-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method |
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US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US8797057B2 (en) | 2011-02-11 | 2014-08-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Testing of semiconductor chips with microbumps |
US9000584B2 (en) | 2011-12-28 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor device with a molding compound and a method of forming the same |
US9111949B2 (en) | 2012-04-09 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of wafer level package for heterogeneous integration technology |
US20130307153A1 (en) | 2012-05-18 | 2013-11-21 | International Business Machines Corporation | Interconnect with titanium-oxide diffusion barrier |
US9263511B2 (en) | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
US9048222B2 (en) | 2013-03-06 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating interconnect structure for package-on-package devices |
US9368460B2 (en) | 2013-03-15 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out interconnect structure and method for forming same |
US9281254B2 (en) | 2014-02-13 | 2016-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming integrated circuit package |
US9496189B2 (en) | 2014-06-13 | 2016-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked semiconductor devices and methods of forming same |
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US20160148864A1 (en) * | 2014-11-21 | 2016-05-26 | Qualcomm Incorporated | Integrated device package comprising heterogeneous solder joint structure |
US10079192B2 (en) * | 2015-05-05 | 2018-09-18 | Mediatek Inc. | Semiconductor chip package assembly with improved heat dissipation performance |
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