TWI791336B - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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TWI791336B
TWI791336B TW110143895A TW110143895A TWI791336B TW I791336 B TWI791336 B TW I791336B TW 110143895 A TW110143895 A TW 110143895A TW 110143895 A TW110143895 A TW 110143895A TW I791336 B TWI791336 B TW I791336B
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Taiwan
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layer
wafer
chip
hole
molding
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TW110143895A
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TW202224121A (zh
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劉子正
郭正錚
郭宏瑞
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例的一種半導體封裝包括第一晶片、第二晶片、第一黏合層、第二黏合層及模塑層。第一黏合層在第一晶片的第一表面上，第二黏合層在所述第二晶片的第二表面上。所述第一黏合層及所述第二黏合層的厚度不同，且所述第一晶片與所述第一黏合層的總厚度實質上等於所述第二晶片與所述第二黏合層的總厚度。模塑層包封所述第一晶片、所述第二晶片、所述第一黏合層及所述第二黏合層。

Description

半導體封裝及其製造方法
本發明實施例是有關於一種半導體封裝及其製造方法。
正在開發用於晶片級封裝的三維集成技術來滿足高密度集成封裝對尺寸減小、高性能內連線、及異質集成（heterogeneous integration）的需求。
本發明實施例的一種半導體封裝包括第一晶片、第二晶片、第一黏合層、第二黏合層及模塑層。第一黏合層在第一晶片的第一表面上，第二黏合層在所述第二晶片的第二表面上。所述第一黏合層及所述第二黏合層的厚度不同，且所述第一晶片與所述第一黏合層的總厚度實質上等於所述第二晶片與所述第二黏合層的總厚度。模塑層包封所述第一晶片、所述第二晶片、所述第一黏合層及所述第二黏合層。
本發明實施例的一種半導體封裝包括第一晶片、第二晶片以及模塑化合物。第一晶片具有突出於所述第一晶片的第一通孔。第二晶片具有突出於所述第二晶片的第二通孔，其中所述第一晶片的厚度不同於所述第二晶片的厚度。模塑化合物包封所述第一晶片、所述第二晶片、所述第一通孔以及所述第二通孔，其中所述第一通孔，所述第二通孔以及所述模塑化合物的表面實質上共面。
本發明實施例的一種半導體封裝包括第一晶片、第二晶片以及模塑化合物。第一晶片具有由所述第一晶片延伸的第一通孔。第二晶片具有由所述第二晶片延伸的第二通孔，其中所述第一通孔的延伸部分的高度不同於所述第二通孔的延伸部分的高度。模塑化合物包封所述第一晶片、所述第二晶片、所述第一通孔以及所述第二通孔。
本發明實施例的一種半導體封裝包括第一晶片、第二晶片以及模塑化合物。第一晶片具有第一電性連接件。第二晶片具有第二電性連接件。所述模塑化合物的表面、所述第一電性連接件以及所述第二電性連接件的表面實質上共面，且所述第一電性連接件以及所述第二電性連接件中的至少一者與所述模塑化合物分開。
以下公開提供用於實作所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本公開內容可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
另外，本文中可能使用例如“位於...之下（beneath）”、“位於...下麵（below）”、“下部的（lower）”、“位於...上方（above）”、“上部的（upper）”等空間相對性用語以便於闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括器件在使用或操作中的不同取向。裝置可具有其他取向（旋轉90度或其他取向），且本文中所用的空間相對性用語可同樣相應地進行解釋。
另外，為易於說明，本文中可使用例如“第一”、“第二”、“第三”、“第四”等用語來闡述與圖中所示相似或不同的元件或特徵，且可依據存在的次序或說明的上下文而互換地使用。
也可包括其他特徵及製程。舉例來說，可包括測試結構，以說明對三維（three dimensional，3D）封裝或三維積體電路（three dimensional integrated circuit，3DIC）器件進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試接墊（test pad），以便能夠對三維封裝或三維積體電路進行測試、對探針及/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，可將本文中所公開的結構及方法與包括對已知良好晶粒進行中間驗證的測試方法結合使用，以提高良率並降低成本。
圖1A至圖1G是根據一些示例性實施例的半導體封裝的製造方法中的各個階段的示意性剖視圖。在示例性實施例中，所述半導體製造方法是封裝製程的一部分。在一些實施例中，繪示兩個晶片來代表多個晶片，且繪示一個或多個封裝來代表在半導體製造方法之後獲得的多個半導體封裝。
參照圖1A，提供載板C。在載板C之上依序堆疊剝離層DB及黏合層103。在一些實施例中，在載板C的上表面上形成剝離層DB，且剝離層DB位於載板C與黏合層103之間。載板C例如為玻璃基底。另一方面，在一些實施例中，剝離層DB是在玻璃基底上形成的光熱轉換（light-to heat-conversion，LTHC）釋放層。在一些實施例中，黏合層103是晶粒貼合膜（die attach film，DAF）。然而，剝離層DB、載板C、及黏合層103的材料僅用於說明，且本公開並非僅限於此。
參照圖1B，在載板C之上設置有多個層間穿孔（through interlayer via，TIV）102、第一晶片（晶粒）110、及第二晶片（晶粒）130。使用黏合層103將第一晶片110及第二晶片130放置到上面形成有層間穿孔102的剝離層DB上。第一晶片110與第二晶片130彼此相鄰且被層間穿孔102環繞。在一些實施例中，第一晶片110與第二晶片130可為相同類型的晶片或不同類型的晶片，且可為數位晶片、類比晶片、或混合訊號晶片，例如應用專用積體電路（application-specific integrated circuit，“ASIC”）晶片、高頻寬記憶體（high bandwidth memory，HBM）晶片、感測器晶片、無線射頻晶片（wireless and radio frequency chip）、記憶體晶片、邏輯晶片、或電壓調節器晶片。
在一些實施例中，第一晶片110與第二晶片130具有不同的厚度t1、t2。在一些實施例中，第一晶片110包括主動表面112、分佈在主動表面112上的多個接墊114、覆蓋主動表面112的鈍化層116、多個第一通孔118、以及保護層120。接墊114被鈍化層116局部地暴露出，第一通孔118設置在接墊114上並電連接到接墊114，且保護層120覆蓋第一通孔118及鈍化層116。舉例來說，第一通孔118從主動表面112到第一通孔118自身的頂表面測量可具有介於約20 μm到約25 μm範圍內的不同高度或相同高度。在示例性實施例中，第一通孔118包括晶種層118a及金屬層118b，且晶種層118a僅設置在金屬層118b的底部上。晶種層118a及金屬層118b的材料可包括例如銅、銅合金、或其他合適的材料選項。在一些實施例中，保護層120可為聚苯并噁唑（polybenzoxazole，PBO）層、聚醯亞胺（PI）層或其他合適的聚合物。在一些替代實施例中，保護層120可由無機材料製成。
在一些實施例中，第二晶片130包括主動表面132、分佈在主動表面132上的多個接墊134、覆蓋主動表面132的鈍化層136、以及多個第二通孔138。接墊134被鈍化層136局部地暴露出，且第二通孔138設置在接墊134上並電連接到接墊134。應注意，第二通孔138被暴露出。換句話說，與被第一晶片110的保護層120覆蓋的第一通孔118相比，第二晶片130的第二通孔138被暴露出而未被覆蓋。在示例性實施例中，第二通孔138包括晶種層138a及金屬層138b，且晶種層138a僅設置在金屬層138b的底部上。在一些實施例中，舉例來說，第二通孔138從主動表面132到第二通孔138自身的頂表面測量可具有介於約20 μm到約25 μm範圍內的不同高度或相同高度。第二通孔138與第一通孔118可具有不同的或相同的高度。在一些實施例中，舉例來說，第二通孔138的頂表面高於第一通孔118的頂表面。如圖1B所示，第一晶片110的頂表面及第二晶片130的頂表面低於層間穿孔102的頂表面。然而，本公開並非僅限於此。在一些替代實施例中，第一晶片110的頂表面及第二晶片130的頂表面可高於層間穿孔102的頂表面或與層間穿孔102的頂表面實質上共面。
參照圖1C，在載板C之上形成模塑化合物140以包封層間穿孔102以及第一晶片110及第二晶片130。在一些實施例中，模塑化合物140是通過模塑製程形成。層間穿孔102、第一晶片110的保護層120、及第二晶片130的第二通孔138被模塑化合物140包封。換句話說，層間穿孔102、第一晶片110的保護層120、及第二晶片130的第二通孔138未被顯露出，且得到模塑化合物140的良好保護。在一些實施例中，模塑化合物140可包含環氧樹脂（epoxy）或其他合適的材料。在示例性實施例中，模塑化合物140可包含不含有填料的材料。
參照圖1D，對模塑化合物140及第一晶片110的保護層120進行研磨直到暴露出第一通孔118的頂表面及第二通孔138的頂表面為止。在對模塑化合物140進行研磨之後，在黏合層103之上形成模塑層140’。在上述研磨製程期間，還對保護層120的一些部分進行了研磨以形成保護層120’。在一些實施例中，在模塑化合物140以及保護層120的上述研磨製程期間，對第一通孔118的一些部分、及第二通孔138的一些部分以及層間穿孔102的一些部分進行研磨直到暴露出第一通孔118的頂表面及第二通孔138的頂表面以及層間穿孔102的頂表面為止。換句話說，模塑層140’暴露出第一晶片110的至少一部分及第二晶片130的至少一部分以及層間穿孔102的至少一部分。在一些實施例中，模塑層140’可通過機械研磨、化學機械研磨（chemical mechanical polishing，CMP）、或另一種合適的機制形成。
模塑層140’包封第一晶片110的側壁及第二晶片130的側壁、保護層120’、及第二通孔138，且模塑層140’被層間穿孔102穿透。換句話說，第一晶片110、及第二晶片130、以及層間穿孔102嵌置在模塑層140’中。應注意，儘管第一晶片110、及第二晶片130、以及層間穿孔102嵌置在模塑層140’中，然而模塑層140’會暴露出第一晶片110的頂表面、及第二晶片130的頂表面、以及層間穿孔102的頂表面。換句話說，層間穿孔102的頂表面、保護層120’的頂表面、以及第一通孔118的頂表面及第二通孔138的頂表面與模塑層140’的頂表面實質上共面。另外，第二通孔138設置在模塑層140’中且與模塑層140’接觸，而第一通孔118設置在保護層120’中且與保護層120’接觸。
參照圖1E，在形成模塑層140’及保護層120’之後，與第一晶片110的第一通孔118及第二晶片130的第二通孔138、以及層間穿孔102電連接的重佈線層150形成在層間穿孔102的頂表面上、模塑層140’的頂表面上、第一通孔118的頂表面上及第二通孔138的頂表面上、以及保護層120’的頂表面上。如圖1E所示，重佈線層150包括交替堆疊的多個層間介電層152與多個重佈線導電圖案154。重佈線導電圖案154電連接到嵌置在保護層120’中的第一通孔118以及嵌置在模塑層140’中的第二通孔138及層間穿孔102。在一些實施例中，第一通孔118的頂表面及第二通孔138的頂表面、以及層間穿孔102的頂表面與重佈線層150的最底部重佈線導電圖案154接觸。第一通孔118的頂表面、及第二通孔138的頂表面以及層間穿孔102的頂表面被最底部層間介電層152局部地覆蓋。在示例性實施例中，重佈線導電圖案154包括晶種層154a及導電層154b，且晶種層154a設置在導電層154b的底部上。另外，最頂部重佈線導電圖案154包括多個接墊。在一些實施例中，上述接墊包括用於球安裝（ball mount）的多個球下金屬（under-ball metallurgy，UBM）圖案156a及/或用於安裝被動元件的至少一個連接接墊156b。球下金屬圖案156a及連接接墊156b的數目在本公開中並無限制。
參照圖1F，在形成重佈線層150之後，將多個導電端子160放置在球下金屬圖案156a上，且將多個被動元件162安裝在連接接墊156b上。在一些實施例中，可通過植球（ball placement）製程或其他合適的製程來將導電端子160放置在球下金屬圖案156a上且可通過焊接製程、回焊製程、或其他合適的製程將被動元件162安裝在連接接墊156b上。
參照圖1F及圖1G，在將導電端子160及被動組件162安裝在重佈線層150上之後，將圖1G所示結構從載板C剝離。也就是說，將載板C、剝離層DB、及黏合層103移除。在一些實施例中，可通過紫外雷射來對剝離層DB（例如，光熱轉換釋放層）進行照射。此處，實質上已完成集成扇出型（integrated fan-out，INFO）封裝10的形成。在一些實施例中，集成扇出型封裝10可與其他電子器件進行連接及/或堆疊。
圖2是繪示根據一些示例性實施例的半導體封裝的示意性剖視圖。在圖2中，闡述與圖1G所示結構相似的半導體封裝10，只是省略了層間穿孔。在半導體封裝10中，第二晶片130的第二通孔138設置在模塑層140’中且第二通孔138的頂表面與模塑層140’的經研磨的頂表面及第一晶片110的第一通孔118的頂表面實質上共面及齊平。
在一些實施例中，通過執行平坦化製程來消除第一晶片與第二晶片之間的厚度差異以及通孔與層間穿孔之間的高度差異。因此，可將具有不同厚度的晶片（例如，不同類型的晶片或來自不同供應商的晶片）放置在載板上以進行封裝。另外，第二通孔是在將第二基底黏合到載板之後被模塑層包封，而第一通孔是在將第一晶片黏合到載板之前被保護層包封。換句話說，第一晶片的第一通孔設置在保護層中且與保護層接觸，且第二晶片的第二通孔設置在模塑層中且與模塑層接觸。
圖3A至圖3I是根據一些示例性實施例的半導體封裝的製造方法中的各個階段的示意性剖視圖。在一些實施例中，繪示兩個晶片來代表多個晶片，且繪示一個或多個封裝來代表在半導體製造方法之後獲得的多個半導體封裝。與上述元件相似或實質上相同的元件將使用相同的參考編號，且本文中將不再重複相同元件的某些細節或說明。
參照圖3A，提供載板C。在一些實施例中，在載板C之上依序堆疊剝離層DB及介電層DI。在一些實施例中，介電層DI例如為聚合物，例如聚醯亞胺、苯環丁烷（BCB）、聚苯并噁唑（PBO）、或類似材料。在一些替代實施例中，介電層DI可包含非有機介電材料，例如氧化矽、氮化矽、碳化矽、氮氧化矽、或類似材料。然而，介電層DI的材料僅用於說明，且本公開並非僅限於此。
接著，在介電層DI之上設置層間穿孔102、具有第一黏合層104的第一晶片110、以及具有第二黏合層106的第二晶片130。在示例性實施例中，第一晶片110與第二晶片130具有不同的厚度t1、t2。然而，通過調整第一黏合層104的厚度t1’及第二黏合層106的厚度t2’，使第一晶片110與第一黏合層104的總厚度實質上等於第二晶片130與第二黏合層106的總厚度，例如，t1+t1’=t2+t2’。因此，第一晶片110的主動表面112與第二晶片130的主動表面132實質上共面。在一些實施例中，第一晶片110包括主動表面112、分佈在主動表面112上的多個接墊114、以及覆蓋主動表面112的鈍化層116。在一些實施例中，第二晶片130包括主動表面132、分佈在主動表面132上的多個接墊134、以及覆蓋主動表面132的鈍化層136。如圖3A所示，舉例來說，第一晶片110的頂表面及第二晶片130的頂表面低於層間穿孔102的頂表面。
參照圖3B，在載板C之上形成模塑層140a以包封第一晶片110及第二晶片130，且模塑層140a的頂表面不高於第一晶片110的主動表面112及第二晶片130的主動表面132。在一些實施例中，介電層DI上的第一晶片110及第二晶片130以及層間穿孔102的位於載板C之上的部分被包封在模塑層140a中。在一些實施例中，模塑層140a覆蓋介電層DI且填充在第一晶片110及第二晶片130與層間穿孔102之間。在示例性實施例中，模塑層140a是通過以下方式形成：使用內表面貼合有釋放膜（圖中未繪示）的模具（mold chase）（圖中未繪示）來覆蓋第一晶片110的主動表面112及第二晶片130的主動表面132以及層間穿孔102的頂部部分，但使第一晶片110的橫向側、及第二晶片130的橫向側以及層間穿孔102的底部部分暴露出。也就是說，模塑層140a的頂表面低於第一晶片110的主動表面112及第二晶片130的主動表面132且低於層間穿孔102的頂表面。在示例性實施例中，模塑層140a的頂表面因來自釋放膜的壓力而具有碟狀凹陷。在示例性實施例中，模塑層140a的材料包括至少一種類型的含填料樹脂且所述樹脂可為環氧樹脂、酚醛樹脂、或含矽樹脂。在示例性實施例中，所述填料由非熔融無機材料製成，且所述填料包括平均粒徑（particle size）介於約3 μm到約20 μm範圍內、約10 μm到約20 μm範圍內、或者介於約15 μm到約20 μm範圍內的金屬氧化物粒子、二氧化矽粒子、或矽酸鹽粒子。已固化模塑化合物的表面粗糙度或表面平坦度根據在模塑化合物材料中添加了細填料粒子還是粗填料粒子而異。如果對模塑化合物執行平坦化製程，則可能會因移除填料而在模塑化合物中形成一些凹坑，從而造成相對大的表面粗糙度、或甚至不平整度及可能的連接故障。在一些實施例中，模塑層140a是在不執行平坦化製程的條件下形成的。
參照圖3C，分別在第一晶片110的主動表面112及第二晶片130的主動表面132之上形成第一通孔118及第二通孔138。如圖3C所示，模塑層140a不覆蓋層間穿孔102從模塑層140a暴露出的頂部部分。也就是說，第一通孔118及第二通孔138、以及層間穿孔102的頂部部分從模塑層140a的頂表面突出。在示例性實施例中，舉例來說，第一通孔118及第二通孔138具有晶種層118a、138a以及金屬層118b、138b。第一通孔118及第二通孔138可以如下方式形成。首先，在鈍化層116、126之上形成晶種層，且在鈍化層116、126之上形成具有開口的罩幕，所述開口暴露出晶種層的一部分。晶種層的材料可包括例如銅、銅合金、或其他合適的材料選項。在一些實施例中，晶種層可通過物理氣相沉積或其他可適用的方法形成。接著，將金屬材料填充到罩幕的開口中，從而形成金屬層118b、138b。在一些實施例中，所述金屬材料可通過鍍覆製程形成。所述鍍覆製程例如為電鍍、無電鍍覆、浸鍍等。金屬材料例如為銅、銅合金、或類似材料。晶種層與金屬材料可包含相同的材料。然後，移除罩幕，且對晶種層進行圖案化以形成晶種層118a、138a。在一些實施例中，晶種層118a、138a僅設置在金屬層118b、138b的底部上，且在金屬層118b、138b的側壁上未設置有晶種層。在一些替代實施例中，可省略晶種層，第一通孔118及第二通孔138可通過其他合適的方法形成。
參照圖3D，在模塑層140a上形成。介電層142與下伏的元件及模塑層140a共形地形成。換句話說，介電層142的頂表面不是平面。介電層142的材料不同於模塑層140a的材料，且介電層142不含填料。如圖3D所示，介電層142形成在模塑層140a、第一晶片110的主動表面112及第二晶片130的主動表面132、以及第一通孔118、及第二通孔138以及層間穿孔102的從模塑層140a暴露出的頂部部分之上，使得整體的層間穿孔102、第一晶片110及第二晶片130以及第一通孔118及第二通孔138共同地被模塑層140a及介電層142包封。在一些實施例中，第一通孔118及第二通孔138、以及層間穿孔102的頂部部分被介電層142包封。也就是說，介電層142的頂表面高於層間穿孔102的頂表面且高於第一通孔118的頂表面及第二通孔138的頂表面。在一些實施例中，舉例來說，介電層142的厚度（從模塑層140a的頂表面到介電層142的頂表面測量）介於約10 μm到約15 μm範圍內。在示例性實施例中，介電層142的材料包括無填料的聚合材料，且所述聚合材料選自低溫可固化聚醯亞胺（PI）材料、高溫可固化聚醯亞胺（PI）材料、感光性乾膜材料或非感光性乾膜材料、環氧樹脂、苯環丁烷、聚苯并噁唑、或任何其他適合的介電材料。在一些實施例中，介電層142是通過塗布製程、沉積製程或其他可適用的方法形成。
參照圖3E，在一些實施例中，對介電層142執行平坦化製程以形成介電層142’，以使得介電層142的一些部分及層間穿孔102的一些部分被移除，且使得第一晶片110的第一通孔118及第二晶片130的第二通孔138從介電層142’暴露出。作為另外一種選擇，在一個實施例中，也可移除第一通孔118的一些部分及第二通孔138的一些部分。在一些實施例中，在平坦化之後，介電層142’具有平面頂表面，且第一通孔118及第二通孔138、層間穿孔102、以及介電層142’變得平坦且實質上齊整（即，第一通孔118的頂表面及第二通孔138的頂表面以及層間穿孔102的頂表面與介電層142’的經研磨頂表面實質上共面且齊平）。在一些實施例中，用於將介電層142及層間穿孔102平坦化的平坦化製程包括飛切（fly cut）製程、研磨製程、或化學機械研磨（“CMP”）製程。在一些實施例中，舉例來說，平面介電層142’的厚度（從模塑層140a的平面頂表面到介電層142’的平面頂表面測量）介於約5 μm到約10 μm範圍內。第一通孔118及第二通孔138、以及層間穿孔102從平面介電層142’的頂表面暴露出以進一步進行連接。平面介電層142’與模塑層140a構成複合模塑化合物。由於介電層142’的材料不含填料且具有更好的流動性（flow ability），因而介電層142’可在下伏元件及模塑層140a之上提供更好的覆蓋與填充能力，從而使模塑層140a與介電層142’的複合結構得到更好的表面平坦度以及結構完整性與強度。
參照圖3F，在一些實施例中，形成與第一晶片110的第一通孔118及第二晶片130的第二通孔138、以及層間穿孔102電連接的重佈線層150。
參照圖3G，在一些實施例中，在形成重佈線層150之後，將多個導電端子160放置在球下金屬圖案156a上，且將多個被動元件162安裝在連接接墊156b上。
參照圖3H，在將導電端子160及被動組件162安裝在重佈線層150上之後，將形成在模塑層140a的底表面上的介電層DI從剝離層DB剝離以使得介電層DI與載板C分離。接著，將多個導電端子164放置在接觸開口中，且形成多個接觸開口O來局部地暴露出層間穿孔102。在一些實施例中，可通過紫外雷射來照射剝離層DB（例如，光熱轉換釋放層），以使得將黏合在模塑層140a的底表面上的介電層DI從載板C剝落。如圖3H所示，接著將介電層DI圖案化，以使得形成多個接觸開口O來局部地暴露出層間穿孔102。接觸開口O的數目對應於層間穿孔102的數目。在一些實施例中，介電層DI的接觸開口O是通過雷射鑽孔製程（laser drilling process）、機械鑽孔製程（mechanical drilling process）、或其他合適的製程形成。
參照圖3I，在介電層DI中形成接觸開口O之後，將多個導電端子164放置在接觸開口O中，且將導電端子164電連接到層間穿孔102。此處，實質上已完成集成扇出型（INFO）封裝10的形成。在一些實施例中，集成扇出型封裝10可與其他電子器件進行堆疊。舉例來說，提供另一封裝（例如，積體電路（integrated circuit，IC）封裝），且通過導電端子164將所述封裝堆疊在集成扇出型封裝10之上並電連接到集成扇出型封裝10以使得製作出疊層封裝（package-on-package，PoP）結構。
圖4是繪示根據一些示例性實施例的半導體封裝的示意性剖視圖。在圖4中，闡述與圖3I所示結構相似的半導體封裝10，只是省略了層間穿孔。在一些實施例中，第一晶片110及第二晶片130在與主動表面112、132相對的表面上具有接墊122、124，接觸開口O被形成為局部地暴露出接墊122、124，且導電端子164被放置在與接墊122、124對應的接觸開口O中。
圖5A至圖5F是根據本公開的一些示例性實施例的半導體封裝的製造方法中的各個階段的示意性剖視圖。圖3C至圖3I的方法與圖5A至圖5F的方法之間的差異在於第一通孔及第二通孔的形成方法。以下詳細繪示所述差異，且本文中不再對相似之處進行重複說明。
參照圖5A，提供圖3B所示結構，且在模塑層140a上形成具有開口144的介電層142，且第一晶片110的接墊114的一些部分及第二晶片130的接墊134的一些部分被開口144暴露出。在一些實施例中，介電層142可通過物理氣相沉積或其他可適用的方法形成，且開口144通過微影製程及蝕刻製程形成。介電層142與下伏的元件及模塑層140a實質上共形地形成，且因此介電層142的頂表面不是平面。在一些實施例中，介電層142的頂表面高於層間穿孔102的頂表面，且因此層間穿孔102被包封在介電層142及模塑層140a中。介電層142的形成方法、材料及厚度與圖3D所闡述的介電層142的形成方法、材料及厚度相似。
參照圖5B，在介電層142上形成導電層148且導電層148填充在開口144中。在一些實施例中，導電層148通過以下方法形成：在介電層142的頂表面上以及開口144的側壁及底部上形成晶種層148a；以及接著在晶種層148a上形成金屬層148b並填充開口144。晶種層148a及金屬層148b的形成方法及材料與圖3C所闡述的晶種層及金屬層的形成方法及材料相似。
參照圖5C，對介電層142及導電層148執行平坦化製程以形成介電層142’及在介電層142’中形成第一通孔118及第二通孔138。在一些實施例中，用於將介電層142、層間穿孔102、及導電層148平坦化的平坦化製程包括飛切製程、研磨製程、或化學機械研磨（“CMP”）製程。在一些實施例中，第一通孔118包括晶種層118a及金屬層118b，且第二通孔138包括晶種層138a及金屬層138b。在一些實施例中，在平坦化之後，介電層142’具有平面頂表面，且第一通孔118及第二通孔138、層間穿孔102、以及介電層142’變得平坦且實質上齊整（即，第一通孔118的頂表面及第二通孔138的頂表面以及層間穿孔102的頂表面與介電層142’的經研磨頂表面實質上共面且齊平）。
參照圖5D，在一些實施例中，形成與第一晶片110的第一通孔118及第二晶片130的第二通孔138、以及層間穿孔102電連接的重佈線層150。在形成重佈線層150之後，將多個導電端子160放置在球下金屬圖案156a上，且將多個被動元件162安裝在連接接墊156b上。
參照圖5E，將形成在模塑層140a的底表面上的介電層DI從剝離層DB剝離以使得介電層DI與載板C分離。接著，將多個導電端子164放置在接觸開口中，且形成多個接觸開口O來局部地暴露出層間穿孔102。
參照圖5F，將多個導電端子164放置在接觸開口O中，且將導電端子164電連接到層間穿孔102。此處，實質上已完成集成扇出型（INFO）封裝10的形成。
圖6是繪示根據一些示例性實施例的半導體封裝的示意性剖視圖。在圖6中，闡述與圖5F所示結構相似的半導體封裝10，只是省略了層間穿孔。在一些實施例中，第一晶片110及第二晶片130在與主動表面112、132相對的表面上具有接墊122、124，接觸開口O被形成為局部地暴露出接墊122、124，且導電端子164被放置在接觸開口O中。另外，在一些實施例中，介電層142’被用作重佈線層150的最底部層間介電層，且因此可無需額外地形成最底部層間介電層，這會減少半導體封裝的製程及成本。
在一些實施例中，各晶片之間的厚度差異通過增加具有不同厚度的黏合層而得到補償。因此，可將不同類型的晶片放置在載板上以進行封裝。在一些實施例中，模塑層被形成為使其頂表面不高於晶片的主動表面，即，模塑層並非是通過包覆模塑（over-molding）技術來形成。因此，不需要對模塑層進行平坦化製程，且防止出現因對包含填料的模塑層執行平坦化製程而引起的凹坑問題。另外，在模塑層之上形成介電層並將所述介電層平坦化，以提供更好的平面表面，此有益於稍後在所述介電層上形成金屬線或配線、尤其是對於具有精細的線/空間（line/space）的金屬線來說。另外，所述介電層為晶片的通孔提供絕緣，且因此，晶片的通孔不需要鈍化層。換句話說，形成模塑層及覆蓋所述模塑層的介電層會在材料選擇方面提供靈活性、為模塑層提供更大的製程裕度、並且提高具有精細的線/空間的重佈線層的可靠性、且使製造方法簡單。因此，可降低半導體封裝的成本，且可提高半導體封裝的性能。
根據一些實施例，一種半導體封裝包括第一晶片、第二晶片及模塑化合物。所述第一晶片上具有至少一個第一通孔及保護層，且所述至少一個第一通孔形成在所述保護層中。所述第二晶片上具有至少一個第二通孔。所述模塑層包封所述第一晶片及所述第二晶片。所述至少一個第二通孔設置在所述模塑層中且與所述模塑層接觸，且所述保護層的頂表面、所述至少一個第一通孔的頂表面及所述至少一個第二通孔的頂表面與所述模塑層的頂表面實質上共面。
在一些實施例中，還包括重佈線層，所述重佈線層設置在所述模塑層之上且電連接到所述至少一個第一通孔及所述至少一個第二通孔。
在一些實施例中，所述第一晶片的厚度不同於所述第二晶片的厚度。
在一些實施例中，所述模塑層包含不含有填料的材料。
在一些實施例中，所述模塑層設置在所述至少一個第二通孔之間。
根據一些實施例，一種半導體封裝包括第一晶片、模塑層、及介電層。所述第一晶片上具有至少一個第一通孔，所述至少一個第一通孔包括晶種層及導電層，且所述晶種層沿所述導電層的側壁及底部設置。所述模塑層包封所述第一晶片，且所述模塑層的頂表面不高於所述第一晶片的主動表面。介電層位於所述模塑層之上，且所述至少一個第一通孔設置在所述介電層中。
在一些實施例中，還包括第二晶片，所述第二晶片上具有至少一個第二通孔，其中所述至少一個第二通孔設置在所述介電層中。
在一些實施例中，所述至少一個第二通孔包括導電層及沿所述導電層的側壁及底部設置的晶種層。
在一些實施例中，所述介電層設置在所述至少一個第一通孔與所述至少一個第二通孔之間。
在一些實施例中，所述第一晶片的厚度不同於所述第二晶片的厚度。
在一些實施例中，所述介電層具有平面表面。
在一些實施例中，所述模塑層的所述頂表面與所述第一晶片的所述主動表面實質上齊平。
在一些實施例中，所述模塑層的所述頂表面具有碟狀凹陷。
在一些實施例中，還包括重佈線層，所述重佈線層位於所述介電層之上且電連接到所述至少一個第一通孔。
根據一些實施例，一種半導體封裝的製造方法包括至少以下步驟。在載板上提供具有第一黏合層的第一晶片及具有第二黏合層的第二晶片，且所述第一晶片的主動表面與所述第二晶片的主動表面實質上共面。形成模塑層以包封所述第一晶片及所述第二晶片，且所述模塑層的頂表面不高於所述第一晶片的所述主動表面及所述第二晶片的所述主動表面。在所述模塑層之上的介電層中形成至少一個第一通孔及至少一個第二通孔。所述至少一個第一通孔及所述至少一個第二通孔分別設置在所述第一晶片及所述第二晶片上，且所述介電層的頂表面、所述至少一個第一通孔的頂表面及所述至少一個第二通孔的頂表面實質上共面。
在一些實施例中，所述形成所述至少一個第一通孔、所述至少一個第二通孔及所述介電層的步驟包括：分別在所述第一晶片及所述第二晶片上形成所述至少一個第一通孔及所述至少一個第二通孔；在所述模塑層之上形成所述介電層，以覆蓋所述至少一個第一通孔及所述至少一個第二通孔；以及執行平坦化製程，以移除所述介電層的一部分來暴露出所述至少一個第一通孔的頂表面及所述至少一個第二通孔的頂表面。
在一些實施例中，所述形成所述至少一個第一通孔及所述至少一個第二通孔以及所述介電層的步驟包括：在所述模塑層之上形成所述介電層；在所述介電層中形成多個開口；在所述介電層之上形成導電層，所述導電層填充所述開口；以及執行平坦化製程，以移除所述導電層的部分以及所述介電層的部分，從而形成設置在所述介電層中的所述至少一個第一通孔及所述至少一個第二通孔。
在一些實施例中，所述形成所述導電層的步驟包括：在所述介電層之上形成晶種層，其中所述晶種層形成在所述開口中的每一開口的側壁及底部上；以及從所述晶種層形成金屬層。
在一些實施例中，還包括：在所述介電層之上形成重佈線層，以分別電連接到所述至少一個第一通孔及所述至少一個第二通孔。
在一些實施例中，所述模塑層包含具有填料的材料。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開內容的各個方面。所屬領域中的技術人員應知，其可容易地使用本公開內容作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開內容的精神及範圍，而且他們可在不背離本公開內容的精神及範圍的條件下對其作出各種改變、代替、及變更。
10:封裝 102:層間穿孔 103:黏合層 104:第一黏合層 106:第二黏合層 110:第一晶片 112、132:主動表面 114、122、124、134:接墊 116、136:鈍化層 118:第一通孔 118a、138a、148a、154a:晶種層 118b、138b、148b:金屬層 120、120’:保護層 130:第二晶片 138:第二通孔 140:模塑化合物 140’、140a:模塑層 142、DI:介電層 142’:介電層 144:開口 148、154b:導電層 150:重佈線層 152:層間介電層 154:重佈線導電圖案 156a:球下金屬圖案 156b:連接接墊 160、164:導電端子 162:被動組件 C:載板 DB:剝離層 O:接觸開口 t1、t1’、t2、t2’:厚度
結合附圖閱讀以下詳細說明，會最好地理解本公開的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1A至圖1G是根據一些示例性實施例的半導體封裝的製造方法中的各個階段的示意性剖視圖。 圖2是繪示根據一些示例性實施例的半導體封裝的示意性剖視圖。 圖3A至圖3I是根據一些示例性實施例的半導體封裝的製造方法中的各個階段的示意性剖視圖。 圖4是繪示根據一些示例性實施例的半導體封裝的示意性剖視圖。 圖5A至圖5F是根據本公開一些示例性實施例的半導體封裝的製造方法中的各個階段的示意性剖視圖。 圖6是繪示根據一些示例性實施例的半導體封裝的示意性剖視圖。
10:封裝
102:層間穿孔
104:第一黏合層
106:第二黏合層
110:第一晶片
112、132:主動表面
114、134:接墊
116、136:鈍化層
118:第一通孔
130:第二晶片
138:第二通孔
140a:模塑層
142’:介電層
150:重佈線層
152:層間介電層
154:重佈線導電圖案
154a:晶種層
154b:導電層
156a:球下金屬圖案
156b:連接接墊
160、164:導電端子
162:被動組件
DI:介電層

Claims (10)

  1. 一種半導體封裝，包括：第一晶片及第二晶片；在所述第一晶片的第一表面上的第一晶粒貼合膜及在所述第二晶片的第二表面上的第二晶粒貼合膜，其中所述第一晶粒貼合膜及所述第二晶粒貼合膜的厚度不同，且所述第一晶片與所述第一晶粒貼合膜的總厚度實質上等於所述第二晶片與所述第二晶粒貼合膜的總厚度；以及模塑層，包封所述第一晶片、所述第二晶片、所述第一晶粒貼合膜及所述第二晶粒貼合膜。
  2. 如請求項1所述的半導體封裝，其中所述第一晶片包括與所述第一表面相對的第一主動表面，所述第二晶片包括與所述第二表面相對的第二主動表面，且所述第一主動表面與所述第二主動表面實質上齊平。
  3. 如請求項1所述的半導體封裝，還包括位於所述模塑層之上的介電層，其中所述第一晶片包括在所述介電層中的第一通孔，所述第二晶片包括在所述介電層中的第二通孔，所述介電層、所述第一通孔及所述第二通孔的頂表面實質上共面。
  4. 如請求項1所述的半導體封裝，其中所述模塑層的厚度實質上等於所述第一晶片與所述第一晶粒貼合膜的所述總厚度。
  5. 如請求項1所述的半導體封裝，其中所述模塑層的頂表面具有碟狀凹陷。
  6. 如請求項1所述的半導體封裝，其中所述模塑層包含具有填料的材料。
  7. 一種半導體封裝，包括：第一晶片，具有突出於所述第一晶片的第一通孔；第二晶片，具有突出於所述第二晶片的第二通孔，其中所述第一晶片的厚度不同於所述第二晶片的厚度；以及模塑化合物，包封所述第一晶片、所述第二晶片、所述第一通孔以及所述第二通孔，其中所述第一通孔、所述第二通孔以及所述模塑化合物的表面實質上共面且所述第一通孔與所述第二通孔中的至少一者與所述模塑化合物直接接觸。
  8. 如請求項7所述的半導體封裝，其中所述第一晶片及所述第一通孔的總厚度實質上等於所述第二晶片及所述第二通孔的總厚度。
  9. 一種半導體封裝，包括：第一晶片，具有由所述第一晶片延伸的第一通孔；第二晶片，具有由所述第二晶片延伸的第二通孔，其中所述第一通孔的延伸部分的高度不同於所述第二通孔的延伸部分的高度；以及模塑化合物，包封所述第一晶片、所述第二晶片、所述第一通孔以及所述第二通孔，其中所述第一通孔與所述第二通孔中的至少一者與所述模塑化合物直接接觸。
  10. 一種半導體封裝，包括：第一晶片，具有第一電性連接件； 第二晶片，具有第二電性連接件；模塑化合物，其中所述模塑化合物的表面、所述第一電性連接件以及所述第二電性連接件的表面實質上共面，且所述第一電性連接件以及所述第二電性連接件中的至少一者與所述模塑化合物分開。
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