TWI754586B - 電子封裝件及其製法 - Google Patents
電子封裝件及其製法 Download PDFInfo
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Abstract
一種電子封裝件,係將外表面配置有導電層之電子元件嵌埋於包覆層中,該電子元件之作用面係具有至少一電極墊,且該電子元件之內部係配置有至少一電性連接該電極墊之導線,以令該導電層電性連接該導線,使該電極墊、導線與導電層作為電力傳輸結構,俾藉由該電力傳輸結構作為電流路徑,以降低直流電阻,並改善電流供應所產生之阻抗問題。
Description
本發明係有關一種半導體封裝製程,尤指一種可供應電源之電子封裝件及其製法。
為了確保電子產品和通信設備的持續小型化和多功能性,半導體封裝需朝尺寸微小化發展,以利於多引腳之連接,且高速操作並具有高功能性。例如,於先進製程封裝中,常用的封裝型式如2.5D封裝製程、扇出(Fan-Out)佈線配合嵌埋橋接(Embedded Bridge)元件之製程(簡稱FO-EB)等,且FO-EB相對於2.5D封裝製程係具有低成本及材料供應商多等優勢。
圖1係習知FO-EB之半導體封裝件1之剖面示意圖。該半導體封裝件1係於一具有線路層101之基板結構10上設置第一半導體晶片11與複數導電柱13,再以一包覆層15包覆該半導體晶片11與該些導電柱13,之後於該包覆層15上形成一電性連接該第一半導體晶片11與該些導電柱13之佈線結構16,以於該佈線結構16上設置複數電性連接該佈線結構16之第二半導體晶片14,並以一封裝層18包覆該些第二半導體晶片14,其中,該線路層101與該佈線結構16係採用扇出型重佈線路層(redistribution layer,簡稱RDL)之規格,且該第一半導體晶片
11係作為嵌埋於該包覆層15中之橋接元件,以電性橋接兩相鄰之第二半導體晶片14。
習知半導體封裝件1中,係以該基板結構10藉由複數銲球12接置於一電路板1a上,且該些導電柱13係電性連接該線路層101,以令其中一部分之導電柱13配合該線路層101與該佈線結構16作為電力傳輸結構,使該電路板1a藉由該線路層101與導電柱13提供遠離該電路板1a之第二半導體晶片14所需的電力。
然而,習知半導體封裝件1中,對於該佈線結構16上方之電子元件而言,越靠近該第一半導體晶片11之中央處,所產生的直流電阻越大,致使電源供應能力較差,即電力傳輸路徑過長,導致阻抗增加(如圖2F所示之阻抗曲線L2),故該佈線結構16上方之部分電子元件往往會發生電力不足之問題,甚至於斷電之情況。例如,該佈線結構16上方之右側第二半導體晶片14,其電源接點17係位於該第一半導體晶片11之中央處之接點110之上方,且該電路板1a之電源供應埠係將電力透過該線路層101與圖1中之右側導電柱13經由該佈線結構16傳輸至該電源接點17,故此電力傳輸路徑極長,導致阻抗過大,致使該佈線結構16上方之右側第二半導體晶片14容易發生斷電之情況。
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失,本發明係提供一種電子封裝件,係包括:包覆層;第一電子元件,係嵌埋於該包覆層中,其中,該第一電子元件
係具有相對之作用面與非作用面及鄰接該作用面與非作用面之側面,該作用面係具有至少一電極墊,且該第一電子元件之內部係配置有至少一電性連接該電極墊之導線;以及導電層,係形成於該第一電子元件之表面上並嵌埋於該包覆層中且電性連接該導線,其中,該導電層未形成於該電極墊上。
本發明亦提供一種電子封裝件之製法,係包括:提供表面具有導電層之第一電子元件,其中,該第一電子元件係具有相對之作用面與非作用面及鄰接該作用面與非作用面之側面,該作用面係具有至少一電極墊,且該第一電子元件之內部係配置有至少一電性連接該電極墊之導線,以令該導電層電性連接該導線,且該導電層未形成於該電極墊上;以及將該第一電子元件連同該導電層一併嵌埋於包覆層中。
前述之電子封裝件及其製法中,該電極墊係位於該作用面之中間處。
前述之電子封裝件及其製法中,該導線係外露於該第一電子元件之側面及/或該非作用面,以接觸該導電層。
前述之電子封裝件及其製法中,該導電層係形成於該第一電子元件之非作用面及/或該側面上。
前述之電子封裝件及其製法中,復包括形成佈線結構於該包覆層上,且該佈線結構係電性連接該電極墊。例如,該佈線結構係具有相對之第一表面與第二表面,以令該包覆層與該第一電子元件配置於該第一表面上,且於該第二表面上配置至少一電性連接該佈線結構之第二電子元件。進一步,該佈線結構之第二表面上係配置複數該第二電子元件,以令該第一電子元件電性橋接複數該第二電子元件之其中二者。
前述之電子封裝件及其製法中,復包括於該包覆層中嵌埋導電柱。例如,復包括形成複數導電元件於該包覆層上,且該複數導電元件係電性連接該導電層與該導電柱。
前述之電子封裝件及其製法中,復包括形成複數導電元件於該包覆層上,且該複數導電元件係電性連接該導電層。
前述之電子封裝件及其製法中,該第一電子元件之內部係配置有複數相互分開而不相連之該導線,且於該第一電子元件上形成有複數相互分開而不相連之該導電層,以令該複數導線分別電性連接不同之該導電層。
由上可知,本發明之電子封裝件及其製法中,主要藉由該導電層形成於該第一電子元件上且電性連接該導線之設計,以令該電極墊、導線與導電層作為電力傳輸結構,故相較於習知技術,本發明之電子封裝件除了導電柱作為電流路徑外,更有其它條由該電極墊、導線與導電層所組成之電流路徑,以降低該電子封裝件之直流電阻,因而能改善電流供應所產生之阻抗問題。
1:半導體封裝件
1a:電路板
10:基板結構
101:線路層
11:第一半導體晶片
110,210a,300a:接點
12:銲球
13,23:導電柱
14:第二半導體晶片
15,25:包覆層
16,26:佈線結構
17:電源接點
18,28:封裝層
2,4:電子封裝件
20:承載結構
20a:第一側
20b:第二側
200:第一介電層
201:第一線路層
21,30:第一電子元件
21a,30a:作用面
21b,30b:非作用面
21c,30c:側面
210,300:電極墊
211,301,410,411,412:導線
212:導電體
213:絕緣保護膜
22,32,42:導電層
22a,42a:第一導電層
22b,42b:第二導電層
24,44:第二電子元件
26a:第一表面
26b:第二表面
260:第二介電層
261:第二線路層
27:導電凸塊
29:導電元件
3:電子模組
40a:第一連接部
40b:第二連接部
5:晶圓
7:電子裝置
70,71:電源供應埠
8,9:承載件
90:板體
91:結合層
L,S:切割路徑
圖1係為習知半導體封裝件之剖面示意圖。
圖1-1係為圖1之第一半導體晶片之局部上視示意圖。
圖2A至圖2E係為本發明之電子封裝件之第一實施例之製法之剖視示意圖。
圖2E-1係為圖2E之另一態樣之剖視示意圖。
圖2F係為本發明之電子封裝件與習知半導體封裝件之阻抗分佈之曲線示意圖。
圖2F-1係為圖2E之第一電子元件之局部上視示意圖。
圖3A至圖3D係為本發明之電子封裝件之電子模組之製法之剖視示意圖。
圖4A及圖4B係為本發明之電子封裝件之第二實施例之剖視示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
圖2A至圖2E係為本發明之電子封裝件2之第一實施例之製法的剖面示意圖。於本實施例中,該電子封裝件2之製法係採用FO-EB方式。
如圖2A所示,提供一個表面具有導電層22之第一電子元件21,再將該第一電子元件21設於一結合於承載件9上之承載結構20上,且該承載結構20係具有相對之第一側20a與第二側20b,以令該第一電子元件21設於該承載結構20之第一側20a上,且該承載結構20之第一側20a上係設置有複數導電柱23(如以
銅之金屬材或銲錫材製作)。另外,於一實施態樣中,亦可先將具有導電層22之第一電子元件21設於該承載結構20之第一側20a上,再結合至承載件9上。
於本實施例中,該承載結構20係例如為具有核心層與線路結構之封裝基板、無核心層(coreless)形式線路結構之封裝基板、具導電矽穿孔(Through-silicon via,簡稱TSV)之矽中介板(Through Silicon interposer,簡稱TSI)或其它板型,其包含至少一第一介電層200及至少一結合該第一介電層200之第一線路層201,如至少一扇出(fan out)型重佈線路層(redistribution layer,簡稱RDL)。例如,形成該第一線路層201之材質係為銅,且形成該第一介電層200之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)之介電材。應可理解地,該承載結構20亦可為其它承載晶片之基材,如導線架(lead frame)、晶圓(wafer)、或其它具有金屬佈線(routing)之板體等,並不限於上述。
再者,該承載結構20之第二側20a係藉由複數如銲球或其它金屬凸塊(如銅柱)之導電元件29接置於該承載件9上。例如,該承載件9係包含如半導體材、介電材、陶瓷材、玻璃或金屬材之板體90,但不限於此,且該承載件9之尺寸可依需求選擇晶圓型基板(Wafer form substrate)或一般整版面型基板(Panel form substrate),並可藉由如離型膜或膠材之結合層91,其以塗佈或貼合方式形成於該板體90上,使該承載結構20壓合於該結合層91上,且令該些導電元件29嵌埋於該結合層91中。
又,該第一電子元件21係為主動元件、被動元件或其組合者,其中,該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。於本實施例中,該第一電子元件21係為半導體晶片,其具有相對之作用面21a與非作用面21b及鄰接該作用面21a與非作用面21b之側面21c,該第一電子元件21係以其非作用面21b設於該承載結構20之第一側20a上,而該作用面21a具有至少一電極墊210(其作為電源接腳埠口,且可配置於該作用面21a之中間處)及複數接點
210a(其作為訊號接腳埠口,且可配置於該作用面21a之任意處,如外圍處或中間處),其中,該第一電子元件21之內部係配置有至少一電性連接該電極墊210之導線211及複數電性連接該接點210a之積體電路(圖未示),且該導線211外露於該第一電子元件21之側面21c(如圖2A所示)或非作用面21b(如圖2E-1所示之導線411)。例如,於該電極墊210及該些接點210a上係形成有如柱狀、針狀或其它凸塊狀之導電體212,並於該作用面21a上形成有一絕緣保護膜213,以令該導電體212外露於該絕緣保護膜213。
另外,該導電層22係形成於該第一電子元件21之非作用面21b與側面21c上,以令該第一電子元件21藉由該導電層22設於該承載結構20之第一側20a上,且該導電層22係電性連接該第一線路層201,以令該導電層22與該導線211作為一電力傳輸結構。例如,形成該導電層22之材質係為銅,其鍍覆厚度約5微米(um)。應可理解地,若該導線411外露於該第一電子元件21之非作用面21b,則該導電層42可僅形成於該第一電子元件21之非作用面21b上(如圖2E-1所示)。
如圖2B所示,形成一包覆層25於該承載結構20之第一側20a上,以令該包覆層25包覆該第一電子元件21、該導電層22與該些導電柱23。接著,形成一佈線結構26於該包覆層25上,以令該佈線結構26電性連接該些導電柱23與該些導電體212。
於本實施例中,形成該包覆層25之材質係為聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、環氧樹脂(epoxy)或封裝材(molding compound)等絕緣材,但並不限於上述。例如,可採用壓合(lamination)或模壓(molding)等方式將該包覆層25形成於該承載結構20之第一側20a上。
再者,可依需求進行整平製程,以令該包覆層25之上表面齊平該導電柱23之端面、該絕緣保護膜213之表面與該導電體212之頂面,使該導電柱23之端面、該絕緣保護膜213之表面與該導電體212之頂面外露出該包覆層25。例
如,可藉由研磨方式進行該整平製程,以移除該導電柱23之部分材質、該絕緣保護膜213之部分材質、該導電體212之部分材質與該包覆層25之部分材質。
又,該佈線結構26係具有相對之第一表面26a與第二表面26b,以令該佈線結構26以其第一表面26a結合該包覆層25,使該第一電子元件21與該些導電柱23配置於該第一表面26a上。
另外,該佈線結構26係具有至少一第二介電層260及設於該第二介電層260上之複數第二線路層261(如RDL),以令該佈線結構26之第二線路層261電性連接該些導電柱23,且藉由該些導電體212電性連接該電極墊210與該些接點210a。例如,形成該第二線路層261之材質係為銅,且形成該第二介電層260之材質係為如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)之介電材。
如圖2C所示,設置複數第二電子元件24於該佈線結構26之第二表面26b上,再以一封裝層28包覆該第二電子元件24。
於本實施例中,該第二電子元件24係為主動元件、被動元件或其二者組合,且該主動元件係例如半導體晶片,而該被動元件係例如電阻、電容及電感。例如,該第二電子元件24係以覆晶方式藉由複數如銲錫凸塊、銅凸塊或其它等之導電凸塊27電性連接該佈線結構26之第二線路層261,使該第一電子元件21成為嵌埋於該包覆層25中之橋接元件,以藉由該些電極墊210電性橋接兩相鄰之第二電子元件24;然而,有關該第二電子元件24連接該佈線結構26之方式繁多,如打線封裝方式,並不限於上述。
再者,該封裝層28可同時包覆該第二電子元件24與該些導電凸塊27。或者,亦可先形成底膠(圖略)於該第二電子元件24與該佈線結構26之第二表面26b之間以包覆該些導電凸塊27,再形成該封裝層28以包覆該底膠與該第二電子元件24。
又,該封裝層28係為絕緣材,如聚醯亞胺(polyimide,簡稱PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound),其可用壓合(lamination)或模壓(molding)之方式形成於該佈線結構26上。應可理解地,形成該封裝層28之材質可相同或不相同該包覆層25之材質。
另外,該封裝層28可依需求包覆該第二電子元件24之晶背(圖未示)或外露該第二電子元件24之晶背(如圖2C所示)。
如圖2D所示,移除該承載件9及其上之結合層91,以外露出該複數導電元件29。
如圖2E所示,沿如圖2D所示之切割路徑S進行切單製程,以獲取複數電子封裝件2,以於後續製程中,各該電子封裝件2可藉由其導電元件29接置於一如電路板之電子裝置7上。
於本實施例中,該電子封裝件2之其中一部分之導電元件29(如圖2E所示之左側導電元件29)係對應連接該電子裝置7之電源供應埠70,71。例如,其中一部分電源供應埠70係電性連接該導電層22,而另一部分電源供應埠71係電性連接該導電柱23。應可理解地,該電子封裝件2之其它導電元件29(如圖2E所示之右側導電元件29)係對應連接該電子裝置7之訊號接點(圖略)。
因此,本發明之電子封裝件2主要藉由該第一電子元件21具有電極墊210、導線211,411與導電層22,42之設計,以令該電極墊210、導線211,411與導電層22,42作為電力傳輸結構,故相較於習知技術,本發明之電子封裝件2除了導電柱23作為電流路徑外,更有另一條由該電極墊210、導線211,411與導電層22,42所組成之電流路徑,以降低該電子封裝件2之直流電阻,因而能改善電流供應所產生之阻抗問題。
例如,習知第一半導體晶片11之接點110之分佈中,如圖1-1所示,靠近中間處之接點110(如圖2F所示之橫座標編號第24號),其所產生的直流電
阻極大(如圖2F阻抗曲線L2所示之阻抗值38.62毫歐姆)。相對地,本發明之第一電子元件21之接腳埠口之分佈中,如圖2F-1所示,靠近中間處之電極墊210(如圖2F所示之橫座標編號第24號),其所產生的直流電阻變小(如圖2F阻抗曲線L1所示之阻抗值17.73毫歐姆),其中,圖2F所示之縱軸係代表器件內部的工作電壓(VDD)所產生之電感內阻抗(DCR),橫軸係代表晶片作用面之接腳埠口之分佈(編號第1號係為外圍之接腳埠口,如接點110,210a,而編號第24號係為中間處之接腳埠口,如接點110或電極墊210)。
因此,由圖2F可知,本發明之電子封裝件2藉由新增一條電源供應迴路,即由該電極墊210、導線211,411與導電層22,42所組成之電流路徑,因而能大幅降低FO-EB型式封裝件之直流電阻(如圖2F所示之電子封裝件2之阻抗曲線L1遠低於習知半導體封裝件1之阻抗曲線L2,即該第一電子元件21之表面鍍覆約5微米厚之導電層22,42,即可改善54%DCR),以有效解決FO-EB之電子封裝件2之電源供應問題。
再者,因該電極墊210、導線211,411與導電層22,42可作為電流路徑,故可依電力需求省略該導電柱23之製作(或僅製作其它功能而非電源功能之導電柱)。
另外,有關FO-EB之流程繁多,並不限於上述。例如,可先將導電柱23與具有導電層22,42之第一電子元件21設置於承載件9上,待完成圖2B至圖2D之製程後,移除該承載件9,再形成該承載結構20及該導電元件29,亦可省略製作該承載結構20而直接形成電性連接該導電柱23與該導電層22,42之導電元件29。因此,本發明之電子封裝件2可依需求配置或省略該承載結構20。
圖3A至圖3D係為本發明之電子封裝件2之電子模組3(即配置有該導電層22之第一電子元件21)之製法的剖面示意圖。
如圖3A至圖3B所示,將一晶圓5進行切單製程,以獲取複數第一電子元件30。接著,將複數第一電子元件30間隔排設於一整版面承載件8上。
於本實施例中,該第一電子元件30係具有相對之作用面30a與非作用面30b,該作用面30a具有複數電極墊300及複數接點300a,且該第一電子元件30之內部係配置有複數電性連接該電極墊300之導線301,並以該作用面30a結合至該承載件8上。例如,於該電極墊300與該接點300a上係形成導電體212,並於該晶圓5之作用面30a上形成一絕緣保護膜213以包覆該些導電體212,以令該晶圓5以該絕緣保護膜213結合於該承載件8上。
再者,於切單該晶圓5後,該導線301將外露於該第一電子元件30之側面30c。應可理解地,該導線301亦可外露於該第一電子元件30之非作用面30b。
如圖3C所示,於該第一電子元件30之非作用面30b與側面30c上形成一導電層32,使該導電層32包覆該第一電子元件30。
於本實施例中,該導電層32係採用電鍍、沉積或其它方式塗佈於該第一電子元件30之全部或部分之非作用面30b及/或全部或部分之側面30c上。
再者,該導電層32係接觸該導線301,以藉由該導線301電性連接該電極墊300,且該導電層32未電性連接該些接點300a。例如,該導電層32與該導線301係作為電力傳輸結構。
如圖3D所示,沿如圖3C所示之切割路徑L進行切單製程,再移除該承載件8,俾獲取複數電子模組3,其中,該導電層32未形成於該第一電子元件30之作用面30a上。
於本實施例中,將該電子模組3應用於圖2E所示之電子封裝件2中,部分該導電柱23將作為其中一條電力傳輸路徑,而該第一電子元件30係具有另一條電力傳輸路徑(即該導電層32、該導線301與該些電極墊300),故該第一
電子元件30能作為至少兩個第二電子元件24之間的橋接晶片,以提供該些第二電子元件24所需之電力。
圖4A及圖4B係為本發明之電子封裝件4之第二實施例的剖面示意圖。本實施例與第一實施例之差異在於該電子封裝件4配置有多組電力傳輸結構,故以下不再贅述相同處。
如圖4A所示,該電子元件21係具有兩組電力傳輸結構,其包含兩相互分開而不相連之導線211,410,以令該兩導線211,410分別電性連接不同之第二電子元件24,且該兩導線211,410係分別電性連接第一導電層22a與第二導電層22b,其中,該第一導電層22a與第二導電層22b係形成於該第一電子元件21之側面21c與非作用面21b上且相互分開而不相連。
於本實施例中,該第一線路層201係具有第一連接部40a與第二連接部40b,以分別電性連接該第一導電層22a與第二導電層22b。例如,該第一與第二連接部40a,40b可為墊狀、柱狀或其它適當形式,並無特別限制。
再者,於兩組電力傳輸結構中,如圖4B所示,其中一導線411(其電性連接該第一導電層42a)可電性連接不同之第二電子元件24,44,而另一導線412(其電性連接該第二導電層42b)係電性連接單一第二電子元件44,使同一第二電子元件44可由兩組電力傳輸結構(即該兩導線411,412)提供所需之電力,其中,該第一導電層42a與第二導電層42b係形成於該第一電子元件21之非作用面21b上,且該第一連接部40a係電性連接該第一導電層42a,而該第二連接部40b係電性連接該第二導電層42b。
本發明復提供一種電子封裝件2,係包括:一包覆層25、一嵌埋於該包覆層25中之第一電子元件21以及至少一形成於該第一電子元件21上之導電層22,42。
所述之第一電子元件21係具有相對之作用面21a與非作用面21b及鄰接該作用面21a與非作用面21b之側面21c,該作用面21a係具有至少一電極墊210,且該第一電子元件21之內部係配置有至少一電性連接該電極墊210之導線211,411。
所述之導電層22,42係嵌埋於該包覆層25中且電性連接該導線211,411,其中,該導電層22,42未形成於該電極墊210上。
於一實施例中,該電極墊210係位於該作用面21a之中間處。
於一實施例中,該導線211,411係外露於該第一電子元件21之側面21c及/或該非作用面21b,以接觸該導電層22,42。
於一實施例中,該導電層22,42係形成於該第一電子元件21之非作用面21b及/或該側面21c上。
於一實施例中,所述之電子封裝件2復包括一形成於該包覆層25上且電性連接該電極墊210之佈線結構26。例如,該佈線結構26係具有相對之第一表面26a與第二表面26b,以令該包覆層25與該第一電子元件21配置於該第一表面26a上,且於該第二表面26b上配置至少一電性連接該佈線結構26之第二電子元件24,44。進一步,該佈線結構26之第二表面26b上係配置複數該第二電子元件24,44,以令該第一電子元件21電性橋接複數該第二電子元件24,44之其中二者。
於一實施例中,所述之電子封裝件2復包括嵌埋於該包覆層25中之導電柱23。進一步包括形成於該包覆層25上且電性連接該導電層22與該導電柱25之導電元件29。
於一實施例中,所述之電子封裝件2復包括形成於該包覆層25上且電性連接該導電層22之導電元件29。
於一實施例中,該第一電子元件21之內部係配置有複數相互分開而不相連之該導線211,410,411,412,且於該第一電子元件21上形成有複數相互分開而不相連之第一導電層22a,42a與第二導電層22b,42b,以令該複數導線211,410,411,412分別電性連接該第一導電層22a,42a與第二導電層22b,42b。
綜上所述,本發明之電子封裝件及其製法,係藉由該第一電子元件上形成有電極墊、導線與導電層,以令該電極墊、導線與導電層作為電力傳輸結構,使本發明之電子封裝件除了導電柱作為電流路徑外,更有另一條由該電極墊、導線與導電層所組成之電流路徑,以降低該電子封裝件之直流電阻,因而能改善電流供應所產生之阻抗問題。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
2:電子封裝件
20:承載結構
21:第一電子元件
211:導線
22:導電層
23:導電柱
24:第二電子元件
25:包覆層
26:佈線結構
26a:第一表面
26b:第二表面
28:封裝層
29:導電元件
7:電子裝置
70,71:電源供應埠
Claims (20)
- 一種電子封裝件,係包括:包覆層;第一電子元件,係嵌埋於該包覆層中,其中,該第一電子元件係具有相對之作用面與非作用面及鄰接該作用面與非作用面之側面,該作用面係具有至少一電極墊,且該第一電子元件之內部係配置有至少一電性連接該電極墊之導線,其中,該導線係外露於該第一電子元件之側面及/或該非作用面;以及至少一導電層,係形成於該第一電子元件上並嵌埋於該包覆層中且接觸該導線,其中,該導電層未形成於該電極墊上。
- 如請求項1所述之電子封裝件,其中,該電極墊係位於該作用面之中間處。
- 如請求項1所述之電子封裝件,其中,該導電層係形成於該第一電子元件之非作用面及/或該側面上。
- 如請求項1所述之電子封裝件,復包括形成於該包覆層上且電性連接該電極墊之佈線結構。
- 如請求項4所述之電子封裝件,其中,該佈線結構係具有相對之第一表面與第二表面,以令該包覆層與該第一電子元件配置於該第一表面上,且於該第二表面上配置至少一電性連接該佈線結構之第二電子元件。
- 如請求項5所述之電子封裝件,其中,該佈線結構之第二表面上係配置複數該第二電子元件,以令該第一電子元件電性橋接複數該第二電子元件之其中二者。
- 如請求項1所述之電子封裝件,復包括嵌埋於該包覆層中之導電柱。
- 如請求項7所述之電子封裝件,復包括形成於該包覆層上且電性連接該導電層與該導電柱之複數導電元件。
- 如請求項1所述之電子封裝件,復包括形成於該包覆層上且電性連接該導電層之複數導電元件。
- 如請求項1所述之電子封裝件,其中,該第一電子元件之內部係配置有複數相互分開而不相連之該導線,且於該第一電子元件上形成有複數相互分開而不相連之該導電層,以令該複數導線分別電性連接不同之該導電層。
- 一種電子封裝件之製法,係包括:提供表面具有至少一導電層之第一電子元件,其中,該第一電子元件係具有相對之作用面與非作用面及鄰接該作用面與非作用面之側面,該作用面係具有至少一電極墊,且該第一電子元件之內部係配置有至少一電性連接該電極墊之導線,其中,該導線係外露於該第一電子元件之側面及/或該非作用面,以令該導電層接觸該導線,且該導電層未形成於該電極墊上;以及將該第一電子元件連同該導電層一併嵌埋於包覆層中。
- 如請求項11所述之電子封裝件之製法,其中,該電極墊係位於該作用面之中間處。
- 如請求項11所述之電子封裝件之製法,其中,該導電層係形成於該第一電子元件之非作用面及/或該側面上。
- 如請求項11所述之電子封裝件之製法,復包括形成佈線結構於該包覆層上,且該佈線結構係電性連接該電極墊。
- 如請求項14所述之電子封裝件之製法,其中,該佈線結構係具有相對之第一表面與第二表面,以令該包覆層與該第一電子元件配置於該第一表面上,且於該第二表面上配置至少一電性連接該佈線結構之第二電子元件。
- 如請求項15所述之電子封裝件之製法,其中,該佈線結構之第二表面上係配置複數該第二電子元件,以令該第一電子元件電性橋接複數該第二電子元件之其中二者。
- 如請求項11所述之電子封裝件之製法,復包括於該包覆層中嵌埋導電柱。
- 如請求項17所述之電子封裝件之製法,復包括形成複數導電元件於該包覆層上,且該複數導電元件係電性連接該導電層與該導電柱。
- 如請求項11所述之電子封裝件之製法,復包括形成複數導電元件於該包覆層上,且該複數導電元件係電性連接該導電層。
- 如請求項11所述之電子封裝件之製法,其中,該第一電子元件之內部係配置有複數相互分開而不相連之該導線,且於該第一電子元件上形成有複數相互分開而不相連之該導電層,以令該複數導線分別電性連接不同之該導電層。
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US20230343665A1 (en) | 2023-10-26 |
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