CN106877653A - The circuit and its method of a kind of DCM switching power converters controlling dead error time - Google Patents
The circuit and its method of a kind of DCM switching power converters controlling dead error time Download PDFInfo
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- CN106877653A CN106877653A CN201710245183.7A CN201710245183A CN106877653A CN 106877653 A CN106877653 A CN 106877653A CN 201710245183 A CN201710245183 A CN 201710245183A CN 106877653 A CN106877653 A CN 106877653A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/175—Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
- H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Power Engineering (AREA)
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- General Physics & Mathematics (AREA)
- Inverter Devices (AREA)
Abstract
The circuit and its method of a kind of DCM sluggishness converter controlling dead error time, task driven signal in by chain of inverters driving power pipe after the time adjusting circuit of adaptive dead zone by carrying out open and close, while self adaptation obtains optimal Dead Time.By to Lx points power P mos shut-off after, power Nmos open when voltage sampling, so as to obtain the information of Dead Time, during sampled signal fed back into self-adaptive dead-time control circuit, the signaling rate of binary system delay line is adjusted, so as to realize the adaptive control optimization of Dead Time.
Description
Technical field
The present invention relates to switching power converters, especially a kind of circuit of DCM sluggishness converter controlling dead error times
And its method, Dead Time between two power output pipes is effectively adjusted when system works in different loads state, so that
Reduce loss and improve power conversion efficiency.
Background technology
Although the switching power converters control signal of synchronous rectification structure is compared to asynchronous rectifier switch power conversion
Complexity is controlled for device, but power attenuation is lower, is particularly suitable for making in low pressure small-power dc-dc supply convertors
With.Wherein, the sluggish switching power converters under DCM patterns are more aimed at the first-selected structure in the case of low current output.So
And, innately there are problems that Dead Time is unmatched in the grid control signal of the high and low side power tube of supply convertor, this makes
Into the loss of power, the lifting of efficiency is hindered.
Fig. 1 show traditional synchronous rectification configuration switches supply convertor, including control circuit and power stage circuit two
Part.Control circuit is made up of DCM hysteresis control circuits, dead time circuit and power tube drive circuit, power stage circuit
It is made up of high and low side power tube M1, M2, inductance L, load capacitance Cout.High side PMOS power tube M1 sources connect input power
Voltage, downside NMOS power tube M2 sources ground connection, the drain electrode of two power tubes is connected and is connected with one end of inductance L, tie point note
It is Lx.The other end of inductance L and output filter capacitor CoutIt is connected, electric capacity CoutThe other end is grounded.Inductance L and electric capacity CoutComposition
Output filter network, both tie points meet output loading Rload, the grid of high and low side power tube connects grid end control signal respectively
PG0、NG0。
When system is worked under DCM patterns, its working condition is as shown in Fig. 2 wherein ILIt is inductive current, IoutFor defeated
Go out electric current, VrefIt is output reference voltage, VoutIt is system output voltage.The sluggish electricity of DCM since circuit is controlled the t1 moment
Road detects VoutLess than Vref, that is, think the beginning of a cycle, and transmission of control signals gives rear stage circuit.In t1~t2 ranks
Section VoutLess than Vref, now M1 is opened, M2 is closed, and inductive current is started from scratch rising, when charging to VoutMore than VrefWhen, continue
The hold mode t3 times.T4~t5 stages afterwards, M2 is opened, and M1 is closed, and inductive current is gradually decreased to 0, now VoutStill greater than
Vref.M1, M2 are simultaneously closed off in the t6 stages, until VoutLess than Vref.So far a cycle is completed, DCM hysteresis circuitries are transmitted again
Cyclic control signal.
In the whole DCM work periods, in power tube switch handoff procedure, particularly M1 is closed, the process of M2 conductings
In, in fact it could happen that the of short duration situation about simultaneously turning on of M1, M2, path is formed between power supply and ground so as to cause larger energy to damage
Consumption.So needing to add certain Dead Time between the switching process of M1, M2.The length of Dead Time can be to a certain extent
Influence the efficiency of whole system.As shown in figure 3, wherein Fig. 3-a are illustrated when Dead Time is excessive, i.e., after M1 is closed,
Just opened every M2 after the long period, then in node Lx positions, its voltage VLx may proceed to decline from after Vin near 0, Zhi Daogong
The parasitic diode of rate pipe M2 is opened, and inductive current is reversely extracted to output from ground through M2, and parasitic diode causes excess power
Loss.Fig. 3-b are the too small situation of Dead Time, and when Lx node voltages not yet drop to zero, M2 has been turned on, such case
Under not only result in the loss of power tube parasitic capacitance energy, and make it possible to M1, M2 and simultaneously turn on, power supply, it
Between form peak current.Fig. 3-c show the working condition of system under the optimal time of dying, i.e., closed in M1, and VLx just drops
To M2 conduction voltage drops VdsonWhen, M2 is opened.Because conduction voltage drop is smaller, VLx can be equal to and drop to 0.Most preferably die the time
Can with power pipe size, system input, output voltage, the change of load current and change, it is impossible to be defined as a fixed value.
The content of the invention
It is an object of the present invention to provide the circuit and its method of a kind of DCM sluggishness converter controlling dead error times, using prolonging
When technology propose the dynamic adjustment of optimal Dead Time, work in different inputs, output voltage and different loads electricity in system
Dead Time can be always stable at by optimal value, lifting system effect with the optimal Dead Time of the acquisition of self adaptation in the case of stream
Can, reduce power tube loss.
To achieve the above object, the present invention uses following technical scheme：A kind of DCM switching power converters controlling dead error
The circuit of time, including control circuit and power stage circuit two parts, when control circuit includes DCM hysteresis control circuits, dead band
Between circuit and power tube drive circuit, DCM hysteresis control circuits output connection dead time circuit, dead time circuit produce
Control signal PG and NG containing Dead Time the output control signal PG0 and NG0 after power tube drive circuit give power stage electricity
Road, power stage circuit includes high side PMOS power tubes M1, downside NMOS power tubes M2, inductance L, output filter capacitor CoutWith it is defeated
Go out to load Rload, the source ground of source electrode connection input supply voltage Vin, the NMOS power tube M2 of PMOS power tubes M1, PMOS
The drain electrode of power tube M1 is connected with the drain interconnection of NMOS power tubes M2 and with one end of inductance L, and tie point is designated as Lx, inductance L
Other end connection output filter capacitor CoutOne end and output loading RloadOne end, output filter capacitor CoutThe other end
And output loading RloadOther end ground connection, inductance L and electric capacity CoutComposition output filter network, the grid of PMOS power tubes M1
With the driving control signal PG0 and NG0 that the grid of NMOS power tubes M2 connects power tube drive circuit output respectively；
It is characterized in that：Dead time circuit in control circuit uses DCM self-adaptive dead-time control circuits, power
Tube drive circuit is constituted using two-way chain of inverters, sets the voltage change that two-way zero cross detection circuit detects Lx points, output two
The input that zero balancing signal is connected to DCM self-adaptive dead-time control circuits is passed by, different inputs, defeated are worked in system
Go out under voltage and different loads current conditions to be capable of the optimal Dead Time of the acquisition of self adaptation, Dead Time is stablized always
In optimal value, lifting system efficiency reduces power tube loss；
DCM self-adaptive dead-time control circuits include dynamic deferred unit, fixed delay unit, rest-set flip-flop RSFF1
And OR gate or1 and door and1 and door and2 and phase inverter inv15；Dynamic deferred unit has three input ports, an end
The system switching control signal in of mouth connection prime DCM hysteresis control circuit outputs, two other port connects zero passage inspection respectively
The end of oppisite phase Q of the signal of the Zero-cross comparator all the way zd2 and rest-set flip-flop RSFF1 of slowdown monitoring circuit output-The clock signal fw of output is held, is moved
The input and an input with door and2 of the output connection phase inverter inv15 of state delay cell, phase inverter inv15's is defeated
Go out to connect the S ends of rest-set flip-flop RSFF1, the Q ends output connection of rest-set flip-flop RSFF1 and another input of door and2, with
Self adaptation is added the control signal NG of optimal Dead Time and is connected to an input of OR gate or1 all the way for door and2 outputs,
System switching the control signal in, OR gate or1 of another input connection prime DCM hysteresis control circuit outputs of OR gate or1
The control signal PG that another road self adaptation adds optimal Dead Time is exported, fixed delay unit is connected including even number of inverters
Constitute, wherein the control of optimal Dead Time is added in the input connection of first phase inverter with the self adaptation all the way of door and2 outputs
Signal NG processed, the output connection of last phase inverter and an input of door and1, another input with door and1
The another of connection zero cross detection circuit output passes by zero balancing signal zd1, is connected rest-set flip-flop RSFF1's with the output of door and1
R ends；
Dynamic deferred unit includes the d type flip flop DFF1 of rising edge triggering, a 2-1 decoders MUX1, one 6
Forward-backward counter, 6 binary system delay lines and including with door and3 and door and4 and door and5 and door and6 and door
The counting limitation that and7, OR gate or2, OR gate or3, OR gate or4, nor gate nor1, nor gate nor2 and phase inverter inv16 are constituted
Circuit；The Q1 that is connected respectively with two inputs of door and3 in the 6 bit Q0-Q5 that 6 forward-backward counters are exported and
Q2, Q3 and Q4 in the 6 bit Q0-Q5 that 6 forward-backward counters are exported are connected with two inputs of door and4 respectively,
An input with door and5 is connected with the output of door and3, is connected defeated with door and4 with another input of door and5
Go out end, an input with door and6 is connected with the output end of door and5,6 are connected with another input of door and6 and are added
Q5 in 6 bit Q0-Q5 of down counter output, an input of nor gate nor2 is connected with the output end of door and6
End, the output end and an input with door and7 of another input connection nor gate nor1 of nor gate nor2, or it is non-
Two inputs of door nor1 connect the output end and 66 bit Q0- of forward-backward counter output of OR gate or4 respectively
Two inputs of the Q5 in Q5, OR gate or4 connect the output end of OR gate or2 and the output end of OR gate or3, OR gate or2 respectively
Two inputs connect Q1 and Q2 in 6 bit Q0-Q5 of 6 forward-backward counters output, the two of OR gate or3 respectively
Individual input connects the Q3 and Q4 in 66 bit Q0-Q5 of forward-backward counter output respectively, and nor gate nor2's is defeated
Go out the input of end connection phase inverter inv16 and the control end of 2-1 decoders MUX1, the output end connection of phase inverter inv16 with
Another input of door and7, an input of 2-1 decoders MUX1,2-1 decoders are connected with the output end of door and7
The output Q ends of another input connection d type flip flop DFF1 of MUX1, the D inputs connection zero passage detection electricity of d type flip flop DFF1
The clock end of Zero-cross comparator the signal zd2, d type flip flop DFF1 of road output connects the end of oppisite phase Q of rest-set flip-flop RSFF1-End output
Clock signal fw, 2-1 decoder MUX1 output end connect 6 control signals of forward-backward counter, 6 forward-backward counters
Clock end interconnected with 6 binary system delay line inputs and be connected prime DCM hysteresis control circuits output system
Switch controlling signal in, another input of bit Q0-Q5 to 6 binary system delay line of 6 forward-backward counter output 6
End, the output of 6 binary system delay lines is the output of dynamic deferred unit；
6 binary system delay lines include phase inverter inv17~inv22, NMOS tube MN2~MN14, PMOS MP2 and MP3
And time adjustment electric capacity C1；Q0 in 66 bit Q0-Q5 of forward-backward counter output connects the defeated of phase inverter inv17
Enter end, the source electrode of NMOS tube MN3 interconnects and be grounded with the source electrode of NMOS tube MN2, the drain electrode of NMOS tube MN3 and NMOS tube MN2's
Drain electrode connects the drain electrode of the source electrode and NMOS tube MN3 of the source electrode and NMOS tube MN4 of NMOS tube MN5 and the leakage of NMOS tube MN2 respectively
Pole interconnects；The drain electrode of NMOS tube MN5 and the drain electrode of NMOS tube MN4 connect the source electrode of NMOS tube MN7 and the source of NMOS tube MN6 respectively
The drain electrode of pole and NMOS tube MN5 and the drain interconnection of NMOS tube MN4；The drain electrode of NMOS tube MN7 and the drain electrode difference of NMOS tube MN6
The drain electrode of the source electrode of connection NMOS tube MN9 and the source electrode and NMOS tube MN7 of NMOS tube MN8 and the drain interconnection of NMOS tube MN6；
The drain electrode of NMOS tube MN9 and the drain electrode of NMOS tube MN8 respectively the source electrode of connection NMOS tube MN11 and the source electrode of NMOS tube MN10 and
The drain electrode of NMOS tube MN9 and the drain interconnection of NMOS tube MN8；The drain electrode of NMOS tube MN11 and the drain electrode of NMOS tube MN10 connect respectively
Connect drain electrode and the drain interconnection of NMOS tube MN10 of the source electrode of NMOS tube MN13 and the source electrode of NMOS tube MN12 and NMOS tube MN11；
NMOS tube MN3, MN5, the grid of MN7, MN9, MN11 and MN13 connect respectively phase inverter inv17, inv18, inv19, inv20,
The output end of inv21 and inv22, the input of phase inverter inv17, inv18, inv19, inv20, inv21 and inv22 connects respectively
Meet Q0, Q1, Q2, Q3, Q4 and the Q5 during 6 forward-backward counters export 6 bit Q0-Q5；The drain electrode of NMOS tube MN13 with
The drain interconnection of NMOS tube MN12 and the grid of the drain electrode with PMOS MP2, one end of time adjustment electric capacity C1 and PMOS MP3
The grid of pole and NMOS tube MN14 links together, and the other end of time adjustment electric capacity C1 and the source electrode of NMOS tube MN14 connect
Ground, the source electrode of the source electrode connection PMOS MP2 of PMOS MP3 simultaneously connects supply voltage Vin, the grid and NMOS of PMOS MP2
The grid of pipe MN2, the grid of NMOS tube MN4, the grid of NMOS tube MN6, the grid of NMOS tube MN8, the grid of NMOS tube MN10
And the grid of NMOS tube MN12 link together and connect prime DCM hysteresis control circuits output system switching control signal
The drain electrode of in, PMOS MP3 connects the drain electrode of NMOS tube MN4 and as 6 output ends of binary system delay line；
Power tube drive circuit include two-way chain of inverters, all the way chain of inverters include be sequentially connected phase inverter ivn1~
When the self adaptation of the input connection DCM self-adaptive dead-time control circuit outputs of ivn6, phase inverter ivn1 adds optimal dead band
Between control signal PG, phase inverter ivn6 exports the grid that enhanced driving control signal PG0 is connected to PMOS power tubes M1；Separately
Chain of inverters includes the phase inverter ivn7~ivn12 being sequentially connected, the input connection DCM adaptive dead zones of phase inverter ivn7 all the way
The self adaptation of time control circuit output adds the control signal NG of optimal Dead Time, and phase inverter ivn6 exports enhanced driving
Control signal NG0 is connected to the grid of NMOS power tubes M2；In two-way chain of inverters, per each phase inverter length wide in all the way
Than being increased step by step as multiple with naturally low logarithm e successively, to obtain the driving force of maximum；
Zero cross detection circuit includes two zero passage detection modules, and a zero passage detection module is used to detect Lx point voltages by bearing
Be changed on the occasion of moment, including comparator COMP1 and phase inverter ivn13, comparator COMP1 negative input connection Lx points,
Positive level input end grounding, the inverted device ivn13 output Zero-cross comparator signals zd1 of output of comparator COMP1；Another zero passage is examined
Surveying module is used to detect that, in switching power converters normal work, after PMOS power tubes M1 is closed, NMOS power tubes M2 to be opened
Moment Lx points voltage condition, including comparator COMP2, phase inverter ivn14, sampling capacitance C_sample and by NMOS tube
The transmission gate of MN1 and PMOS MP1 compositions, the source electrode of NMOS tube MN1 is interconnected with the source electrode of PMOS MP1 and is connected Lx points,
The drain interconnection of the drain electrode of NMOS tube MN1 and PMOS MP1 is simultaneously connected one end and the comparator COMP2 of sampling capacitance C_sample
Negative input, the grid of NMOS tube MN1 and the grid of PMOS MP1 are connected in power tube drive circuit chain of inverters respectively
The output NG1 of phase inverter ivn11 and the electrode input end connection sampling electricity of the output NG2 of phase inverter ivn10, comparator COMP2
Hold the other end of C_sample and be grounded, the inverted device ivn14 output Zero-cross comparator signals zd2 of output of comparator COMP2.
Adaptive dead-time control method according to foregoing circuit, it is characterised in that：DCM adaptive dead-time controls
Circuit meets DCM mode of operations, self adaptation addition most for the system switching control signal in of input to be converted into two-way
The control signal PG and NG of excellent Dead Time, wherein, using the rest-set flip-flop RSFF1 and output signal zd1 of zero cross detection circuit
Cooperation, can realize meeting the two-way power tube drive signal of DCM Schema control requirements, and utilize dynamic deferred unit and mistake
The output zd2 of zero detection circuit coordinates, and be capable of self adaptation is the addition dead band of PG, NG two-way power tube drive signal self adaptation
Time, in dynamic deferred unit, coordinated using 6 binary system delay lines and 6 forward-backward counters, in Switching Power Supply conversion
In the device course of work, after PMOS M1 is closed, Lx point voltages constantly decline, if Lx points voltage is more than 0, generation when NMOS tube M2 is opened
It is too small that table Dead Time, then increase by 6 forward-backward counters and count, that is, increase Dead Time；If NMOS tube M2 is opened, Lx points
Voltage is less than 0, and it is excessive to represent Dead Time, then reduce by 6 forward-backward counters and count, that is, reduce Dead Time, by so
Sampling comparative approach, obtain in dcm operating modes when, power tube PMOS close and power NMOS tube open between Dead Time
Information, the feedback of the information of Dead Time is returned into auto-adaptive time control unit, so that appropriate 6 forward-backward counters of adjustment
Binary system is exported, and to cause that Dead Time obtains the adjustment of self adaptation, final stabilization is in an optimal Dead Time, power tube
Grid control signal carries out enhancing driving force by the power tube driving stage that chain of inverters is constituted, and is finally used to control power tube
Switch, realize self adaptation the controlling dead error time take optimal position without being input into, output voltage and load current
The influence of change, optimal value is stable at by Dead Time always.
The present invention has advantages below and remarkable result：
1st, in reading each cycle, Dead Time when switching power converters DCM works, and according to actual conditions to dead
Area's time carries out the adjustment of self adaptation, so as to obtain optimal Dead Time, reduces system loss, raising efficiency.
2nd, DCM Dead Times adaptation control circuit only adds Dead Time to the rising edge of in signals, and for declining
The sequential on edge is not done and is influenceed.This is conducive to controlling circuit for the control of power tube output timing.
3rd, it is used in the present invention to control circuit while self adaptation addition Dead Time is completed, also by way of zero passage ratio
Compared with the control that device realizes circuit DCM mode of operations.So as to reduce circuit complexity, it is not necessary to which additional circuit is used to control
DCM sequential.
Brief description of the drawings
Fig. 1 is traditional synchronous rectification configuration switches power converter circuit structure chart；
Fig. 2 is circuit operating diagram under switching power converters DCM patterns；
Fig. 3 is that Dead Time is of different sizes to systematic influence schematic diagram；
Fig. 4 is general principles block diagram of the invention；
Fig. 5 is power tube driving stage circuit diagram of the present invention；
Fig. 6 is zero cross detection circuit schematic diagram of the present invention；
Fig. 7 is DCM self-adaptive dead-time control circuits schematic diagram of the present invention；
Fig. 8 is each node potential variation diagram of DCM self-adaptive dead-time control circuits under normal work；
Fig. 9 is dynamic deferred element circuit schematic diagram of the invention；
Figure 10 is binary system delay line circuit diagram of the present invention.
Specific embodiment
Therefore the present invention proposes optimal Dead Time dynamic regulating circuit using technology between time delay, and Dead Time is stablized always
In optimal value, so as to improve system effectiveness.
As shown in figure 4, the present invention includes DCM self-adaptive dead-time control circuits, power tube drive circuit, power stage electricity
Road (relevant art) and two-way zero cross detection circuit.Vin is supply voltage, the connection input of high side PMOS power tube M1 sources in figure
Supply voltage, downside NMOS power tube M2 sources ground connection, the drain electrode of two power tubes is connected and is connected with one end of inductance L, connects
Point is designated as Lx.The other end of inductance L is connected with output filter capacitor Cout, electric capacity other end ground connection.Inductance L and electric capacity Cout groups
Into output filter network, both tie points meet output loading Rload, and nodename is Vout.Pmos power tube M1, Nmos work(
Rate pipe M2, inductance L, output capacitance CloadAnd output loading RloadConstitute power stage circuit.DCM hysteresis control circuits are produced
Control signal from port in be input into DCM self-adaptive dead-time control circuits so that produce contain Dead Time self adaptation adjust
Whole power tube control signal PG, NG.After the two people's signals are input to power tube drive circuit, power tube drive circuit is defeated
Go out driving force stronger drive signal PG0, NG0.The grid of high and low side power tube M1, M2 connects grid end control signal respectively
PG0、NG0.Zero cross detection circuit is sampled Lx point voltages, and is exported zd1, zd2 two-way Zero-cross comparator signal and be recycled to DCM self adaptations
Dead-time control circuit.
Fig. 5 is power tube driving stage circuit diagram, including two chain of inverters inv1-inv6 and inv7-inv12.Two anti-
Each phase inverter breadth length ratio size is gradually increased with natural logrithm e as multiple in phase device chain.Control signal PG, NG passes through two respectively
Chain of inverters increases driving force, obtains output signal PG0, NG0 with driving power pipe M1, M2.The output of inv10 and inv11
Respectively NG2, NG1, use as the sampled signal of transmission gate before control sampling capacitance in zero-crossing comparator.
Fig. 6 is zero cross detection circuit schematic diagram, and zero cross detection circuit is made up of two zero passage detection modules, its output difference
Correspondence zd1 and zd2.The correspondence output of zero passage detection module one zd1 is simple Zero-cross comparator circuit, and comparator COMP1 negative poles are defeated
It is Lx, positive level input end grounding to enter end.When power P mos pipes M1 is closed, after power Nmos pipes M2 is opened, Lx point voltages are with electricity
The continuous reduction of inducing current IL, from negative value constantly close to zero, zero passage detection module one is used for detecting Lx point voltages by negative change
Be on the occasion of moment.The correspondence output of zero passage detection module two zd2.The transmission gate being made up of zero-crossing comparator COMP2, MN1, MP1
And sampling capacitance C_sample compositions.The positive level input end grounding of zero-crossing comparator COMP2, negative input is by transmission gate
Lx points are connected afterwards, while in the sampling capacitance C_sample of negative input connection other end ground connection.The grid of transmission gate is by work(
The switching signal of rate Nmos pipes is controlled.Zero passage detection module two be used for detect in switching power converters normal work,
After M1 is closed, the voltage condition of the moment Lx points that M2 is opened.
Fig. 7 is DCM self-adaptive dead-time control circuit schematic diagrames, and DCM self-adaptive dead-time control circuits are used for will
The periodic system switch controlling signal in that the DCM hysteresis circuitries of input are produced be converted into two-way meet DCM mode of operations,
Self adaptation adds control signal PG, the NG output of optimal Dead Time.Wherein, it is defeated with zero cross detection circuit using rest-set flip-flop
Going out zd1 signals and output NG signals can realize that meeting DCM Schema controls wants by the cooperation after of short duration fixed delay circuit
The two-way power tube drive signal asked, and can be with adaptive with the output zd2 cooperations of zero cross detection circuit using dynamic deferred unit
What is answered is the addition Dead Time of PG, NG two-way power tube drive signal self adaptation.Fw signals are exported for rest-set flip-flop end of oppisite phase
Signal, is used for SECO in tieback to dynamic deferred unit.
Fig. 8 is each node potential variation diagram of DCM self-adaptive dead-time control circuits under normal work.It is wherein dynamic deferred
Unit only postpones rising edge, and to trailing edge without modification.Initial state is 0 for input control signal in, and signal PG, NG are 0,
Power tube PMOS M1 is opened, power NMOS tube M2 is closed.When in is changed into 1 from 0, PG signals immediately become 1, M1 closings.Simultaneously
Signal in after dynamic deferred unit after postponing one section of Dead Time so that VA is changed into 1, S and is changed into 0 from 1 from 0.Due to Q always
High level, NG signals is kept also to overturn therewith, M2 is opened.Now circuit enters freewheeling period, and inductive current is from ground by after M2
Inductance is flowed into, Lx point voltages are negative, and zd1 is changed into 0.As inductive current is gradually reduced, Lx point voltages gradually rise up to from negative value
Zero.When Lx point voltages become timing by negative, zd1 is changed into 1 from 0.So that R signal produces rising edge, it is 0 that Q is changed into 0, NG upsets from 1,
M2 is closed.When the another in upsets of the control signal in next cycle are 0, M1 is opened and VA, Q signal upset.
Fig. 9 is dynamic deferred cellular construction schematic diagram, and it includes the d type flip flop DFF1, a 2-1 of rising edge triggering
Decoder 2-1MUX1,6 forward-backward counters, 6 binary system delay lines and counting limiting circuit are (with door and3-
And7, OR gate or2-or4, nor1, nor gate nor2, phase inverter inv16).6 forward-backward counter inputs are believed to rise, declining
Number up/down_ and clock signal clk, are output as 6 bit Q0-Q5.When up/down_ is 1, under each clock signal
Drop adds one along 6 bits, and when up/down_ is 0, each bit of clock signal trailing edge 6 subtracts one.6 plus-minuss
The binary number of counter output is input in 6 binary system delay lines and counting limiting circuit.DCM hysteresis control signals are from
6 binary system delay lines of end input, the output of out ends, the binary number control that delay time is received.Limiting circuit is counted to use
In the counting size of detection forward-backward counter, with reference to 2-1MUX1 so that exporting and will not be less than when in forward-backward counter counting process
000000 or more than 111111.When circuit normal work, the end signal S that controls of 2-1MUX1 is 1, then X1 signals are effective.D is touched
Hair device DFF1 reads the output signal of zero-crossing comparator zd2 in each clock signal fw rising edges, that is, represent close as M1,
M2 when being opened after Dead Time, the magnitude of voltage of Lx points.After M1 is closed, Lx point voltages constantly decline, if Lx points when M2 is opened
Voltage is 1 more than 0, zd2, then it represents that Dead Time is too small, and at P ends during trailing edge, count is incremented for 6 forward-backward counters, during dead band
Between increase.If M2 is opened, Lx point voltages are 0 less than 0, zd2, then it represents that Dead Time is excessive, and at P ends during trailing edge, 6 add
Down counter is counted and subtracts 1, and Dead Time reduces.By such method, you can realize that the controlling dead error time of self adaptation takes
Optimal position without by being input into, output voltage and load current change influenceed.
Figure 10 is binary system delay line circuit diagram.6 binary system delay line circuits are by phase inverter inv17-inv22, MN2-
MN14, MP2-MP3 and time adjustment electric capacity C1 composition.6 forward-backward counter output Q0-Q5 are input into 6 binary system time delays
After line, by phase inverter shaping, the grid of MN3, MN5, MN7, MN9, MN11, MN13 is connected, control the rear conducting resistance to be with R
The switch of MN2, MN4, MN6, MN8, MN10, MN12 that radix is multiplied, so that releasing when adjusting electric capacity C1 leakage currents
Speed, after being finally able to the rising edge input of adjustment IN signals, the delay time of out ends output.The final control for being able to self adaptation
The Dead Time of circuit.
The method that the present invention is compared by sampling, is obtained when in dcm operating modes, and power tube PMOS is closed and power
The information of Dead Time, returns auto-adaptive time control unit, so that suitably by the feedback of the information of Dead Time between NMOS tube unlatching
Adjustment forward-backward counter binary system output, final such that Dead Time obtains the adjustment of self adaptation, final stabilization exists
One optimal Dead Time.Final power tube grid control signal is carried out by the power tube driving stage that chain of inverters is constituted
Enhancing driving force, is finally used to control the switch of power tube.
Claims (2)
1. a kind of circuit of DCM switching power converters controlling dead error time, including control circuit and power stage circuit two
Point, control circuit includes DCM hysteresis control circuits, dead time circuit and power tube drive circuit, DCM hysteresis control circuits
Output connection dead time circuit, dead time circuit produces the control signal PG and NG containing Dead Time to be driven through power tube
To power stage circuit, power stage circuit includes high side PMOS power tubes M1, downside to output control signal PG0 and NG0 after circuit
NMOS power tubes M2, inductance L, output filter capacitor CoutWith output loading Rload, the source electrode connection input electricity of PMOS power tubes M1
The source ground of source voltage Vin, NMOS power tube M2, the drain electrode of PMOS power tubes M1 is with the drain interconnection of NMOS power tubes M2 simultaneously
One end with inductance L is connected, and tie point is designated as Lx, the other end connection output filter capacitor C of inductance LoutOne end and output it is negative
Carry RloadOne end, output filter capacitor CoutThe other end and output loading RloadOther end ground connection, inductance L and electric capacity Cout
Composition output filter network, the grid of PMOS power tubes M1 and the grid of NMOS power tubes M2 connect power tube drive circuit respectively
The driving control signal PG0 and NG0 of output；
It is characterized in that：Dead time circuit in control circuit uses DCM self-adaptive dead-time control circuits, power tube to drive
Dynamic circuit is constituted using two-way chain of inverters, sets the voltage change that two-way zero cross detection circuit detects Lx points, and output two is passed by
Zero balancing signal is connected to the input of DCM self-adaptive dead-time control circuits；
DCM self-adaptive dead-time control circuits include dynamic deferred unit, fixed delay unit, rest-set flip-flop RSFF1 and
OR gate or1 and door and1 and door and2 and phase inverter inv15；Dynamic deferred unit has three input ports, and a port connects
The system switching control signal in of prime DCM hysteresis control circuits output is met, two other port connects zero passage detection electricity respectively
The end of oppisite phase Q of the signal of the Zero-cross comparator all the way zd2 and rest-set flip-flop RSFF1 of road output-The clock signal fw of output is held, is dynamically prolonged
The input and an input with door and2 of the output connection phase inverter inv15 of slow unit, the output of phase inverter inv15 connect
The S ends of rest-set flip-flop RSFF1, the Q ends output connection of rest-set flip-flop RSFF1 and another input of door and2 are connect, with door
Self adaptation is added the control signal NG of optimal Dead Time and is connected to an input of OR gate or1 all the way for and2 outputs, or
System switching the control signal in, OR gate or1 of another input connection prime DCM hysteresis control circuit outputs of door or1 are defeated
Go out the control signal PG that another road self adaptation adds optimal Dead Time, fixed delay unit includes even number of inverters series connection structure
Into wherein the control of optimal Dead Time is added in the input connection of first phase inverter with the self adaptation all the way of door and2 outputs
Signal NG, the output connection of last phase inverter connects with an input of door and1, another input with door and1
Meet the another of zero passage detection circuit output and pass by zero balancing signal zd1, the R of rest-set flip-flop RSFF1 is connected with the output of door and1
End；
Dynamic deferred unit includes the d type flip flop DFF1, a 2-1 decoders MUX1,6 plus-minuss of rising edge triggering
Counter, 6 binary system delay lines and including with door and3 and door and4 and door and5 and door and6 and door
The counting limitation that and7, OR gate or2, OR gate or3, OR gate or4, nor gate nor1, nor gate nor2 and phase inverter inv16 are constituted
Circuit；The Q1 that is connected respectively with two inputs of door and3 in the 6 bit Q0-Q5 that 6 forward-backward counters are exported and
Q2, Q3 and Q4 in the 6 bit Q0-Q5 that 6 forward-backward counters are exported are connected with two inputs of door and4 respectively,
An input with door and5 is connected with the output of door and3, is connected defeated with door and4 with another input of door and5
Go out end, an input with door and6 is connected with the output end of door and5,6 are connected with another input of door and6 and are added
Q5 in 6 bit Q0-Q5 of down counter output, an input of nor gate nor2 is connected with the output end of door and6
End, the output end and an input with door and7 of another input connection nor gate nor1 of nor gate nor2, or it is non-
Two inputs of door nor1 connect the output end and 66 bit Q0- of forward-backward counter output of OR gate or4 respectively
Two inputs of the Q5 in Q5, OR gate or4 connect the output end of OR gate or2 and the output end of OR gate or3, OR gate or2 respectively
Two inputs connect Q1 and Q2 in 6 bit Q0-Q5 of 6 forward-backward counters output, the two of OR gate or3 respectively
Individual input connects the Q3 and Q4 in 66 bit Q0-Q5 of forward-backward counter output respectively, and nor gate nor2's is defeated
Go out the input of end connection phase inverter inv16 and the control end of 2-1 decoders MUX1, the output end connection of phase inverter inv16 with
Another input of door and7, an input of 2-1 decoders MUX1,2-1 decoders are connected with the output end of door and7
The output Q ends of another input connection d type flip flop DFF1 of MUX1, the D inputs connection zero passage detection electricity of d type flip flop DFF1
The clock end of Zero-cross comparator the signal zd2, d type flip flop DFF1 of road output connects the end of oppisite phase Q of rest-set flip-flop RSFF1-End output
Clock signal fw, 2-1 decoder MUX1 output end connect 6 control signals of forward-backward counter, 6 forward-backward counters
Clock end interconnected with 6 binary system delay line inputs and be connected prime DCM hysteresis control circuits output system
Switch controlling signal in, another input of bit Q0-Q5 to 6 binary system delay line of 6 forward-backward counter output 6
End, the output of 6 binary system delay lines is the output of dynamic deferred unit；
6 binary system delay lines include phase inverter inv17~inv22, NMOS tube MN2~MN14, PMOS MP2 and MP3 and
Time adjustment electric capacity C1；6 forward-backward counters export the input of the Q0 connection phase inverters inv17 in 6 bit Q0-Q5
End, the source electrode of NMOS tube MN3 interconnects and is grounded with the source electrode of NMOS tube MN2, the drain electrode of NMOS tube MN3 and the leakage of NMOS tube MN2
Pole connects the drain electrode and the drain electrode of NMOS tube MN2 of the source electrode of NMOS tube MN5 and the source electrode of NMOS tube MN4 and NMOS tube MN3 respectively
Interconnection；The drain electrode of NMOS tube MN5 and the drain electrode of NMOS tube MN4 connect the source electrode of NMOS tube MN7 and the source electrode of NMOS tube MN6 respectively
And the drain interconnection of the drain electrode of NMOS tube MN5 and NMOS tube MN4；The drain electrode of NMOS tube MN7 and the drain electrode of NMOS tube MN6 connect respectively
Connect drain electrode and the drain interconnection of NMOS tube MN6 of the source electrode of NMOS tube MN9 and the source electrode of NMOS tube MN8 and NMOS tube MN7；NMOS
The drain electrode of pipe MN9 and the drain electrode of NMOS tube MN8 connect the source electrode of NMOS tube MN11 and the source electrode and NMOS of NMOS tube MN10 respectively
The drain electrode of pipe MN9 and the drain interconnection of NMOS tube MN8；The drain electrode of NMOS tube MN11 and the drain electrode of NMOS tube MN10 are connected respectively
The drain electrode of the source electrode of NMOS tube MN13 and the source electrode of NMOS tube MN12 and NMOS tube MN11 and the drain interconnection of NMOS tube MN10；
NMOS tube MN3, MN5, the grid of MN7, MN9, MN11 and MN13 connect respectively phase inverter inv17, inv18, inv19, inv20,
The output end of inv21 and inv22, the input of phase inverter inv17, inv18, inv19, inv20, inv21 and inv22 connects respectively
Meet Q0, Q1, Q2, Q3, Q4 and the Q5 during 6 forward-backward counters export 6 bit Q0-Q5；The drain electrode of NMOS tube MN13 with
The drain interconnection of NMOS tube MN12 and the grid of the drain electrode with PMOS MP2, one end of time adjustment electric capacity C1 and PMOS MP3
The grid of pole and NMOS tube MN14 links together, and the other end of time adjustment electric capacity C1 and the source electrode of NMOS tube MN14 connect
Ground, the source electrode of the source electrode connection PMOS MP2 of PMOS MP3 simultaneously connects supply voltage Vin, the grid and NMOS of PMOS MP2
The grid of pipe MN2, the grid of NMOS tube MN4, the grid of NMOS tube MN6, the grid of NMOS tube MN8, the grid of NMOS tube MN10
And the grid of NMOS tube MN12 link together and connect prime DCM hysteresis control circuits output system switching control signal
The drain electrode of in, PMOS MP3 connects the drain electrode of NMOS tube MN4 and as 6 output ends of binary system delay line；
Power tube drive circuit include two-way chain of inverters, all the way chain of inverters include be sequentially connected phase inverter ivn1~
When the self adaptation of the input connection DCM self-adaptive dead-time control circuit outputs of ivn6, phase inverter ivn1 adds optimal dead band
Between control signal PG, phase inverter ivn6 exports the grid that enhanced driving control signal PG0 is connected to PMOS power tubes M1；Separately
Chain of inverters includes the phase inverter ivn7~ivn12 being sequentially connected, the input connection DCM adaptive dead zones of phase inverter ivn7 all the way
The self adaptation of time control circuit output adds the control signal NG of optimal Dead Time, and phase inverter ivn6 exports enhanced driving
Control signal NG0 is connected to the grid of NMOS power tubes M2；In two-way chain of inverters, per each phase inverter length wide in all the way
Than being increased step by step as multiple with naturally low logarithm e successively, to obtain the driving force of maximum；
Zero cross detection circuit includes two zero passage detection modules, and a zero passage detection module is used to detect that Lx point voltages are changed into from negative
On the occasion of moment, including comparator COMP1 and phase inverter ivn13, comparator COMP1 negative input connection Lx points, positive level
Input end grounding, the inverted device ivn13 output Zero-cross comparator signals zd1 of output of comparator COMP1；Another zero passage detection mould
Block is used to detect in switching power converters normal work, after PMOS power tubes M1 is closed, the wink that NMOS power tubes M2 is opened
Between Lx points voltage condition, including comparator COMP2, phase inverter ivn14, sampling capacitance C_sample and by NMOS tube MN1
The transmission gate constituted with PMOS MP1, the source electrode of NMOS tube MN1 is interconnected with the source electrode of PMOS MP1 and is connected Lx points, NMOS tube
The drain interconnection of the drain electrode of MN1 and PMOS MP1 is simultaneously connected one end of sampling capacitance C_sample and the negative pole of comparator COMP2
Input, the grid of NMOS tube MN1 and the grid of PMOS MP1 connect phase inverter in power tube drive circuit chain of inverters respectively
The output NG1 of the ivn11 and electrode input end connection sampling capacitance C_ of the output NG2 of phase inverter ivn10, comparator COMP2
The other end of sample is simultaneously grounded, the inverted device ivn14 output Zero-cross comparator signals zd2 of output of comparator COMP2.
2. the control method of the circuit of DCM switching power converters controlling dead error time, its feature according to claim 1
It is：DCM self-adaptive dead-time control circuits meet for the system switching control signal in of input to be converted into two-way
DCM mode of operations, self adaptation add the control signal PG and NG of optimal Dead Time, wherein, using rest-set flip-flop RSFF1 with
The cooperation of the output signal zd1 of zero cross detection circuit, can realize that the two-way power tube for meeting DCM Schema control requirements drives letter
Number, and utilize dynamic deferred unit to coordinate with the output zd2 of zero cross detection circuit, be capable of self adaptation is PG, NG two-way power
The addition Dead Time of pipe drive signal self adaptation, in dynamic deferred unit, uses 6 binary system delay lines and 6 plus-minus meters
Number device is coordinated, and in the switching power converters course of work, after PMOS M1 is closed, Lx point voltages constantly decline, if
Lx points voltage is more than 0 when NMOS tube M2 is opened, and it is too small to represent Dead Time, then increase by 6 forward-backward counters and count, that is, increase
Dead Time；If when NMOS tube M2 is opened, Lx points voltage is less than 0, it is excessive to represent Dead Time, then reduce by 6 plus-minus countings
Device is counted, that is, reduce Dead Time, by such sampling comparative approach, is obtained when in dcm operating modes, power tube PMOS
The information of the Dead Time and between the unlatching of power NMOS tube is closed, it is single that the feedback of the information of Dead Time is returned into auto-adaptive time control
Unit, so that the binary system output of appropriate 6 forward-backward counters of adjustment, to cause that Dead Time obtains the adjustment of self adaptation, most
In an optimal Dead Time, power tube grid control signal is driven grading stabilization by the power tube that chain of inverters is constituted eventually
Row enhancing driving force, is finally used to control the switch of power tube, realizes that the controlling dead error time of self adaptation is taken in optimal position
Put without by being input into, output voltage and load current change influenceed, Dead Time is stable at optimal value always.
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