CN203352444U - High-efficiency step-down DC-DC converter - Google Patents
High-efficiency step-down DC-DC converter Download PDFInfo
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- CN203352444U CN203352444U CN 201320453001 CN201320453001U CN203352444U CN 203352444 U CN203352444 U CN 203352444U CN 201320453001 CN201320453001 CN 201320453001 CN 201320453001 U CN201320453001 U CN 201320453001U CN 203352444 U CN203352444 U CN 203352444U
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Abstract
The utility model relates to a high-efficiency step-down DC-DC converter. The converter comprises two parts, i.e. a power circuit and a control circuit. The power circuit part includes a power switch tube, a synchronous rectifier tube and a filtering and feedback circuit. The control circuit includes a current detection circuit, a gate-width control circuit, a logic control and gate drive circuit, a pulse-width modulation circuit, a dead-zone prediction circuit and a dead-zone circuit. The step-down DC-DC converter provided by the utility model is capable of stepping-down and effectively converting an unstable direct voltage into a stable direct voltage. When the DC-DC converter works in light-load conditions, the gate width control circuit changes the dimensions of the power switch tube and the synchronous rectifier tube, thereby reducing the drive loss in the power circuit and improving the light-load conversion efficiency. The dead zone prediction circuit detects and records the surplus dead-zone time in real time, and controls the length of the dead-zone time added for a switch signal by the dead-zone circuit, so that the dead-zone time is minimized, the conduction loss caused by the surplus dead-zone time is reduced, and the conversion efficiency of the system is improved.
Description
Technical field
The utility model belongs to the electronic circuit technology field, relates to analog integrated circuit.Be particularly related to a kind of efficient voltage reducing type DC-DC converter, mainly adopt grid width control technology and dead band Prediction and Control Technology to improve the conversion efficiency of system.
Background technology
The inner required voltage of supply power voltage in electronic product and electronic product is inconsistent is extremely common.A lot of portable sets adopt powered battery, and the output voltage of battery changes along with the length of service time of battery, so supply power voltage is not a constant voltage usually.The chip of electronic product inside needs a stable supply power voltage, power management chip just becomes the indispensable part of electronic product, and whether the quality of power management chip directly has influence on the technical performance index of electronic equipment and and work safe and reliable.
Buck type Switching Power Supply is the class in the DC-DC converter, and its basic function is: will input unsettled direct voltage step-down and be converted to more stable output dc voltage.When being heavy duty, its major advantage can arrive very high conversion efficiency.
There is parasitic capacitance in power switch pipe in side circuit, so handoff procedure in power tube conducting and shutoff, voltage and current on power tube is not desirable instantaneous saltus step, but the process of a rising or decline is arranged, and this is that parasitic capacitance due to switching tube discharges and recharges and causes.Parasitic capacitance has been introduced the driving loss during the course.This loss is directly proportional to parasitic capacitance value size and switching frequency size.For the maximum current that may occur in the load power circuit, usually select metal-oxide-semiconductor that breadth length ratio W/L is very large as power switch pipe, this just makes wide with metal-oxide-semiconductor and to grow up to the parasitic capacitance of direct ratio larger.Under the underloading condition, this part loss proportion highlights, and makes system conversion efficiency when underloading lower.And modern many portable set mosts of the time operate in the standby mode of low-power consumption, i.e. underloading pattern.So the conversion efficiency improved under the underloading condition extremely is necessary.
The utility model content
The utility model is mainly to solve the existing technical problem of prior art; Providing a kind of can be low voltage equipment by unsettled direct voltage step-down and is converted to efficiently the galvanic current pressure.When the DC-DC converter is operated under the underloading condition, device will be closed corresponding power switch pipe and synchronous rectifier, thereby reduces the driving loss in power circuit, improves a kind of efficient voltage reducing type DC-DC converter of underloading conversion efficiency.
It is to solve the existing technical problem of prior art that the utility model also has a purpose; Provide a kind of and can detect in real time unnecessary Dead Time, the line item of going forward side by side, then join the length of Dead Time in switching signal by controlling dead-zone circuit.Thereby minimize Dead Time, reduce the conduction loss that unnecessary Dead Time is introduced, improve a kind of efficient voltage reducing type DC-DC converter of system conversion efficiency.
Above-mentioned technical problem of the present utility model is mainly solved by following technical proposals:
A kind of efficient voltage reducing type DC-DC converter, is characterized in that, comprises power circuit and control circuit module (101); Wherein the input Vin of power circuit is the power input of DC-DC converter, and its output end vo ut is the power output end of DC-DC converter, the 5bit output V of control circuit module (101)
driveP<4:0>be connected respectively to the input of power circuit, i.e. the grid of 5 groups of metal-oxide-semiconductors in power switch pipe group SW, the 5bit output V of control circuit module (101)
driveN<4:0>be connected respectively to the input of power circuit, i.e. the grid of 5 groups of metal-oxide-semiconductors in power switch pipe group SR, the output V of power circuit
sWwith the input of control circuit module (101), be connected, the output Vfb of power circuit is connected with the input of control circuit module (101), the output V of power circuit
sWwith the input of control circuit module (101), be connected.
For this problem, the utility model adopts the grid width control technology, and according to the load current size of Real-Time Monitoring, judgement determines the channel width of power switch pipe.Make under the underloading condition, the parasitic capacitance of power switch pipe is less, thereby reduces to drive loss.
In addition, in order further to reduce the wastage, in present most power circuit, all adopt synchronous rectifier to replace traditional fly-wheel diode, because select suitable synchronous rectifier, its drain-source two ends are lower than the pressure drop of fly-wheel diode two ends.Under and application conditions that output voltage is lower large at load current, do like this and can effectively improve conversion efficiency.But to strictly control the not conducting simultaneously at work of synchronous rectifier and power switch pipe, not so can cause unnecessary large current surge, affect circuit stability.So be necessary for the dead band that the control signal of two switching tubes adds.In Dead Time, synchronous rectifier and power switch pipe all turn-off, now, the body diode of synchronous rectifier is forced to conducting, the pressure drop at sync-body diode two ends is the pressure drop at rectifying tube drain-source two ends, this pressure drop is also the drain-source pressure drop while being greater than the synchronous rectifier conducting, so this section Dead Time is the smaller the better.But traditional dead band control circuit is that to add the fixedly method of Dead Time, the Dead Time added to switch controlling signal be the Dead Time of the maximum that needs in circuit working, to guarantee circuit, under worst case, also can work.But this can make system when normal operation, introduces unnecessary Dead Time, introduces too much unnecessary conduction loss.
For this problem, the utility model adopts the dead band Prediction and Control Technology, detects the Dead Time of this switch periods, dynamically controls the Dead Time length that next cycle need to add, thereby the Dead Time in the minimization system course of work, and then the conduction loss of reduction synchronous rectifier.
Comprise power switch pipe group SW, synchronous rectifier group SR and filtering feedback circuit (102) at the above-mentioned described power circuit of a kind of efficient voltage reducing type DC-DC converter; The input of the drain terminal of the drain terminal of described power switch pipe group SW, power switch pipe group SW and filtering feedback circuit (10) is connected to the output V of power circuit jointly
sW; Described power switch pipe group SW comprises five P type metal-oxide-semiconductors that breadth length ratio is identical, and the source electrode of five P type metal-oxide-semiconductors all is connected with power input Vin, and drain electrode all is connected to the output V of power circuit
sW, grid respectively with the input V of power circuit
driveP<4:0>be connected; Described synchronous rectifier group SR comprises five N-type metal-oxide-semiconductors that breadth length ratio is identical, and the drain electrode of five power switch pipes all is connected to the output V of power circuit
sW, source electrode all is connected to ground, grid respectively with the input V of power circuit (102)
driveN<4:0>be connected.
Comprise inductance L, capacitor C, resistance R 1 and R2 at above-mentioned a kind of efficient voltage reducing type DC-DC described filtering feedback circuit of converter (102); Wherein, an end of inductance L is connected to the output V of power circuit
sW; The other end is connected to the power output end Vout of DC-DC converter; Capacitor C is connected between output port of power source Vout and ground; Resistance R 1 and R2 are connected in series between output port of power source Vout and ground, draw the output Vfb of power circuit in the middle of R1 and R2.
Comprise current detection circuit (103), grid width control circuit (104), logic control and gate driver circuit (105), pulse width modulation circuit (106), dead-zone circuit (107) and dead band prediction circuit (108) in above-mentioned a kind of efficient voltage reducing type DC-DC described control circuit module of converter (101); The input of described current detection circuit (103) is the input V of control circuit module (101)
sW, the output Vsense of current detection circuit 103 is connected to the input of grid width control circuit (104), two input D of grid width control circuit (104)
sWand D
sRbe connected to the output of dead-zone circuit (107), the two-way 5bit output G of grid width control circuit (104)
sW<4:0>and G
sR<<4:0>be connected respectively to the input of logic control and gate driver circuit (105), the two-way 5bit output of logic control and gate driver circuit (105) is the two-way 5bit output V of control circuit module (101)
driveP<4:0>and V
driveN<4:0>; The input of pulse width modulation circuit (106) is the input Vfb of control circuit module (101), the output of pulse width modulation circuit (106) is connected with the input Vpwm of dead-zone circuit (107), output Dsw and the D of dead-zone circuit (107)
sRbe connected respectively to the input of grid width control circuit (104), the two-way eight 8bit input CTL_SW<7:0 of dead-zone circuit (107)>and CTL_SR<7:0 dead band prediction circuit (108) output that is connected to, two inputs of dead band prediction circuit (108) are respectively the input V of control circuit module (101)
sWa road output voltage V with logic control and gate driver circuit (105)
driveN0.
Comprise that at above-mentioned a kind of efficient voltage reducing type DC-DC described grid width control circuit of converter (104) reference voltage electronic circuit (301), four comparator com1～com4 and logic subcircuit (302) form, the normal phase input end of four comparators all is connected with the input Vsense of grid width control circuit (104), the inverting input of four comparators is connected with the output Vref1～Vref4 of reference voltage electronic circuit (301) respectively, the input D of the output Vcom1_out～Vcom4_out of four comparators and grid width control circuit (104)
sWand D
sRbe the input of logic subcircuit (302), the two-way 5bit output G of logic subcircuit (302)
sW<4:0>and G
sR<4:0>be the output of grid width control circuit (104).
Comprise two dead band passages at above-mentioned a kind of efficient voltage reducing type DC-DC converter institute's dead-zone circuit (107): SW passage group (501) and SR passage group (502), two passages are connected side by side, input is the input Vpwm of dead-zone circuit (107), and output is the output D of dead-zone circuit (107)
sWand D
sR;
Described SW passage group (501) comprise the first delay circuit (503), comparator com_SW, with door and_SW and not gate Not_SW; The input Vpwm of dead-zone circuit (107) is connected with the input of the first delay circuit (503), the output of the first delay circuit (503) is connected to the normal phase input end of comparator com_SW, the output of comparator com_SW is connected to the input with door and_SW, be connected to the input of not gate Not_SW with the output of door and_SW, the output of not gate Not_SW is the output D of dead-zone circuit (107)
sW;
Described SR passage group (502) comprise not gate Not_SR, the second delay circuit (504), comparator com_SR and with door and_SR; The input of the input Vpwm NAND gate Not_SR of dead-zone circuit (107) is connected, the output of not gate Not_SR is connected with the input of delay circuit second (504), the output of the second delay circuit (504) is connected to the normal phase input end of comparator com_SR, the output of comparator com_SR is connected to the input with door and_SR, with the output of door and_SR, is the output D of dead-zone circuit (107)
sR.
Comprise a NOR gate Nor, delay circuit (601), the first shaping circuit (602), the second shaping circuit (603), the first counter (604) and the second counter (605) at above-mentioned a kind of efficient voltage reducing type DC-DC converter described dead band prediction circuit (108); Two input V of dead band prediction circuit (108)
sWand V
driveN0two inputs of ANDORNOTgate Nor are connected, simultaneously, and input V
sWalso with the input of the first shaping circuit (602), be connected, input V
driveN0also with the input of the second shaping circuit 603, be connected, the output of the first shaping circuit (602) is connected to the input end of clock of the first counter (604), and the output of the second shaping circuit (603) is connected to the input end of clock of the second counter (605); The output of NOR gate Nor is connected with the input of delay circuit (601), the data input pin of the first counter (604) and the second counter (605) is connected with the output Delay of delay circuit (601), output CTL_SW<the 7:0 of the 8bit output of the first counter (604) and dead band prediction circuit (108)>be connected, the output CTL_SR<7:0 of the 8bit output of the second counter (605) and dead band prediction circuit (108)>be connected.
Therefore, the utlity model has following advantage: 1. can be low voltage equipment by unsettled direct voltage step-down and be converted to efficiently galvanic current and press.When the DC-DC converter is operated under the underloading condition, device will be closed corresponding power switch pipe and synchronous rectifier, thereby reduces the driving loss in power circuit, improves the underloading conversion efficiency.2. can detect in real time unnecessary Dead Time, the line item of going forward side by side, then join the length of Dead Time in switching signal by two-way 8bit Data Control dead-zone circuit.Thereby minimize Dead Time, reduce the conduction loss that unnecessary Dead Time is introduced, improve the system conversion efficiency.
The accompanying drawing explanation
The circuit structure block diagram of the high efficiency DC-DC converter of Fig. 1.
Fig. 2 power circuit structure chart.
The structured flowchart of Fig. 3 grid width control circuit 104.
The judgement waveform schematic diagram whether Fig. 4 power switch tube S W1 enables.
Fig. 5 dead-zone circuit structure chart.
The structured flowchart of Fig. 6 dead band prediction circuit.
The work wave schematic diagram of each signal in Fig. 7 dead band prediction circuit and dead-zone circuit.
Embodiment
Below by embodiment, and by reference to the accompanying drawings, the technical solution of the utility model is described in further detail.
Embodiment:
Below in conjunction with drawings and Examples, the utility model is described in further detail.
Buck DC-DC converter in the utility model comprises power circuit and control circuit 101 two parts.Referring to Fig. 1, the circuit beyond control circuit 101 is power circuit.
Referring to Fig. 1, the topology of power circuit is voltage-dropping type.Include power switch tube S W, synchronous rectifier SR and filtering feedback circuit 102.The input Vin of power circuit is the power input of DC-DC converter, and its output end vo ut is the power output end of DC-DC converter.
Referring to Fig. 2, above-mentioned power switch tube S W is by 5 P type metal-oxide-semiconductors that breadth length ratio is identical: SW4～SW0 forms side by side.The source electrode of 5 P type metal-oxide-semiconductors all is connected with power input Vin, and drain electrode all is connected to switching node Vsw, grid respectively with the output port V of control circuit 101
driveP<4:0>be connected.Equally, above-mentioned synchronous rectifier SR is by 5 N-type metal-oxide-semiconductors that breadth length ratio is identical: SR4～SR0 forms side by side.The drain electrode of 5 N-type metal-oxide-semiconductors all is connected to switching node Vsw, and source electrode all is connected to ground, grid respectively with the output port V of control circuit 101
driveN<4:0>be connected.For guaranteeing the circuit normal operation, SW0 and SR0 conducting all the time, SW4～SW1 and SR4～SR1 participates in the judgement whether circuit working depends on 104 pairs of loading conditions of grid width control circuit.When converter is operated in stage of output current minimum, SW4～SW1 and SR4～SR1 are all the time in off state.When converter is operated in stage of output current maximum, SW4～SW1 and SR4～SR1 all work, and ON time is determined by the pulse duration of grid control signal.
Above-mentioned filtering feedback circuit 102 includes inductance L, capacitor C
out, resistance R 1 and R2.Wherein an end of inductance L is connected to switching node Vsw, and the other end is connected to the power output end Vout of DC-DC variator.Capacitor C
outbe connected between output port Vout and ground, resistance R 1 and R2 are connected in series between output port and ground, the input of pulse width modulation module in the output Vfb of R1 and R2 centre is connected to control circuit 101.
Above-mentioned control circuit 101 adopts pulse-width-modulated mode.Referring to Fig. 1, control circuit 101 includes current detection circuit 103, grid width control circuit 104, logic control and gate driver circuit 105, pulse width modulation circuit 106, dead-zone circuit 107 and dead band prediction circuit 108 and forms.
Above-mentioned current detection circuit 103 detects in real time by the size of current of power switch pipe, and be converted to voltage signal, and by the maintenance of sampling of the detected value of power switch pipe conduction period, thereby obtain the detection signal Vsense of reflected load size of current, then be input to grid width control circuit 104.The input of current detection circuit 103 is connected to the switching node Vsw of power circuit, and output Vsense is connected to the input Vsense of grid width control circuit 104.
Above-mentioned grid width control circuit 104 is for controlling the number arranged side by side of external power pipe.Make power tube can bear that respective negative is current-carrying has a less channel dimensions simultaneously, so just dynamically reduced the grid parasitic capacitance of power switch pipe, thereby reduced the driving loss under the underloading condition, obviously improve the light-load efficiency of system.Referring to Fig. 3, grid width control circuit 104 is comprised of reference voltage circuit 301, four comparator com1～com4 and logic subcircuit 302.The load current detection signal that Vsense is the current detection circuit input, four reference voltage V ref1～Vref4 that Vsense provides by four comparator com1～com4 and reference voltage circuit 301 respectively compare, and comparative result determines respectively in the metal-oxide-semiconductor SW of power circuit and SR whether SW4～SW1 and SR4～SR1 participate in circuit working.For the pipe of working, the square-wave signal D that the pulse duration that its control signal is dead-zone circuit output is modulated
sWand D
sR.The deterministic process whether 104 couples of power switch tube S W1 of grid width control circuit work can be referring to Fig. 4.During t1～t2, Vsense is higher than Vref1, and Vcom1_out is high level, is equivalent to SW1 and enables, and illustrates that the load current size needs SW1 to join the transmission work of electric current.Through the processing of logic subcircuit, V
driveP1during t1～t2, be the square-wave signal that pulse duration is modulated, and V in during t0～t1 and t2～t3
driveP1be always high level, SW1 turn-offs.In like manner, SW4～SW2 and SR4～SR1 determine V in a comparable manner
driveP<4:2>and V
driveN<4:1>waveform.For guaranteeing the circuit normal operation, SW0 and SR0 conducting all the time, so D
sWand D
sRdirectly transfer G to
sW0and G
sR0output to logic control and drive circuit 105, finally be converted into the grid control signal V of SW0 and SR0
driveP0and V
driveN0.
Gate level circuit and inverter that above-mentioned logic control and gate driver circuit 105 are commonly used by some form, and are mainly used in strengthening the driving force of switching signal, and its input signal is two-way 5bit data G
sW<4:0>and G
sR<4:0>; Two-way 5bit output signal V
driveP<4:0>and V
driveN<4:0>directly drive corresponding power switch pipe and synchronous rectifier.
Above-mentioned pulse width modulation circuit 106, according to the fixing square-wave signal of the modulation pulsewidth of the output voltage feedback signal Vfb in power circuit, obtains adding Dead Time switching signal before, i.e. pulse width modulating signal Vpwm.The input Vfb that the input of pulse width modulation circuit 106 is control circuit, output Vpwm is connected with the input of dead-zone circuit 107.
Above-mentioned dead-zone circuit 107, for add the Dead Time of certain-length to switching signal, includes two passage groups: SW passage group and SR passage group are postponed the rising edge of Vpwm and trailing edge respectively.Be exactly Dead Time this period time of delay, and two-way 8bit data CTL_SW<7:0 that time of delay, length was exported by dead band prediction circuit 108 control with CTL_SR<7:0.Referring to Fig. 6,501 is SW passage group, includes delay circuit 503, comparator com_SW, forms with door and_SW and not gate Not_SW.502 is SW passage group, includes not gate Not_SR, delay circuit 504, comparator com_SR and forms with door and_SR.Delay circuit 503 is by electric capacity R
sW, capacitor C
sW0～C
sW7form capacitor C with K switch 0～K7
sW0～C
sW7with K switch 0～K7, connect respectively, the conducting of K0～K7 and the 8bit data CTL_SW<7:0 turn-offed by prediction circuit 105 outputs>control.Capacitor C when the K0 conducting
sW0and link delay circuit, thus increased the time constant of delay circuit, make increase time of delay, finally increased the Dead Time of switching signal.In like manner, the working method of K1～K7 is also that similarly in K0～K7, the switch of conducting is more, and the Dead Time added in switching signal is longer.The inhibit signal of delay circuit 503 output after comparator com_SW shaping with Vpwm signal phase with, to eliminate the impact of the first delay circuit 503 on Vpwm signal trailing edge.Again after not gate not_SW carries out logical synchronization, obtain adding the switching signal D in dead band with the signal of door and_SW output
sW.The operation principle of SR passage is also similar, just not gate Not_SR be added to delay circuit before, become rising edge for the trailing edge by Vpwm.Finally obtain adding the switching signal D in dead band
sR.
Above-mentioned dead band prediction circuit 108 detects the dead band that switching signal existed in this cycle.Then the optimum dead zone time length under actual operating conditions is recorded to counter, the two-way 8bit data of counter output output to dead-zone circuit 107.Referring to Fig. 5, dead band prediction circuit 108 comprises that NOR gate Nor, delay circuit 601, the first shaping circuit 602, the second shaping circuit 603, the first counter 604 and the second counter 605 form.Two input signals are respectively the gate drive voltage V of node voltage Vsw and the 0th synchronous rectifier SR0
driveN0.Vsw and V
driveN0carry out or non-after obtain Nor_out, Nor_out is Delay after delay circuit 601.Then constantly, if Delay is high level, the first counter 604 subtracts 1 to the rising edge after the Vsw shaping, otherwise the first counter 604 adds 1; Equally, at V
driveN0rising edge after shaping detects inhibit signal Delay, if Delay is high level, the second counter 605 subtracts 1, otherwise the second counter 605 adds 1.When the circuit steady operation, the first counter 604 and the second counter 605 record respectively the optimum dead zone time span that should add of Vpwm signal at rising edge and falling edge like this.
In dead band prediction circuit 108 and dead-zone circuit 107, the work wave of each signal can be referring to Fig. 7, and Vpwm is the pulse width modulating signal of pulse width modulation module output.V
driveP0and V
driveN0respectively D
sWand D
sRsignal after the enhancing driving force.Vsw is node voltage.Nor_out is the output waveform of NOR gate Nor in the prediction circuit of dead band, and in display switch signal current period, there is situation in dead band.Dead-zone circuit 107, according to the data in the first counter 604, has added dead band t at the Vpwm rising edge
d1become D
sW; Data according in the second counter 605, added dead band t at the Vpwm trailing edge
d2become D
sR.Vsw and V in dead band prediction circuit 108
driveN0carry out or non-after the Nor_out that obtains, the pulse in Nor_out is the dead band detected.1., 3. and 5. dead band wherein is that the SW via set in dead-zone circuit 107 is controlled, and 2. and 4. dead band is the SR via set control in dead-zone circuit 107.Delay is the output waveform of Nor_out after delay circuit 601.At Vsw rising edge place, Delay is high level, and the first counter 604 in dead-zone circuit 107 can subtract 1, this means that the time constant of delay circuit in dead-zone circuit 107 reduces.So in Nor_out, the dead band of T2 is 3. 1. narrow than the dead band of T1, one-period reduces some Dead Times like this, until Dead Time is when just very few, as dead band 2., waveform after postponing can't detect in the clock hopping edge of counter, now the second counter 605 can add 1, and Dead Time increases.So the dead band at T2 in the cycle is 4. 2. wide than the dead band in T1 cycle.Dynamic prediction is adjusted Dead Time length like this, makes dead band length in switching signal in optimum length, has reduced unnecessary dead band waste.Such dead band prediction circuit is not subject to the impact of other conditions of work in circuit, only is concerned about whether dead band length minimizes.
The utility model provides a kind of high efficiency DC-DC converter, can and be converted to efficiently more stable output dc voltage by the unstable direct voltage step-down of input.Control circuit 101 in this device and the power switch tube S W in power circuit and SR can be integrated in the chip of mancarried electronic aid, and the available discrete component of other parts of power circuit is placed on outside chip.
Specific embodiment described herein is only to the explanation for example of the utility model spirit.The utility model person of ordinary skill in the field can make various modifications or supplements or adopt similar mode to substitute described specific embodiment, but can't depart from spirit of the present utility model or surmount the defined scope of appended claims.
Claims (7)
1. an efficient voltage reducing type DC-DC converter, is characterized in that, comprises power circuit and control circuit module (101); Wherein the input Vin of power circuit is the power input of DC-DC converter, and its output end vo ut is the power output end of DC-DC converter, the 5bit output V of control circuit module (101)
driveP<4:0>be connected respectively to the input of power circuit, i.e. the grid of 5 groups of metal-oxide-semiconductors in power switch pipe group SW, the 5bit output V of control circuit module (101)
driveN<4:0>be connected respectively to the input of power circuit, i.e. the grid of 5 groups of metal-oxide-semiconductors in power switch pipe group SR, the output V of power circuit
sWwith the input of control circuit module (101), be connected, the output Vfb of power circuit is connected with the input of control circuit module (101), the output V of power circuit
sWwith the input of control circuit module (101), be connected.
2. a kind of efficient voltage reducing type DC-DC converter according to claim 1, is characterized in that, described power circuit comprises power switch pipe group SW, synchronous rectifier group SR and filtering feedback circuit (102); The input of the drain terminal of the drain terminal of described power switch pipe group SW, power switch pipe group SW and filtering feedback circuit (10) is connected to the output V of power circuit jointly
sW; Described power switch pipe group SW comprises five P type metal-oxide-semiconductors that breadth length ratio is identical, and the source electrode of five P type metal-oxide-semiconductors all is connected with power input Vin, and drain electrode all is connected to the output V of power circuit
sW, grid respectively with the input V of power circuit
driveP<4:0>be connected; Described synchronous rectifier group SR comprises five N-type metal-oxide-semiconductors that breadth length ratio is identical, and the drain electrode of five power switch pipes all is connected to the output V of power circuit
sW, source electrode all is connected to ground, grid respectively with the input V of power circuit (102)
driveN<4:0>be connected.
3. a kind of efficient voltage reducing type DC-DC converter according to claim 2, is characterized in that, described filtering feedback circuit (102) comprises inductance L, capacitor C, resistance R 1 and R2; Wherein, an end of inductance L is connected to the output V of power circuit
sW; The other end is connected to the power output end Vout of DC-DC converter; Capacitor C is connected between output port of power source Vout and ground; Resistance R 1 and R2 are connected in series between output port of power source Vout and ground, draw the output Vfb of power circuit in the middle of R1 and R2.
4. a kind of efficient voltage reducing type DC-DC converter according to claim 3, it is characterized in that, described control circuit module (101) comprises current detection circuit (103), grid width control circuit (104), logic control and gate driver circuit (105), pulse width modulation circuit (106), dead-zone circuit (107) and dead band prediction circuit (108); The input of described current detection circuit (103) is the input V of control circuit module (101)
sW, the output Vsense of current detection circuit 103 is connected to the input of grid width control circuit (104), two input D of grid width control circuit (104)
sWand D
sRbe connected to the output of dead-zone circuit (107), the two-way 5bit output G of grid width control circuit (104)
sW<4:0>and G
sR<<4:0>be connected respectively to the input of logic control and gate driver circuit (105), the two-way 5bit output of logic control and gate driver circuit (105) is the two-way 5bit output V of control circuit module (101)
driveP<4:0>and V
driveN<4:0>; The input of pulse width modulation circuit (106) is the input Vfb of control circuit module (101), the output of pulse width modulation circuit (106) is connected with the input Vpwm of dead-zone circuit (107), output Dsw and the D of dead-zone circuit (107)
sRbe connected respectively to the input of grid width control circuit (104), the two-way 8bit input CTL_SW<7:0 of dead-zone circuit (107)>and CTL_SR<7:0 dead band prediction circuit (108) output that is connected to, two inputs of dead band prediction circuit (108) are respectively the input V of control circuit module (101)
sWa road output voltage V with logic control and gate driver circuit (105)
driveN0<4:0>.
5. a kind of efficient voltage reducing type DC-DC converter according to claim 4, it is characterized in that, described grid width control circuit (104) comprises reference voltage electronic circuit (301), four comparator com1～com4 and logic subcircuit (302) form, the normal phase input end of four comparators all is connected with the input Vsense of grid width control circuit (104), the inverting input of four comparators is connected with the output Vref1～Vref4 of reference voltage electronic circuit (301) respectively, the input D of the output Vcom1_out～Vcom4_out of four comparators and grid width control circuit (104)
sWand D
sRbe the input of logic subcircuit (302), the special output G of the two-way 5bit of logic subcircuit (302)
sW<4:0>and G
sR<4:0>be the output of grid width control circuit (104).
6. a kind of efficient voltage reducing type DC-DC converter according to claim 5, it is characterized in that, institute's dead-zone circuit (107) comprises two dead band passages: SW dead band passage (501) and SR dead band passage (502), two passages are connected side by side, input is the input Vpwm of dead-zone circuit (107), and output is the output D of dead-zone circuit (107)
sWand D
sR;
Described SW passage group (501) comprise the first delay circuit (503), comparator com_SW, with door and_SW and not gate Not_SW; The input Vpwm of dead-zone circuit (107) is connected with the input of the first delay circuit (503), the output of the first delay circuit (503) is connected to the normal phase input end of comparator com_SW, the output of comparator com_SW is connected to the input with door and_SW, be connected to the input of not gate Not_SW with the output of door and_SW, the output of not gate Not_SW is the output D of dead-zone circuit (107)
sW;
Described SR passage group (502) comprise not gate Not_SR, the second delay circuit (504), comparator com_SR and with door and_SR; The input of the input Vpwm NAND gate Not_SR of dead-zone circuit (107) is connected, the output of not gate Not_SR is connected with the input of delay circuit second (504), the output of the second delay circuit (504) is connected to the normal phase input end of comparator com_SR, the output of comparator com_SR is connected to the input with door and_SR, with the output of door and_SR, is the output D of dead-zone circuit (107)
sR.
7. a kind of efficient voltage reducing type DC-DC converter according to claim 6, it is characterized in that, described dead band prediction circuit (108) comprises a NOR gate Nor, delay circuit (601), the first shaping circuit (602), the second shaping circuit (603), the first counter (604) and the second counter (605); Two input V of dead band prediction circuit (108)
sWand V
driveN0two inputs of ANDORNOTgate Nor are connected, simultaneously, and input V
sWalso with the input of the first shaping circuit (602), be connected, input V
driveN0also with the input of the second shaping circuit 603, be connected, the output of the first shaping circuit (602) is connected to the input end of clock of the first counter (604), and the output of the second shaping circuit (603) is connected to the input end of clock of the second counter (605); The output of NOR gate Nor is connected with the input of delay circuit (601), the data input pin of the first counter (604) and the second counter (605) is connected with the output Delay of delay circuit (601), output CTL_SW<the 7:0 of the 8bit output of the first counter (604) and dead band prediction circuit (108)>be connected, the output CTL_SR<7:0 of the 8bit output of the second counter (605) and dead band prediction circuit (108)>be connected.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320453001 CN203352444U (en) | 2013-07-26 | 2013-07-26 | High-efficiency step-down DC-DC converter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320453001 CN203352444U (en) | 2013-07-26 | 2013-07-26 | High-efficiency step-down DC-DC converter |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103368394A (en) * | 2013-07-26 | 2013-10-23 | 武汉大学 | Efficient step-down DC-DC (Direct Current-Direct Current) converter |
| CN105024529A (en) * | 2015-07-28 | 2015-11-04 | 周海波 | Intelligent power module adaptive dead-time generation circuit and application method |
| CN107026561A (en) * | 2016-02-01 | 2017-08-08 | 华润矽威科技（上海）有限公司 | Gate driving circuit and method |
| CN108847772A (en) * | 2018-07-17 | 2018-11-20 | 合肥工业大学 | A kind of Buck converter based on adaptive size selection |
| CN112816804A (en) * | 2019-11-15 | 2021-05-18 | 中车株洲电力机车研究所有限公司 | High-integration pulse testing device |
-
2013
- 2013-07-26 CN CN 201320453001 patent/CN203352444U/en not_active Withdrawn - After Issue
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103368394A (en) * | 2013-07-26 | 2013-10-23 | 武汉大学 | Efficient step-down DC-DC (Direct Current-Direct Current) converter |
| CN103368394B (en) * | 2013-07-26 | 2016-05-11 | 武汉大学 | A kind of efficient voltage reducing type DC-DC converter |
| CN105024529A (en) * | 2015-07-28 | 2015-11-04 | 周海波 | Intelligent power module adaptive dead-time generation circuit and application method |
| CN105024529B (en) * | 2015-07-28 | 2018-08-31 | 金学成 | A kind of intelligent power module adaptive dead zone time generation circuit and application process |
| CN107026561A (en) * | 2016-02-01 | 2017-08-08 | 华润矽威科技（上海）有限公司 | Gate driving circuit and method |
| CN108847772A (en) * | 2018-07-17 | 2018-11-20 | 合肥工业大学 | A kind of Buck converter based on adaptive size selection |
| CN112816804A (en) * | 2019-11-15 | 2021-05-18 | 中车株洲电力机车研究所有限公司 | High-integration pulse testing device |
| CN112816804B (en) * | 2019-11-15 | 2024-04-26 | 中车株洲电力机车研究所有限公司 | Pulse testing device with high integration level |
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