CN114337233A - Self-adaptive dead time control circuit suitable for GaN driving chip - Google Patents

Abstract

The invention discloses a self-adaptive dead time control circuit suitable for a GaN driving chip, and belongs to the field of switching power supplies. Generating a control signal by detecting the voltage change condition of a switch node SW in real time, and delaying a high-side or low-side input control signal, namely delaying the low-side input control signal at the falling edge of the switch node SW and delaying the high-side input control signal at the rising edge of the switch node SW so as to generate dead time and realize dead time optimization; the problem of great reverse conduction loss caused by the fact that the traditional fixed dead time is too long is solved, and conversion efficiency is improved.

Description

Self-adaptive dead time control circuit suitable for GaN driving chip

Technical Field

The invention relates to the technical field of switching power supplies, in particular to a self-adaptive dead-time control circuit suitable for a GaN driving chip.

Background

Compared with the traditional Si power device, the gallium nitride power device (GaN) has lower on-resistance, lower grid charge and smaller device size under the same withstand voltage, and can better meet the requirements of the switching power supply on continuous development towards high frequency, high efficiency, small volume and light weight. However, since the GaN power device has some special physical characteristics, such as small gate withstand voltage, narrow gate safe operating voltage range, low threshold voltage, large reverse conducting voltage, and sensitivity to parasitic factors, the GaN power device cannot be directly driven by the conventional driving circuit, and a driving chip suitable for the GaN power device needs to be redesigned.

For BUCK power supplies, to prevent the high and low side power transistors from turning on at the same time, dead time is introduced, during which the high and low side power transistors turn off at the same time. Fig. 1 shows a dead time control topology structure of a conventional half-bridge driving circuit, and it can be known from fig. 1 that the conventional dead time is set as a fixed dead time, but since the closing and opening processes of the GaN power device are affected by the variation of parameters such as load conditions, current, voltage, and temperature, in order to ensure that the high-side and low-side power devices do not have the shoot-through phenomenon under all operating conditions, the dead time is set according to the worst operating environment conditions. Therefore, the dead time is set to be too long for most load conditions, and the reverse conduction voltage of the GaN power device is large, so that excessive reverse conduction loss is generated, and the conversion efficiency of the switching power supply is reduced. In addition, the reverse conduction loss is proportional to the reverse conduction time, and the larger the dead time is, the larger the reverse conduction time is, so that the dead time is adjusted according to the load condition to reduce the reverse conduction time and further reduce the reverse conduction loss.

In summary, since the optimal dead time under different load current and input voltage conditions is different, it is necessary to design a dead time control circuit adaptive to the load current and input voltage conditions.

Disclosure of Invention

The invention aims to provide a self-adaptive dead time control circuit suitable for a GaN driving chip, and the self-adaptive dead time control circuit is used for solving the problem of large reverse conduction loss caused by overlong traditional fixed dead time.

In order to solve the technical problem, the invention provides a self-adaptive dead-time control circuit suitable for a GaN driving chip, which comprises a zero-crossing detection module and a dead-time control module;

the zero-crossing detection module detects the voltage change condition of the switch node SW in real time and generates a control signal to the dead zone control module;

the dead zone control module delays the control signal input by the high side or the low side, namely the control signal input by the low side is delayed at the falling edge of the switch node SW, and the control signal input by the high side is delayed at the rising edge of the switch node SW, so that dead zone time is generated, and dead zone optimization is realized.

Optionally, the zero-crossing detection module includes a bias current I_BIASA first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first diode D₁A second diode D₂Resistance R₁And a voltage comparator COMP;

wherein the bias current I_BIASOne end of the first PMOS transistor is simultaneously connected with the drain end and the gate end of a third PMOS transistor MP3, the gate end of a second PMOS transistor MP2 and the gate end of a first PMOS transistor MP1, and the bias current I_BIASThe other end of the first and second electrodes is grounded;

the source ends of the first PMOS tube MP1, the second PMOS tube MP2 and the third PMOS tube MP3 are all connected with VDD; the drain terminal of the first PMOS transistor MP1 is connected to the node V₁The drain terminal of the second PMOS transistor MP2 is connected to the node V₂(ii) a Resistance R₁Is connected to node V₁The other end is connected with a first diode D₁The first diode D₁Is connected to the switch node SW, wherein the node V₁Is controlled by a bias current I_BIASThe width-length ratio of the first PMOS tube MP1, the width-length ratio of the third PMOS tube MP3, and R₁Resistance value, first diode D₁The forward conducting voltage and the voltage of the switch node SW jointly determine, and the second diode D₂Anode connection node V of₂Cathode is grounded, wherein node V₂Is supplied by a second diode D₂The forward turn-on voltage of;

positive input terminal node V of voltage comparator COMP₂Negative input terminal connected to node V₁Output terminal is connected to node V_senceFor comparing nodes V₁And V₂Voltage of said node V₁Is varied with the voltage at the switch node SW, when V is₁Voltage of (V) is large₂When, V_senceAnd outputting a low level, and otherwise, outputting a high level.

Optionally, the first diode D₁And the second diode D₂All are reverse bias high voltage resistant devices, and the forward conduction voltages are equal.

Optionally, the device sizes of the first PMOS transistor MP1 and the second PMOS transistor MP2 are set to be the same.

Optionally, the dead zone control module includes a first D flip-flop D _ FF1, a first D flip-flop D _ FF2, a first 1-out-of-2 selector MUX1, a second 1-out-of-2 selector MUX2, a first buffer BUF1, and a second buffer BUF 2;

the trigger port Clk of the first D flip-flop D _ FF1 is connected with the node V_senceThe input port D is connected with a low-side input signal LI,the output port Q is connected with the port 0 of the first 2-to-1 selector MUX 1; the port 1 of the first 2-to-1 selector MUX1 is connected with a low-side input signal LI, the selection port S is connected with a high-side input signal HI, and the output port is connected with the input end of a first buffer BUF 1; an output termination node LO of the first buffer BUF 1;

the trigger port Clk of the second D flip-flop D _ FF2 is connected with the node V_senceThe input port D is connected with the low-side input signal HI, and the output port Q is connected with the port 0 of the second 1-out-of-2 selector MUX 2; the port 1 of the second 2-to-1 selector MUX2 is connected with the low-side input signal HI, the selection port S is connected with the high-side input signal LI, and the output port is connected with the input end of the second buffer BUF 2; the output of said second buffer BUF2 terminates at the node HO.

In the self-adaptive dead time control circuit suitable for the GaN driving chip, the voltage change condition of the switch node SW is detected in real time to generate a control signal, and the high-side or low-side input control signal is delayed, namely, the low-side input control signal is delayed at the falling edge of the switch node SW, and the high-side input control signal is delayed at the rising edge of the switch node SW, so that dead time is generated, and dead time optimization is realized; the problem of great reverse conduction loss caused by the fact that the traditional fixed dead time is too long is solved, and conversion efficiency is improved.

Drawings

FIG. 1 is a diagram of a conventional half-bridge drive circuit dead-time control topology;

FIG. 2 is a topological diagram of an adaptive dead time control circuit suitable for a GaN driver chip according to the present invention;

FIG. 3 is a schematic waveform diagram of the working principle of the adaptive dead time control circuit suitable for the GaN driver chip.

Detailed Description

The adaptive dead time control circuit for GaN driver chips according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

The invention provides an adaptive dead time control circuit suitable for a GaN driving chip, which has a structure shown in FIG. 2, and controls the delay of a high-side or low-side input signal by carrying out zero-crossing detection on the voltage of an open joint point SW so as to realize dead time control. Dead time optimization is achieved by delaying the low side input control signal at the falling edge of the switch node SW and by delaying the high side input control signal at the rising edge of the switch node SW to create dead time.

The self-adaptive dead-time control circuit suitable for the GaN driving chip comprises a zero-crossing detection module and a dead-time control module; the zero-crossing detection module comprises a bias current I_BIASA first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first diode D₁A second diode D₂Resistance R₁And a voltage comparator COMP. The first diode D₁And the second diode D₂The devices are reverse biased high-voltage tolerant devices and have equal forward turn-on voltages, and the device sizes (i.e., width-to-length ratios) of the first PMOS transistor MP1 and the second PMOS transistor MP2 are set to be the same. The dead zone control module includes a first D flip-flop D _ FF1, a first D flip-flop D _ FF2, a first 1-out-of-2 selector MUX1, a second 1-out-of-2 selector MUX2, a first buffer BUF1, and a second buffer BUF 2. The bias current I_BIASOne end of the first PMOS transistor is simultaneously connected with the drain end and the gate end of a third PMOS transistor MP3, the gate end of a second PMOS transistor MP2 and the gate end of a first PMOS transistor MP1, and the bias current I_BIASAnd the other end of the same is grounded. The source ends of the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are all connected to VDD, and the drain end of the first PMOS transistor MP1 is connected to a node V₁The drain terminal of the second PMOS transistor MP2 is connected to the node V₂(ii) a Resistance R₁Is connected to node V₁The other end is connected with a first diode D₁The first diode D₁Is connected to the switch node SW, wherein the node V₁Is controlled by a bias current I_BIASWidth-to-length ratio of the first PMOS tube MP1 and the third PMOS tube MP3, and R₁Resistance value of,First diode D₁Is determined by the forward conduction voltage of the switch node SW. Second diode D₂Anode connection node V of₂Cathode is grounded, wherein node V₂Is supplied by a second diode D₂The forward turn-on voltage of; positive input terminal node V of voltage comparator COMP₂Negative input terminal connected to node V₁Output terminal is connected to node V_senceThe main role is to compare the nodes V₁And V₂Due to node V₁Will vary with the voltage at the switch node SW, when V is₁Big V₂When, V_senceAnd outputting a low level, and otherwise, outputting a high level.

The trigger port Clk of the first D flip-flop D _ FF1 is connected with the node V_senceThe input port D is connected with the low-side input signal LI, and the output port Q is connected with the port 0 of the first 1-from-2 selector MUX 1; the port 1 of the first 2-to-1 selector MUX1 is connected with a low-side input signal LI, the selection port S is connected with a high-side input signal HI, the output port is connected with the input end of a first buffer BUF1, and the output end of the first buffer BUF1 is connected with a node LO. The trigger port Clk of the second D flip-flop D _ FF2 is connected to the node Vsref, the input port D is connected to the low-side input signal HI, the output port Q is connected to the port 0 of the second 1-out-of-2 selector MUX2, the port 1 of the second 1-out-of-2 selector MUX2 is connected to the low-side input signal HI, the select port S is connected to the high-side input signal LI, the output port is connected to the input terminal of the second buffer BUF2, and the output terminal of the second buffer BUF2 is connected to the node HO.

Fig. 3 is a schematic waveform diagram illustrating the operation principle of the present invention. First, the function of the zero-crossing detection module in which a resistor R having a small resistance is provided will be described with reference to fig. 2₁The main purpose is to provide a comparison threshold value to avoid the voltage comparator COMP being in an intermediate state when the switch node SW is 0V for a long time. Assuming that the device sizes of the first, second and third PMOS transistors MP1, MP2 and MP3 are set to 1:1:1, node V₁The voltage of (a) is: v₁＝I_BIAS*R₁+V_F+V_SWNode V₂Has a voltage of V₂＝V_FIn which V is_FIs a bootstrap diode D_BOOTConducting voltage drop of V_SWIs the voltage of the switch node SW; when the switch node SW falls to-I_BIAS*R₁Before, due to node V₁Is greater than node V₂Voltage of (1), the voltage comparator COMP outputs a low level, i.e. V_senceIs low level; when the switch node SW falls to-I_BIAS*R₁Then, due to node V₁Is less than node V₂Voltage of (1), the voltage comparator COMP outputs a high level, i.e. V_senceHigh level, thereby realizing zero-crossing detection of the switching node SW voltage.

As can be seen from the structure of the half-bridge driving circuit shown in fig. 2, the preceding stage circuit converts the input PWM signal into two signals HI and LI, where the HI and PWM signals are in phase and are high-side driving signals, and the LI and PWM signals are in opposite phase and are low-side driving signals, and the two signals have a phase difference of 180 degrees, and the operation principle of the present invention is described below by taking an example where the PWM signal jumps from high level to low level. Before the PWM transition, LI is low, HI is high, the output of the first D flip-flop D _ FF1 is high, the output of the second D flip-flop D _ FF2 is high, HO is high, and LO is low. When the PWM signal jumps from a high level to a low level at t1, HI and LI respond rapidly, HI changes to a low level, and LI changes to a high level, at this time, the second 2-to-1 selector MUX2 gates the HI signal, HO changes from a high level to a low level rapidly, and the high-side GaN power tube MN1 is turned off; the first 1-out-of-2 selector MUX1 gates the output signal Q1 of the first D flip-flop D _ FF1, and the state of LO changes with the state change of Q1, but since the first D flip-flop D _ FFl is not triggered at this time, Ql remains in the last state, i.e., low, so LO remains low, and at this time, the circuit enters the dead time and the voltage at the switch node SW starts to drop. Passing by Δ t_LWhen the voltage of the switching node SW gradually decreases to the threshold value-I during the time period t2-t1_BIAS*R₁Time, node V₁Is initially less than node V₂Voltage of (1), the output state of the voltage comparator COMP is inverted, and the node V_senceJumping from low level to high level. Due to node V_senceThe arrival of the rising edge triggers the first D flip-flop D _ FF1 and the second D flip-flop D _ FF2,the state of the Q1 is inverted, and the low level jumps to the high level, and meanwhile, the LO jumps to the high level along with the change of the Q1, and the low-side GaN power tube MN2 is turned on. From the above analysis, when the PWM is changed from high level to low level, the dead time is adaptively adjusted to Δ t_L. Similarly, when the PWM is changed from low level to high level, the dead time is adaptively adjusted to be delta t_H。

The embodiment can also be used for other GaN HEMT driving circuits (such as a full-bridge driving circuit) and DC-DC switching power supply circuits, and the problem of large reverse conduction loss caused by overlong traditional dead time setting is solved by detecting the SW point voltage of the switching node and adaptively adjusting the dead time under different load current and power supply voltage conditions.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (5)

1. A self-adaptive dead time control circuit suitable for a GaN driving chip is characterized by comprising a zero-crossing detection module and a dead time control module;

the zero-crossing detection module detects the voltage change condition of the switch node SW in real time and generates a control signal to the dead zone control module;

the dead zone control module delays the control signal input by the high side or the low side, namely the control signal input by the low side is delayed at the falling edge of the switch node SW, and the control signal input by the high side is delayed at the rising edge of the switch node SW, so that dead zone time is generated, and dead zone optimization is realized.

2. The adaptive dead-time control circuit for a GaN driver chip of claim 1, wherein the zero-crossing detection module includes a bias current I_BIASA first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first diode D₁A second diode D₂Resistance R₁And a voltage comparator COMP;

wherein the bias current I_BIASOne end of the first PMOS transistor is simultaneously connected with the drain end and the gate end of a third PMOS transistor MP3, the gate end of a second PMOS transistor MP2 and the gate end of a first PMOS transistor MP1, and the bias current I_BIASThe other end of the first and second electrodes is grounded;

the source ends of the first PMOS tube MP1, the second PMOS tube MP2 and the third PMOS tube MP3 are all connected with VDD; the drain terminal of the first PMOS transistor MP1 is connected to the node V₁The drain terminal of the second PMOS transistor MP2 is connected to the node V₂(ii) a Resistance R₁Is connected to node V₁The other end is connected with a first diode D₁The first diode D₁Is connected to the switch node SW, wherein the node V₁Is controlled by a bias current I_BIASThe width-length ratio of the first PMOS tube MP1, the width-length ratio of the third PMOS tube MP3, and R₁Resistance value, first diode D₁The forward conducting voltage and the voltage of the switch node SW jointly determine, and the second diode D₂Anode connection node V of₂Cathode is grounded, wherein node V₂Is supplied by a second diode D₂The forward turn-on voltage of;

positive input terminal node V of voltage comparator COMP₂Negative input terminal connected to node V₁Output terminal is connected to node V_senceFor comparing nodes V₁And V₂Voltage of said node V₁Is varied with the voltage at the switch node SW, when V is₁Voltage of (V) is large₂When, V_senceAnd outputting a low level, and otherwise, outputting a high level.

3. The adaptive dead-time control circuit for a GaN driver chip of claim 2 wherein the first diode D₁And the second diode D₂All are reverse bias high voltage resistant devices, and the forward conduction voltages are equal.

4. The adaptive dead-time control circuit for a GaN driver chip as claimed in claim 2 wherein the device sizes of the first PMOS transistor MP1 and the second PMOS transistor MP2 are set to be the same.

5. The adaptive dead time control circuit for a GaN driver chip of claim 2, wherein the dead time control module comprises a first D flip-flop D _ FF1, a first D flip-flop D _ FF2, a first 1-out-of-2 selector MUX1, a second 1-out-of-2 selector MUX2, a first buffer BUF1, and a second buffer BUF 2;

the trigger port Clk of the first D flip-flop D _ FF1 is connected with the node V_senceThe input port D is connected with the low-side input signal LI, and the output port Q is connected with the port 0 of the first 1-from-2 selector MUX 1; the port 1 of the first 2-to-1 selector MUX1 is connected with a low-side input signal LI, the selection port S is connected with a high-side input signal HI, and the output port is connected with the input end of a first buffer BUF 1; an output termination node LO of the first buffer BUF 1;

the trigger port Clk of the second D flip-flop D _ FF2 is connected with the node V_senceThe input port D is connected with the low-side input signal HI, and the output port Q is connected with the port 0 of the second 1-out-of-2 selector MUX 2; the port 1 of the second 2-to-1 selector MUX2 is connected with the low-side input signal HI, the selection port S is connected with the high-side input signal LI, and the output port is connected with the input end of the second buffer BUF 2; the output of said second buffer BUF2 terminates at the node HO.

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