CN104901541A - Switching power supply power tube driven dead band time adaptive control circuit and method thereof - Google Patents
Switching power supply power tube driven dead band time adaptive control circuit and method thereof Download PDFInfo
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Abstract
Provided is a switching power supply power tube driven dead band time adaptive control circuit. After a PWM_P signal passes through a dead band fixing circuit and a phase inverter chain driving circuit, a control signal PG is output. After a PWM_N signal and an output signal which passes through a detection and sampling holding circuit for sampling the voltage of an LX point, an error comparison circuit and a control current generation circuit are jointly input to a dead band generating and driving circuit, a control signal NG is output. According to the invention, the rising dead band time T1 and the falling dead band time T2 are controlled separately, the dead band time is fixed as T2 is not largely affected by load current and power tube size, T1 is adjusted automatically in a negative feedback mode, and adaptive dead band optimization is carried out, thus obtaining the optimal dead band time.
Description
Technical field
The present invention relates to Dead Time adaptation control circuit and the method thereof of the driving of a kind of switch power supply power tube, effectively can reduce the loss caused because Dead Time is improper in the switching power converters with synchronous rectification, improve power supply conversion efficiency.
Background technology
For the simple asynchronous rectifier switch supply convertor of control, although synchronous rectification structure control signal is comparatively complicated, can significantly improve conversion efficiency, reduce power loss, the place higher at more and more efficiency requirements is widely applied.But in synchronous rectification configuration switches supply convertor, because high-end synchronous rectifier does not mate with the Dead Time of low side synchronous rectifier grid control signal the raising that the energy loss caused limits its efficiency.
Figure 1 shows that typical synchronous rectification configuration switches power voltage step down converter.High-end PMOS M1 source connects input voltage, low side synchronous rectification NMOS tube M2 source ground connection, and M1 and M2 drain electrode is connected and is designated as LX node, and is connected with one end of inductance L.The inductance L other end is connected with electric capacity C one end, the other end ground connection of electric capacity C, composition LC filter network.Inductance L and electric capacity C tie point are for export V
out.PWM_P and PWM_N signal obtains M1 grid control signal PG, M2 grid control signal NG after dead zone function circuit and driving stage processing of circuit.
In order to avoid emergent power pipe M1, M2 conducting simultaneously in rising and decline process of PG and NG signal, thus produce larger energy loss, M1 and M2 needs certain Dead Time in the process of switched conductive.As shown in Figure 2, namely open through T1 time M2 pipe after M1 pipe is closed, M2 pipe is opened through T2 time M1 pipe after closing again, and avoids the current path being input to ground that M1 and M2 conducting simultaneously causes again.Rising Dead Time T1 be defined as 50% to NG signal that PG signal rises to supply voltage rise to supply voltage 50% between time of delay, decline Dead Time T2 be defined as 50% to PG signal that NG signal drops to supply voltage drop to supply voltage 50% between time of delay.
Long or the too short power supply conversion efficiency that all can reduce converter of Dead Time, for T1.As shown in Figure 3, when M1 pipe and M2 pipe turn off simultaneously, inductive current flows into inductance through the body diode of switching tube from ground, causes the voltage drop of LX point to negative level.If Dead Time is long, the body diode of NMOS tube M2 is opened during T_dio, and body diode exists electric current and voltage always, causes the loss of energy.Particularly when heavy duty, energy loss is larger.As shown in Figure 4, when the too little LX of the making point voltage of Dead Time T1 does not drop to zero, low side NMOS tube M2 opens, and LX point voltage, by M2 repid discharge, makes M2 produce larger forward conduction electric current; Too short Dead Time even can cause M1 and M2 incomplete closedown simultaneously, forms peak current.
Definition optimum dead zone time T is the Dead Time that when making LX point voltage just be discharged to zero, N pipe is opened.Because optimum dead zone time T will change with the change of power tube size and load current, be make converter obtain higher conversion efficiency, Dead Time should change with the change of load current or power tube size.Adopt adaptive control Dead Time of the present invention, make all can obtain the optimum dead zone time under any power tube size and loading condition, thus improve the conversion efficiency of converter.
Summary of the invention
The object of this invention is to provide Dead Time adaptation control circuit and the method thereof of the driving of a kind of switch power supply power tube, when the factors such as load, power tube size, output voltage change, can automatically adjust Dead Time adaptively, obtain the optimum dead zone time, improve Switching Power Supply conversion efficiency.
For achieving the above object, the present invention is by the following technical solutions: the Dead Time adaptation control circuit that a kind of switch power supply power tube drives, comprise high-end synchronous rectification PMOS M1, low side synchronous rectification NMOS tube M2 and LC filter network, the source electrode of PMOS M1 connects input voltage V
in, the input of the drain electrode of PMOS M1 and the drain electrode of NMOS tube M2 and inductance L links together, and tie point is defined as LX point, the output of inductance L connect electric capacity C one end and as the output V of Switching Power Supply
outthe other end of electric capacity C connects the source electrode of NMOS tube M2 and ground connection, the pulse-width signal defining high-end PMOS is PWM_P, the pulse-width signal of low side NMOS tube is PWM_N, PWM_P and PWM_N signal, after dead-zone circuit and drive circuit, produces the control signal NG of the control signal PG of the grid of high-end PMOS M1 and the grid of low side NMOS tube M2 respectively; It is characterized in that:
Dead Time adaptation control circuit comprises two-way control circuit, PWM_P signal exports control signal PG after dead band permanent circuit and chain of inverters drive circuit, PWM_N signal with through detection that LX point voltage is sampled and sampling hold circuit, application condition circuit, control current generating circuit after output signal jointly input to dead band and produce and export control signal NG after drive circuit; Wherein:
Dead band permanent circuit comprises two inverter inv6 and inv7, two input NOR gate nor2, two input nand gate nand2, and NG signal exports through inverter inv6
signal outputs signal as NG2 after inverter inv7 again, NG2 and the input produced from dead band and in drive circuit, the output signal NG1 of inverter inv1 inputs NOR gate nor2 as two, the output signal of two input NOR gate nor2 is PC, PC signal and PWM_P signal are as the input of two input nand gate nand2, and two input nand gate nand2 export PG0 signals;
Chain of inverters drive circuit comprises six inverter inv8 ~ inv13, their breadth length ratio with natural truth of a matter e for multiple increases step by step, the input of inverter inv8 connects the output signal PG0 of dead band permanent circuit, successively through the chain of inverters of inverter inv8 to inv13 composition, inverter inv13 exports the grid control signal PG with large driving force, wherein the output of inverter inv8 is PG1 signal, and the output of inverter inv9 is PG2 signal;
Detect and comprise with sampling hold circuit the NMOS tube M4 that samples, charge switch PMOS M3, two sampling switch PMOS M5 and M6 and three sampling capacitance C_sample0, C_sample1 and C_sample2, the source electrode of NMOS tube M4 connects LX point, the grounded-grid of NMOS tube M4, the drain electrode of NMOS tube M4 and the drain electrode of PMOS M3, M5, the source electrode of M6 and one end of sampling capacitance C_sample0 link together, the source electrode of PMOS M3 connects the output of charging current source I_charge, the input of charging current source I_charge connects Vdd, the grid of PMOS M3 connects charging control signal V
charge, the drain electrode of PMOS M5 connects one end of sampling capacitance C_sample1 also as detecting an output output voltage signal V_dec1 with sampling hold circuit, the grid of PMOS M5 connects sampling control signal V_sample1, and the drain electrode of PMOS M6 connects one end of sampling capacitance C_sample2 also as detecting another output output voltage signal V_dec2 with sampling hold circuit, the grid of PMOS M6 connects sampling control signal V_sample2, sampling control signal V_sample1 by the grid control signal NG of low side synchronous rectification NMOS tube M2 delayed anti-phase after and NG phase and non-post obtain, sampling control signal V_sample2 is obtained after NAND gate by the delayed inversion signal that is rear and PG signal of the grid control signal PG of high-end synchronous rectification PMOS M1, charging control signal V
chargethen direct by sampling control signal V_sample1 delay acquisition,
Application condition circuit adopts typical dual input list to export simple-stage differential structure for amplifying, comprise NMOS tube M7, M8, M11, M12, PMOS M9, M10 and bias current sources Is, NMOS tube M7, M8 is as Differential Input pipe, the grid of NMOS tube M7 is that in-phase end connection detects and the voltage of sampling hold circuit outputs signal V_dec2, the grid of NMOS tube M8 is that end of oppisite phase connection detects and the voltage of sampling hold circuit outputs signal V_dec1, the leakage of PMOS M9, grid short circuit also links together with the drain electrode of NMOS tube M7 and the grid of PMOS M10, the source electrode of PMOS M9 links together with the input of the source electrode of PMOS M10 and bias current sources Is and is connected Vdd, the drain electrode of PMOS M10 is connected with the drain electrode of NMOS tube M8 and as the output of application condition circuit, export control voltage Vcontrol, the drain electrode of the source electrode of NMOS tube M7, the source electrode of NMOS tube M8 and NMOS tube M12 links together, the source ground of NMOS tube M12, the grid of NMOS tube M12 connects the output of the leakage of NMOS tube M11, grid and bias current sources Is, the source grounding of NMOS tube M11 and M12,
Control current generating circuit and comprise PMOS M14, M15 and NMOS tube M13, M16, M17, the grid of NMOS tube M13 connects the control voltage Vcontrol of application condition circuit output, the drain electrode of NMOS tube M13 connects the grid of PMOS M14, drain electrode, the source electrode of PMOS M14 connects the source electrode of PMOS M15 and connects Vdd, the source electrode of NMOS tube M13 and NMOS tube M16, the source electrode of M17 links together and ground connection, the grid of NMOS tube M16, drain electrode short circuit also connects the drain electrode of PMOS M15 and the grid of NMOS tube M17, the drain electrode of NMOS tube M17 is as the output controlling current generating circuit, export and control electric current I control,
Dead band produces and control circuit comprises the inverter inv0 that NMOS tube M18 and PMOS M19 form, two input NOR gate nor1, two input nand gate nand1, five inverter inv1 ~ inv5, their breadth length ratio with natural truth of a matter e for multiple increases step by step; The control electric current I control controlling current generating circuit output connects the source electrode of NMOS tube M18 as discharging current source, the other end ground connection of discharging current source Icontrol, the gate interconnection of NMOS tube M18 and PMOS M19, input as inverter inv0 connects the PG2 signal that in chain of inverters drive circuit, inverter inv9 exports, the drain interconnection of NMOS tube M18 and PMOS M19, the output as inverter inv0 exports
signal,
signal and the PG1 signal that exports from inverter inv8 in chain of inverters drive circuit are through two input NOR gate nor1 phases or non-output NC signals, NC signal exports NG0 signal with PWM_N signal through two input nand gate nand1 phases and non-post again, and NG0 signal exports the grid control signal NG with large driving force successively through inverter inv1 ~ inv5; Wherein the output signal of inverter inv1 is NG1, and be connected to an input of two input NOR gate nor2 in the permanent circuit of dead band, the source electrode of PMOS M19 connects Vdd.
Six inverter inv8 ~ inv13 in said chain of inverters drive circuit, inv8 breadth length ratio is minimum, and inv13 breadth length ratio is the e of inv8 breadth length ratio
5.
Said dead band produces and five inverter inv1 ~ inv5 in control circuit, and inv1 breadth length ratio is minimum, and inv5 breadth length ratio is the e of inv1 breadth length ratio
4.
The control method of the Dead Time adaptation control circuit that above-mentioned switch power supply power tube drives, it is characterized in that: rising Dead Time T1 and decline Dead Time T2 is controlled respectively, the control signal NG that the control signal PG that wherein rising Dead Time T1 is defined as high-end synchronous rectification PMOS M1 grid rises to 50% to low side synchronous rectification NMOS tube M2 grid of supply voltage rise to supply voltage 50% between time of delay, the control signal NG that decline Dead Time T2 is defined as low side synchronous rectification NMOS tube M2 grid drop to 50% to the control signal PG of high-end synchronous rectification PMOS M1 grid of supply voltage drop to supply voltage 50% between time of delay, decline Dead Time T2 adopts fixing Dead Time, and to rising Dead Time T1, utilizes negative feedback mode to automatically adjust according to the size of load, using the discharge signal of the low side synchronous rectification NMOS tube M2 body diode Continuity signal in Switching Power Supply as sampling capacitance C_sample0, magnitude of voltage on the sampling capacitance C_sample0 utilizing V_sample1 and V_sample2 sampling control signal to sample respectively before and after the conducting of low side synchronous rectification NMOS tube M2 body diode, and by these two voltage value signals, the end of oppisite phase of put-into error comparator and in-phase end compare respectively, the output of error comparator becomes control current signal by Voltage-current conversion, be used for adjusting dead band to produce and the discharging current of inverter inv0 in drive circuit, thus change rising Dead Time, and circuit forms feedback loop, constantly automatically adjust until front and back sample voltage value is equal, namely after high-end synchronous rectification PMOS M1 closes, treat the just non-conducting of low side synchronous rectification NMOS tube M2 body diode, when high-end and low side two power tube node voltage is down to zero, low side synchronous rectification NMOS tube M2 opens again, thus obtain best rising Dead Time T1.
Advantage of the present invention and remarkable result:
(1) the present invention adopts pure analogue enlargement, and automated response speed is fast; Use two sampled signals method of comparing through comparator originally, two sampled signal approximately equals during stable state, be namely stabilized in the just non-conducting of low side synchronous rectification NMOS body diode, two power tube node voltages be down to zero state, accuracy is high.
(2) all control signals obtain through logical conversion by the original signal of circuit, and without the need to external signal, structure is simple, are easy to realize.
(3) highly versatile of the present invention, can conveniently embed in the switching power converters circuit of various control mode, is also applicable to any switch converters with synchronous rectifier.
Accompanying drawing explanation
Fig. 1 is the Switching Power Supply decompression converter circuit structure chart of existing synchronous rectification structure;
Fig. 2 is PG, NG signal of Fig. 1 and the schematic diagram of Dead Time, and T1, T2 are Dead Time;
Fig. 3 is that Dead Time T1 is long, causes the conducting of low side synchronous rectifier body diode, and the oscillogram of the negative value of a period of time appears in node LX place voltage;
Fig. 4 is that Dead Time T1 is too short, and when making LX voltage not drop to zero, low side synchronous rectifier is opened, LX point voltage by rectifying tube repid discharge, the oscillogram that node LX place voltage is undergone mutation;
Fig. 5 is the theory diagram of circuit of the present invention;
Fig. 6 detects in Fig. 5 and sampling retaining part circuit theory diagrams;
Fig. 7 is the schematic diagram that in Fig. 6, two sampling control signals and charging control signal produce;
Fig. 8 detects the specific works oscillogram with sampling hold circuit;
Fig. 9 is Fig. 5 medial error comparison circuit schematic diagram;
Figure 10 controls current generating circuit schematic diagram in Fig. 5;
Figure 11 is that in Fig. 5, dead band produces and driving circuit principle figure;
Figure 12 is permanent circuit schematic diagram in dead band in Fig. 5;
Figure 13 is chain of inverters driving circuit principle figure in Fig. 5;
Figure 14 is the working waveform figure that in Fig. 5, Dead Time T1 produces circuit and low side NMOS tube grid control signal NG generation circuit;
Figure 15 is the working waveform figure that in Fig. 5, Dead Time T2 produces circuit and high-end PMOS grid control signal PG generation circuit.
Embodiment
Figure 1 shows that typical synchronous rectification configuration switches power voltage step down converter.High-end PMOS M1 source connects input voltage, low side synchronous rectification NMOS tube M2 source ground connection, and M1 and M2 drain electrode is connected and is designated as LX node, and is connected with one end of inductance L.The inductance L other end is connected with indirect electric capacity C one end, ground, the other end ground connection of electric capacity C, composition LC filter network.Inductance L and electric capacity C tie point are for export Vout.PWM_P and PWM_N signal obtains M1 grid control signal PG, M2 grid control signal NG after dead zone function circuit and driving stage processing of circuit.
As shown in Figure 2, be the sequential chart of M1 grid control signal PG and M2 grid control signal NG.Rising Dead Time T1 be defined as 50% to NG signal that PG signal rises to supply voltage rise to supply voltage 50% between time of delay, decline Dead Time T2 be defined as 50% to PG signal that NG signal drops to supply voltage drop to supply voltage 50% between time of delay.
Figure 3 shows that rising Dead Time T1 is long, cause the conducting of low synchronous rectifier body diode, body diode ON time is T_dio, and node LX place voltage occurs negative value in the T_dio time period.
Fig. 4 is too short for being depicted as rising Dead Time T1, and when making LX voltage not drop to zero, low synchronous rectifier is opened, and LX point voltage is by rectifying tube repid discharge, and node LX place voltage is undergone mutation.
Principle of the invention block diagram as shown in Figure 5.Comprise high-end synchronous rectification PMOS M1, low side synchronous rectification NMOS tube M2 and LC filter network, the source electrode of PMOS M1 connects input voltage V
in, the input of the drain electrode of PMOS M1 and the drain electrode of NMOS tube M2 and inductance L links together, and tie point is defined as LX point, the output of inductance L connect electric capacity C one end and as the output V of Switching Power Supply
outthe other end of electric capacity C connects the source electrode of NMOS tube M2 and ground connection, the pulse-width signal defining high-end PMOS is PWM_P, the pulse-width signal of low side NMOS tube is PWM_N, PWM_P and PWM_N signal, after dead-zone circuit and drive circuit, produces the control signal NG of the control signal PG of the grid of high-end PMOS M1 and the grid of low side NMOS tube M2 respectively.Dead Time adaptation control circuit comprises two-way control circuit, PWM_P signal exports control signal PG after dead band permanent circuit and chain of inverters drive circuit, PWM_N signal with through detection that LX point voltage is sampled and sampling hold circuit, application condition circuit, control current generating circuit after output signal jointly input to dead band and produce and export control signal NG after drive circuit.
Be illustrated in figure 6 and detect and sampling hold circuit schematic diagram.Sampling pipe M4 source is connected on aforementioned nodes LX, grounded-grid, drains connected with the drain electrode of charge switch M3 and is connected sampling capacitance C_sample0, sampling capacitance C_sample0 other end ground connection as exporting; When negative voltage and the conducting of M2 body diode appear in LX, M4 conducting, C_sample0 discharges.Charge switch M3 source electrode connects current source, and grid meets charging control signal V
charge, V
chargewhen signal is low level, charge switch M3 opens, with fixing charging current I_charge and set time for C_sample0 charges.The connected node of C_sample0 and M3 drain electrode connects the source electrode of sampling switch M5 and M6, and M5 drain electrode connects the other end of ground connection sampling capacitance C_sample1, and same M6 drain electrode connects sampling capacitance C_sample2.The grid of M5 and M6 meets sampling control signal V_sample1, V_sample2 respectively, sample respectively and keep dead band T1 on C_sample0 terminate after and dead band T1 arrival before magnitude of voltage.
Figure 7 shows that the sequential of sampling control signal and charging control signal produces schematic diagram.V_sample1 by M2 actual grid drive singal NG delayed anti-phase after and self with have to be to; V_sample2 is obtained through NAND gate by the delayed inversion signal that is rear and original signal of M1 grid control signal PG; V
chargethen directly to be obtained by V_sample1 signal delay.
Figure 8 shows that the working waveform figure detected with sampling hold circuit.In Dead Time T1 section, LX is down to the conducting of less than zero, M2 body diode, and C_sample0 discharges; After NG becomes high level M2 conducting, LX reverts to 0, and electric discharge terminates, and C_sample0 keeps, and obtains voltage V_dec1 through V_sample1 control M5 conducting sampling and keeps; After sampling terminates, V
chargecontrol M3 conducting be C_sample0 charging, charging current and each cycle in charging interval all fixing; Treat in Dead Time T2 section, C_sample0 may because LX be down to less than zero and discharge, and dead band is terminated voltage rear C_sample0 on and remained another definite value, and sampling through V_sample2 control M6 conducting obtains voltage V_dec2 and keep.From aforementioned invention principle, the present invention is regulated by subsequent conditioning circuit automatic feedback and makes V_dec1 and V_dec2 approximately equal, so there are not the C_sample0 electric discharge phenomena that T1 time internal cause LX causes lower than zero, when namely LX just reduces to zero, M2 conducting, obtains the optimum dead zone time.Compared by V_dec1 and V_dec2, target makes these two voltages equal by regulating, but do not pay close attention to their absolute figure.
Figure 9 shows that application condition circuit theory diagrams, adopt typical dual input list to export simple-stage differential structure for amplifying.NMOS tube M7, M8 are as Differential Input pipe, and the grid of M7 is that in-phase end connects the output V_dec2 detected with sampling hold circuit, and the grid of M8 is that end of oppisite phase connects the output V_dec1 detected with sampling hold circuit.M7 drain electrode meets the PMOS M9 of grid leak short circuit as load, and PMOS M10 and M9 one-tenth mirror image connects, and complete two turns of single outputs, M10 drain electrode drains with M8 and is connected as output node, exports control voltage Vcontrol.NMOS tube M11 grid leak short circuit is also connected with bias current sources Is, and M12 and M11 forms NMOS current mirror, and mirror image flows through the electric current of M11, and M12 same M7, M8 source electrode that drains connects connected, thus provides bias current for differential amplifier circuit.The difference of V_dec2 and V_dec1 is amplified output for control signal by application condition circuit, is automatically regulated its difference is constantly reduced by negative-feedback circuit.
Figure 10 shows that and control current generating circuit schematic diagram.The output control voltage Vcontrol of application condition circuit is transformed by V-I change-over circuit and controls electric current I control, the Icontrol discharging current as inverter, the control lag time.NMOS tube M13 grid meets Vcontrol, and control voltage is converted into electric current I _ M13; M13 source ground, drain electrode meets the PMOS M14 of grid leak short circuit as load.PMOS M15 and M14 forms PMOS current-mirror structure, and the PMOS M16 of grid leak short circuit to drain with M15 as load and is connected simultaneously; NMOS tube M17 and M16 forms NMOS current mirror, and M17 leakage current is as control electric current I control.
Figure 11 shows that dead band produces and driving circuit principle figure.M18 and M19 forms CMOS inverter inv0, and Icontrol connects M18 source electrode as inverter discharging current.Inverter inv0 is input as PG2, changes the fall time that Icontrol can change inv0 output, when the clamping of rear class logical transition, can change output pulse width; The output of inverter inv0 and PG2 through two input NOR gate nor1 phases or non-output NC, NC again with the pulse-width signal PWM_N of low side NMOS tube through two input nand gate nand1 phases with have to NG0; NC signal is equivalent to the switch of NAND gate nand1, and when only having NC to export as high level, the output NG0 of NAND gate nand1 just can follow PWM_N change and change.As shown in figure 13, PG1 is exported by the inverter inv8 in chain of inverters drive circuit (empty frame 2) and produces, and PG2 is exported by inverter inv9 and produces.NC signal is obtained through logical conversion by PG1, PG2, and after PG becomes high level, NG just likely becomes high level, thus ensures that high-end PMOS M1 closes the low side NMOS tube M2 that has no progeny and just likely opens.NG0 obtains the gate signal NG with larger driving force again by chain of inverters (in Figure 11 empty frame 1).Chain of inverters (empty frame 1) comprises five inverter inv1 ~ inv5, and their breadth length ratio is that multiple increases step by step with e, and inv1 breadth length ratio is minimum, and inv5 breadth length ratio is the e of inv1 breadth length ratio
4.The chain of inverters that NG0 forms through inv1 ~ inv5, exports and obtains the grid control signal NG with large driving force.NG1 is the output signal of inverter inv1.
NG0 and NG produces oscillogram as shown in figure 14, and oscillogram considers the delay that chain of inverters (in Figure 11 empty frame 1) causes simultaneously.Obtain Dead Time T1 by waveform is known, and T1 can increase with Icontrol and reduce, and T2 size does not change with Icontrol change.
Be described above the embodiment producing NG signal, and PG signal is obtained after dead band permanent circuit and chain of inverters drive circuit by the pulse-width signal PWM_P signal of high-end PMOS.
Dead band permanent circuit as shown in figure 12, comprise two inverter inv6 and inv7, two input NOR gate nor2, two input nand gate nand2, NG signal outputs signal as NG2 after two-stage inverter inv6, inv7, the output signal NG1 of NG2 and inverter inv1 inputs the input of NOR gate nor2 as two, nor2 output signal is for PC, PC and PWM_P are through two input nand gate nand2 output PG0.PC signal is equivalent to the switch of NAND gate nand2, and when only having PC to export as high level, the output PG0 of NAND gate nand2 just can follow PWM_P change and change.PC is obtained through logical conversion by NMOS drive singal NG simultaneously, and after NG becomes low level, PG just likely becomes low level, thus ensures that low side NMOS tube M2 closes the high-end PMOS M1 that has no progeny and just likely opens.
Chain of inverters drive circuit as shown in figure 13, comprises six inverter inv8 ~ inv13, and their breadth length ratio is that multiple successively increases with e, and inv8 breadth length ratio is minimum, and inv13 breadth length ratio is the e of inv8 breadth length ratio
5.The chain of inverters that PG0 forms through inv8 to inv13, exports and obtains the grid control signal PG with large driving force.PG1, PG2 are respectively the output signal of inverter inv8, inv9.
PG0 and PG produces oscillogram as shown in figure 15, and considers the time delay of reverser chain (in Figure 13 empty frame 2).By the known Dead Time T2 be fixed of waveform.
The present invention adopts the method controlled respectively rising Dead Time T1 and decline Dead Time T2, because T2 not quite fixes its Dead Time by load current and power tube size impact, only utilizes negative feedback mode automatically to regulate T1 to carry out adaptive dead zone optimization.Using low side synchronous rectification NMOS tube body diode Continuity signal as sampling capacitance discharge signal, magnitude of voltage on the sampling capacitance adopting suitable sequential to sample respectively before and after the conducting of low side synchronous rectification NMOS body diode, the in-phase end and the end of oppisite phase that these two signals are accessed respectively comparator compare, the output of comparator converts control current signal to by V-I converting unit, being used for dead band produces and the discharging current of inverter in drive circuit, thus change rising Dead Time, constantly automatically adjust until front and back sample voltage value approximately equal, namely after PMOS is closed, treat the just non-conducting of NMOS body diode, when two power tube node voltages are down to zero, NMOS tube is opened again, thus obtain the optimum dead zone time, the gate drive signal with larger driving force is exported finally by chain of inverters.
Feature and the content of this patent disclose as above, but those skilled in the art may make all replacement and the amendment that do not deviate from invention spirit based on explanation of the present invention.Therefore, protection scope of the present invention should be not limited to above-mentioned embodiment, and should comprise the various substitutions and modifications of the present invention that do not deviate from, and is contained by claims.
Claims (4)
1. a Dead Time adaptation control circuit for switch power supply power tube driving, comprises high-end synchronous rectification PMOS M1, low side synchronous rectification NMOS tube M2 and LC filter network, and the source electrode of PMOS M1 connects input voltage V
in, the input of the drain electrode of PMOS M1 and the drain electrode of NMOS tube M2 and inductance L links together, and tie point is defined as LX point, the output of inductance L connect electric capacity C one end and as the output V of Switching Power Supply
outthe other end of electric capacity C connects the source electrode of NMOS tube M2 and ground connection, the pulse-width signal defining high-end PMOS is PWM_P, the pulse-width signal of low side NMOS tube is PWM_N, PWM_P and PWM_N signal, after dead-zone circuit and drive circuit, produces the control signal NG of the control signal PG of the grid of high-end PMOS M1 and the grid of low side NMOS tube M2 respectively; It is characterized in that:
Dead Time adaptation control circuit comprises two-way control circuit, PWM_P signal exports control signal PG after dead band permanent circuit and chain of inverters drive circuit, PWM_N signal with through detection that LX point voltage is sampled and sampling hold circuit, application condition circuit, control current generating circuit after output signal jointly input to dead band and produce and export control signal NG after drive circuit; Wherein:
Dead band permanent circuit comprises two inverter inv6 and inv7, two input NOR gate nor2, two input nand gate nand2, and NG signal exports through inverter inv6
signal outputs signal as NG2 after inverter inv7 again, NG2 and the input produced from dead band and in drive circuit, the output signal NG1 of inverter inv1 inputs NOR gate nor2 as two, the output signal of two input NOR gate nor2 is PC, PC signal and PWM_P signal are as the input of two input nand gate nand2, and two input nand gate nand2 export PG0 signals;
Chain of inverters drive circuit comprises six inverter inv8 ~ inv13, their breadth length ratio with natural truth of a matter e for multiple increases step by step, the input of inverter inv8 connects the output signal PG0 of dead band permanent circuit, successively through the chain of inverters of inverter inv8 to inv13 composition, inverter inv13 exports the grid control signal PG with large driving force, wherein the output of inverter inv8 is PG1 signal, and the output of inverter inv9 is PG2 signal;
Detect and comprise with sampling hold circuit the NMOS tube M4 that samples, charge switch PMOS M3, two sampling switch PMOS M5 and M6 and three sampling capacitance C_sample0, C_sample1 and C_sample2, the source electrode of NMOS tube M4 connects LX point, the grounded-grid of NMOS tube M4, the drain electrode of NMOS tube M4 and the drain electrode of PMOS M3, M5, the source electrode of M6 and one end of sampling capacitance C_sample0 link together, the source electrode of PMOS M3 connects the output of charging current source I_charge, the input of charging current source I_charge connects Vdd, the grid of PMOS M3 connects charging control signal V
charge, the drain electrode of PMOS M5 connects one end of sampling capacitance C_sample1 also as detecting an output output voltage signal V_dec1 with sampling hold circuit, the grid of PMOS M5 connects sampling control signal V_sample1, and the drain electrode of PMOS M6 connects one end of sampling capacitance C_sample2 also as detecting another output output voltage signal V_dec2 with sampling hold circuit, the grid of PMOS M6 connects sampling control signal V_sample2, sampling control signal V_sample1 by the grid control signal NG of low side synchronous rectification NMOS tube M2 delayed anti-phase after and NG phase and non-post obtain, sampling control signal V_sample2 is obtained after NAND gate by the delayed inversion signal that is rear and PG signal of the grid control signal PG of high-end synchronous rectification PMOS M1, charging control signal V
chargethen direct by sampling control signal V_sample1 delay acquisition,
Application condition circuit adopts typical dual input list to export simple-stage differential structure for amplifying, comprise NMOS tube M7, M8, M11, M12, PMOS M9, M10 and bias current sources Is, NMOS tube M7, M8 is as Differential Input pipe, the grid of NMOS tube M7 is that in-phase end connection detects and the voltage of sampling hold circuit outputs signal V_dec2, the grid of NMOS tube M8 is that end of oppisite phase connection detects and the voltage of sampling hold circuit outputs signal V_dec1, the leakage of PMOS M9, grid short circuit also links together with the drain electrode of NMOS tube M7 and the grid of PMOS M10, the source electrode of PMOS M9 links together with the input of the source electrode of PMOS M10 and bias current sources Is and is connected Vdd, the drain electrode of PMOS M10 is connected with the drain electrode of NMOS tube M8 and as the output of application condition circuit, export control voltage Vcontrol, the drain electrode of the source electrode of NMOS tube M7, the source electrode of NMOS tube M8 and NMOS tube M12 links together, the source ground of NMOS tube M12, the grid of NMOS tube M12 connects the output of the leakage of NMOS tube M11, grid and bias current sources Is, the source grounding of NMOS tube M11 and M12,
Control current generating circuit and comprise PMOS M14, M15 and NMOS tube M13, M16, M17, the grid of NMOS tube M13 connects the control voltage Vcontrol of application condition circuit output, the drain electrode of NMOS tube M13 connects the grid of PMOS M14, drain electrode, the source electrode of PMOS M14 connects the source electrode of PMOS M15 and connects Vdd, the source electrode of NMOS tube M13 and NMOS tube M16, the source electrode of M17 links together and ground connection, the grid of NMOS tube M16, drain electrode short circuit also connects the drain electrode of PMOS M15 and the grid of NMOS tube M17, the drain electrode of NMOS tube M17 is as the output controlling current generating circuit, export and control electric current I control,
Dead band produces and control circuit comprises the inverter inv0 that NMOS tube M18 and PMOS M19 form, two input NOR gate nor1, two input nand gate nand1, five inverter inv1 ~ inv5, their breadth length ratio with natural truth of a matter e for multiple increases step by step; The control electric current I control controlling current generating circuit output connects the source electrode of NMOS tube M18 as discharging current source, the other end ground connection of discharging current source Icontrol, the gate interconnection of NMOS tube M18 and PMOS M19, input as inverter inv0 connects the PG2 signal that in chain of inverters drive circuit, inverter inv9 exports, the drain interconnection of NMOS tube M18 and PMOS M19, the output as inverter inv0 exports
signal,
signal and the PG1 signal that exports from inverter inv8 in chain of inverters drive circuit are through two input NOR gate nor1 phases or non-output NC signals, NC signal exports NG0 signal with PWM_N signal through two input nand gate nand1 phases and non-post again, and NG0 signal exports the grid control signal NG with large driving force successively through inverter inv1 ~ inv5; Wherein the output signal of inverter inv1 is NG1, and be connected to an input of two input NOR gate nor2 in the permanent circuit of dead band, the source electrode of PMOS M19 connects Vdd.
2. the Dead Time adaptation control circuit of switch power supply power tube driving according to claim 1, it is characterized in that: six inverter inv8 ~ inv13 in said chain of inverters drive circuit, inv8 breadth length ratio is minimum, and inv13 breadth length ratio is the e of inv8 breadth length ratio
5.
3. the Dead Time adaptation control circuit of switch power supply power tube driving according to claim 1, it is characterized in that: said dead band produces and five inverter inv1 ~ inv5 in control circuit, inv1 breadth length ratio is minimum, and inv5 breadth length ratio is the e of inv1 breadth length ratio
4.
4. the control method of the Dead Time adaptation control circuit of switch power supply power tube driving according to claim 1, it is characterized in that: rising Dead Time T1 and decline Dead Time T2 is controlled respectively, the control signal NG that the control signal PG that wherein rising Dead Time T1 is defined as high-end synchronous rectification PMOS M1 grid rises to 50% to low side synchronous rectification NMOS tube M2 grid of supply voltage rise to supply voltage 50% between time of delay, the control signal NG that decline Dead Time T2 is defined as low side synchronous rectification NMOS tube M2 grid drop to 50% to the control signal PG of high-end synchronous rectification PMOS M1 grid of supply voltage drop to supply voltage 50% between time of delay, decline Dead Time T2 adopts fixing Dead Time, and to rising Dead Time T1, utilizes negative feedback mode to automatically adjust according to the size of load, using the discharge signal of the low side synchronous rectification NMOS tube M2 body diode Continuity signal in Switching Power Supply as sampling capacitance C_sample0, magnitude of voltage on the sampling capacitance C_sample0 utilizing V_sample1 and V_sample2 sampling control signal to sample respectively before and after the conducting of low side synchronous rectification NMOS tube M2 body diode, and by these two voltage value signals, the end of oppisite phase of put-into error comparator and in-phase end compare respectively, the output of error comparator becomes control current signal by Voltage-current conversion, be used for adjusting dead band to produce and the discharging current of inverter inv0 in drive circuit, thus change rising Dead Time, and circuit forms feedback loop, constantly automatically adjust until front and back sample voltage value is equal, namely after high-end synchronous rectification PMOS M1 closes, treat the just non-conducting of low side synchronous rectification NMOS tube M2 body diode, when high-end and low side two power tube node voltage is down to zero, low side synchronous rectification NMOS tube M2 opens again, thus obtain best rising Dead Time T1.
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