CN106847227B - Goa电路驱动架构 - Google Patents
Goa电路驱动架构 Download PDFInfo
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Abstract
本发明提供一种GOA电路驱动架构。该GOA电路驱动架构包括:数个提供数据信号的数据线,数个提供扫描信号的扫描线,数个像素阵列排布,每一像素电性连接于一条数据线及一条扫描线;奇数级GOA电路依序排列于AA区像素一侧,偶数级GOA电路依序排列于AA区像素另一侧,每一级GOA电路分别输出一栅极信号以扫描对应的扫描线,各级GOA电路分别连接第一低频时钟信号、第二低频时钟信号、直流低电压,奇数级GOA电路连接第一高频时钟信号和第三高频时钟信号其中之一,偶数级GOA电路连接第二高频时钟信号和第四高频时钟信号其中之一,最初两级和最后两级GOA电路分别连接启动信号。本发明GOA电路驱动架构能够减少GOA电路所占边框空间,使显示面板做到更窄边框或无边框设计。
Description
技术领域
本发明涉及液晶显示技术领域,尤其涉及一种GOA电路驱动架构。
背景技术
液晶显示器以其高显示品质、价格低廉、携带方便等优点,成为在移动通讯设备、PC、TV等的显示终端。目前普遍采用的TV液晶显示器的面板驱动技术逐渐趋向于采用GOA技术,即阵列基板行驱动(Gate Driver on Array)技术,其运用平板显示面板的原有制程将面板水平扫描线的驱动电路制作在显示区周围的基板上,GOA技术能简化平板显示面板的制作工序,省去水平扫描线方向的接合(bonding)工艺,可提升产能并降低产品成本,同时可以提升显示面板的集成度使之更适合制作窄边框或无边框显示产品,满足现代人们的视觉追求。
随着人们对液晶显示器越来越窄边框的视觉需求,GOA技术还需要不断的缩减边框,这就成为技术人员们急需解决的难题。
图1所示为现有平板显示的GOA多级驱动架构示意图,显示了在现有技术中,用于平板显示的GOA电路的一种多级连接方法,面板左右两侧各级GOA电路的***都放置有第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS、及4个高频时钟信号CK1~CK4的金属线。数个提供数据信号的数据线,数个提供扫描信号的扫描线,数个像素P阵列排布,每一像素P电性连接于一条数据线及一条扫描线;数个GOA电路依序逐级排列GOA(1)、GOA(n-1)、GOA(n)、GOA(n+1),每一GOA电路分别输出一栅极信号,以扫描显示装置中对应的扫描线(gate line),各GOA电路分别电性连接第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS、四个高频时钟信号CK1~CK4中的一个高频时钟信号。具体地,第n级GOA电路分别接受第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS、高频时钟信号CK1~CK4中的1个高频时钟信号、第n-2级GOA电路产生的G(n-2)信号和启动信号ST(n-2)、第n+2级GOA电路产生的G(n+2)信号,并产生G(n)、ST(n)和Q(n)信号。由此可见,现有用于平板显示的GOA电路中使用的薄膜晶体管元件数量较多,并且在显示面板的左、右两侧都需要五条金属线来传输第一低频时钟信号LC1与第二低频时钟信号LC2,直流低电压VSS及四个高频信号中一个,这样既不利于制作成本的降低,也不利于GOA电路尺寸的缩减。
如图2所示,为现有技术中一种GOA电路,同时结合图1进行说明,本显示架构中,GOA电路包括有启动信号STV,第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS、及4个高频时钟信号CK1~CK4。启动信号用于启动GOA的前2级的T11,以及下拉最后两级的T31和T41,低频信号LC1和LC2交替的进行GOA电路的下拉维持,GOA电路主要用于在扫描线(gate line)处于关闭状态时,保持Gn处于稳定的低电位VSS,同时扫描线(gate line)所需Gn信号主要通过四个高频信号中的其中一个进行输出高电平,使显示面板的扫描(gate)信号可以很好地打开控制数据(date)信号输入的TFT,即使像素P可以正常充放电。这种GOA显示面板扫描线(gate line)侧边框较大,无法满足目前更窄边框的需求。
发明内容
因此,本发明的目的在于提供一种GOA电路驱动架构,减少GOA电路所占边框空间。
为实现上述目的,本发明提供了一种GOA电路驱动架构,包括:数个提供数据信号的数据线,数个提供扫描信号的扫描线,数个像素阵列排布,每一像素电性连接于一条数据线及一条扫描线;奇数级GOA电路依序排列于AA区像素一侧,偶数级GOA电路依序排列于AA区像素另一侧,每一级GOA电路分别输出一栅极信号以扫描对应的扫描线,各级GOA电路分别连接第一低频时钟信号、第二低频时钟信号、直流低电压,奇数级GOA电路连接第一高频时钟信号和第三高频时钟信号其中之一,偶数级GOA电路连接第二高频时钟信号和第四高频时钟信号其中之一,最初两级和最后两级GOA电路分别连接启动信号。
其中,第N级GOA电路包括:
第一薄膜晶体管,其栅极连接第N-2级启动信号端,源极和漏极分别连接第N-2级栅极信号端和第N级第一电路点;
第二薄膜晶体管,其栅极连接第N级第一电路点,源极和漏极分别连接高频时钟信号和第N级栅极信号端;
第三薄膜晶体管,其栅极连接第N级第一电路点,源极和漏极分别连接高频时钟信号和第N级启动信号端;
电容,其连接于第N级第一电路点和第N级栅极信号端之间;
第四薄膜晶体管,其栅极连接第N+2级启动信号端,源极和漏极分别连接第N级栅极信号端和直流低电压;
第五薄膜晶体管,其栅极连接第N+2级启动信号端,源极和漏极分别连接第N级第一电路点和直流低电压;
第六薄膜晶体管,其栅极连接第N级第二电路点,源极和漏极分别连接第N级栅极信号端和直流低电压;
第七薄膜晶体管,其栅极连接第N级第二电路点,源极和漏极分别连接第N级第一电路点和直流低电压;
第八薄膜晶体管,其栅极连接第N级第三电路点,源极和漏极分别连接第N级栅极信号端和直流低电压;
第九薄膜晶体管,其栅极连接第N级第三电路点,源极和漏极分别连接第N级第一电路点和直流低电压;
第十薄膜晶体管,其栅极连接第一低频时钟信号,源极和漏极分别连接第一低频时钟信号和第十一薄膜晶体管的栅极;
第十一薄膜晶体管,其源极和漏极分别连接第一低频时钟信号和第N级第三电路点;
第十二薄膜晶体管,其栅极连接第N级第一电路点,源极和漏极分别连接第N级第三电路点和直流低电压;
第十三薄膜晶体管,其栅极连接第二低频时钟信号,源极和漏极分别连接第二低频时钟信号和第十四薄膜晶体管的栅极;
第十四薄膜晶体管,其源极和漏极分别连接第二低频时钟信号和第N级第二电路点;
第十五薄膜晶体管,其栅极连接第N级第一电路点,源极和漏极分别连接第N级第二电路点和直流低电压;
第十六薄膜晶体管,其栅极连接第N级第一电路点,源极和漏极分别连接第十四薄膜晶体管的栅极和直流低电压;
第十七薄膜晶体管,其栅极连接第N级第一电路点,源极和漏极分别连接第十一薄膜晶体管的栅极和直流低电压;
第十八薄膜晶体管,其栅极连接第N级第一电路点,源极和漏极分别连接第N-2级栅极信号端和电压下拉电路点。
其中,该电压下拉电路点为高频时钟信号。
其中,该电压下拉电路点为直流低电压。
其中,该电压下拉电路点为第N级启动信号端。
其中,所述第一、第二、第三及第四高频时钟信号的波形相同,相位顺序相差四分之一周期。
其中,所述第一低频时钟信号和第二低频时钟信号波形相同,相位相反。
综上所述,本发明的GOA电路驱动架构能够减少GOA电路所占边框空间,使显示面板做到更窄边框或无边框设计。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其他有益效果显而易见。
附图中,
图1为现有平板显示的GOA多级驱动架构示意图;
图2为现有平板显示的一种GOA实施电路示意图;
图3为本发明的GOA电路驱动架构示意图;
图4为本发明的GOA电路驱动架构实施方案一的GOA电路原理图;
图5为本发明的GOA电路驱动架构实施方案二的GOA电路原理图;
图6为本发明的GOA电路驱动架构实施方案三的GOA电路原理图;
图7为本发明的GOA电路驱动架构的GOA电路时序图。
具体实施方式
如图3所示,其为本发明的GOA电路驱动架构。该GOA电路驱动架构采用的是GOA电路奇数偶数级左右分开驱动的方式,如奇数级G1在AA(有效显示)区像素的左侧驱动,偶数级G2则在AA区像素的右侧驱动,依次奇数级G3在AA区像素的左侧驱动,偶数级G4则在AA区像素的右侧驱动,依次类推,实现像素的驱动,此种驱动方式可以省去一半的GOA电路所占的高度空间,如果以一级GOA电路的面积来计算,在GOA电路的高度可以增加一倍的前提下,GOA电路的宽度就可以减少一半,再加上GOA电路驱动所需要的高频信号CK的数量也可以减少一半,这样就极大的缩减了扫描线侧的边框。
该GOA电路驱动架构主要包括:
数个提供数据信号的数据线,数个提供扫描信号的扫描线,数个像素P阵列排布,每一像素P电性连接于一条数据线及一条扫描线;奇数级GOA电路依序排列于AA区像素一侧,偶数级GOA电路依序排列于AA区像素另一侧,每一级GOA电路分别输出一栅极信号以扫描对应的扫描线,各级GOA电路分别电性连接第一低频时钟信号LC1、第二低频时钟信号LC2、直流低电压VSS,奇数级GOA电路连接高频时钟信号CK1和CK3其中之一,偶数级GOA电路连接高频时钟信号CK2和CK4其中之一,最初两级和最后两级GOA电路分别连接启动信号ST。
图4为本发明的GOA电路驱动架构实施方案一的GOA电路原理图。第N级GOA电路包括:
薄膜晶体管T11,其栅极连接第N-2级启动信号端ST(N-2),源极和漏极分别连接第N-2级栅极信号端G(N-2)和第N级第一电路点Q(N);
薄膜晶体管T21,其栅极连接第N级第一电路点Q(N),源极和漏极分别连接高频时钟信号CK和第N级栅极信号端G(N);
薄膜晶体管T22,其栅极连接第N级第一电路点Q(N),源极和漏极分别连接高频时钟信号CK和第N级启动信号端ST(N);
电容Cb,其连接于第N级第一电路点Q(N)和第N级栅极信号端G(N)之间;
薄膜晶体管T31,其栅极连接第N+2级启动信号端ST(N+2),源极和漏极分别连接第N级栅极信号端G(N)和直流低电压VSS;
薄膜晶体管T41,其栅极连接第N+2级启动信号端ST(N+2),源极和漏极分别连接第N级第一电路点Q(N)和直流低电压VSS;
薄膜晶体管T33,其栅极连接第N级第二电路点K(N),源极和漏极分别连接第N级栅极信号端G(N)和直流低电压VSS;
薄膜晶体管T43,其栅极连接第N级第二电路点K(N),源极和漏极分别连接第N级第一电路点Q(N)和直流低电压VSS;
薄膜晶体管T32,其栅极连接第N级第三电路点P(N),源极和漏极分别连接第N级栅极信号端G(N)和直流低电压VSS;
薄膜晶体管T42,其栅极连接第N级第三电路点P(N),源极和漏极分别连接第N级第一电路点Q(N)和直流低电压VSS;
薄膜晶体管T51,其栅极连接第一低频时钟信号LC1,源极和漏极分别连接第一低频时钟信号LC1和第薄膜晶体管T53的栅极;
薄膜晶体管T53,其源极和漏极分别连接第一低频时钟信号LC1和第N级第三电路点P(N);
薄膜晶体管T54,其栅极连接第N级第一电路点Q(N),源极和漏极分别连接第N级第三电路点P(N)和直流低电压VSS;
薄膜晶体管T61,其栅极连接第二低频时钟信号LC2,源极和漏极分别连接第二低频时钟信号LC2和薄膜晶体管T63的栅极;
薄膜晶体管T63,其源极和漏极分别连接第二低频时钟信号LC2和第N级第二电路点K(N);
薄膜晶体管T64,其栅极连接第N级第一电路点Q(N),源极和漏极分别连接第N级第二电路点K(N)和直流低电压VSS;
薄膜晶体管T62,其栅极连接第N级第一电路点Q(N),源极和漏极分别连接薄膜晶体管T63的栅极和直流低电压VSS;
薄膜晶体管T52,其栅极连接第N级第一电路点Q(N),源极和漏极分别连接薄膜晶体管T53的栅极和直流低电压VSS;
薄膜晶体管T71,其栅极连接第N级第一电路点Q(N),源极和漏极分别连接第N-2级栅极信号端G(N-2)和电压下拉电路点。
图4中,T71连接的电压下拉电路点为高频时钟信号CK。要想使用图3所示的驱动架构,只需要在图2所示原有的GOA电路中增加一颗TFT(T71)即可实现,原因为目前GOA电路之所以使用图1所示原有的驱动架构,主要在于GOA输出驱动信号Gn后,Gn信号的下降时间(falling time)过长,在AA区gate侧的远端,falling time会更长,这样面板在显示品质在就可能存在gate侧远近端亮度不同,远端色偏等问题。而图4中的GOA电路即可实现GOA电路gate输出在变成低电位的时候,有更大的力度下拉,可以很好的将Gn的falling time缩短。
图5为本发明的GOA电路驱动架构实施方案二的GOA电路原理图,其中T71连接的电压下拉电路点为直流低电压VSS。如图5,将图4中T71的Source端下拉到VSS,同样也可以实现Gn快速下拉的目的。
图6为本发明的GOA电路驱动架构实施方案三的GOA电路原理图,其中T71连接的电压下拉电路点为第N级启动信号端ST(N)。如图6,将图4中T71下拉到STn,同样也可以实现Gn快速下拉的目的。同时实施案例中Gn的下拉全部由原来的Gn+2变化成ST(n+2),这样做的好处在于不需要Gn参与下拉,原因为Gn输出实际上会受到AA区,date等信号的干扰,下拉能力是不太稳定的,同时如果由于面内不良造成Gn异常,那么Gn-2就无法下拉,从而将造成整个GOA电路异常。使用STn+2来下拉后,下拉不会受到面内的任何干扰,最主要是STn下拉会较Gn更快,有利于减小Gn的falling time。
图7为本发明的GOA电路驱动架构的GOA电路时序图,适用于所有实施例的GOA电路,另外,本发明的CK的数量可以是任何偶数。第一、第二、第三及第四高频CK时钟信号的波形相同,相位顺序相差四分之一周期。第一低频时钟信号LC1和第二低频时钟信号LC2波形相同,相位相反。
综上所述,本发明的GOA电路驱动架构能够减少GOA电路所占边框空间,使显示面板做到更窄边框或无边框设计。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。
Claims (6)
1.一种GOA电路驱动架构,其特征在于,包括:数个提供数据信号的数据线,数个提供扫描信号的扫描线,数个像素阵列排布,每一像素电性连接于一条数据线及一条扫描线;奇数级GOA电路依序排列于AA区像素一侧,偶数级GOA电路依序排列于AA区像素另一侧,每一级GOA电路分别输出一栅极信号以扫描对应的扫描线,各级GOA电路分别连接第一低频时钟信号、第二低频时钟信号、直流低电压,奇数级GOA电路连接第一高频时钟信号和第三高频时钟信号其中之一,偶数级GOA电路连接第二高频时钟信号和第四高频时钟信号其中之一,最初两级和最后两级GOA电路分别连接启动信号;
第N级GOA电路包括:
第一薄膜晶体管(T11),其栅极连接第N-2级启动信号端(ST(N-2)),源极和漏极分别连接第N-2级栅极信号端(G(N-2))和第N级第一电路点(Q(N));
第二薄膜晶体管(T21),其栅极连接第N级第一电路点(Q(N)),源极和漏极分别连接高频时钟信号(CK)和第N级栅极信号端(G(N));
第三薄膜晶体管(T22),其栅极连接第N级第一电路点(Q(N)),源极和漏极分别连接高频时钟信号(CK)和第N级启动信号端(ST(N));
电容(Cb),其连接于第N级第一电路点(Q(N))和第N级栅极信号端(G(N))之间;
第四薄膜晶体管(T31),其栅极连接第N+2级启动信号端(ST(N+2)),源极和漏极分别连接第N级栅极信号端(G(N))和直流低电压(VSS);
第五薄膜晶体管(T41),其栅极连接第N+2级启动信号端(ST(N+2)),源极和漏极分别连接第N级第一电路点(Q(N))和直流低电压(VSS);
第六薄膜晶体管(T33),其栅极连接第N级第二电路点(K(N)),源极和漏极分别连接第N级栅极信号端(G(N))和直流低电压(VSS);
第七薄膜晶体管(T43),其栅极连接第N级第二电路点(K(N)),源极和漏极分别连接第N级第一电路点(Q(N))和直流低电压(VSS);
第八薄膜晶体管(T32),其栅极连接第N级第三电路点(P(N)),源极和漏极分别连接第N级栅极信号端(G(N))和直流低电压(VSS);
第九薄膜晶体管(T42),其栅极连接第N级第三电路点(P(N)),源极和漏极分别连接第N级第一电路点(Q(N))和直流低电压(VSS);
第十薄膜晶体管(T51),其栅极连接第一低频时钟信号(LC1),源极和漏极分别连接第一低频时钟信号(LC1)和第十一薄膜晶体管(T53)的栅极;
第十一薄膜晶体管(T53),其源极和漏极分别连接第一低频时钟信号(LC1)和第N级第三电路点(P(N));
第十二薄膜晶体管(T54),其栅极连接第N级第一电路点(Q(N)),源极和漏极分别连接第N级第三电路点(P(N))和直流低电压(VSS);
第十三薄膜晶体管(T61),其栅极连接第二低频时钟信号(LC2),源极和漏极分别连接第二低频时钟信号(LC2)和第十四薄膜晶体管(T63)的栅极;
第十四薄膜晶体管(T63),其源极和漏极分别连接第二低频时钟信号(LC2)和第N级第二电路点(K(N));
第十五薄膜晶体管(T64),其栅极连接第N级第一电路点(Q(N)),源极和漏极分别连接第N级第二电路点(K(N))和直流低电压(VSS);
第十六薄膜晶体管(T62),其栅极连接第N级第一电路点(Q(N)),源极和漏极分别连接第十四薄膜晶体管(T63)的栅极和直流低电压(VSS);
第十七薄膜晶体管(T52),其栅极连接第N级第一电路点(Q(N)),源极和漏极分别连接第十一薄膜晶体管(T53)的栅极和直流低电压(VSS);
第十八薄膜晶体管(T71),其栅极连接第N级第一电路点(Q(N)),源极和漏极分别连接第N-2级栅极信号端(G(N-2))和电压下拉电路点。
2.如权利要求1所述的GOA电路驱动架构,其特征在于,该电压下拉电路点为高频时钟信号(CK)。
3.如权利要求1所述的GOA电路驱动架构,其特征在于,该电压下拉电路点为直流低电压(VSS)。
4.如权利要求1所述的GOA电路驱动架构,其特征在于,该电压下拉电路点为第N级启动信号端(ST(N))。
5.如权利要求1所述的GOA电路驱动架构,其特征在于,所述第一、第二、第三及第四高频时钟信号的波形相同,相位顺序相差四分之一周期。
6.如权利要求1所述的GOA电路驱动架构,其特征在于,所述第一低频时钟信号和第二低频时钟信号波形相同,相位相反。
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CN107154245B (zh) * | 2017-07-17 | 2019-06-25 | 深圳市华星光电技术有限公司 | 一种栅极驱动电路及其驱动方法 |
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CN112967663B (zh) * | 2020-11-16 | 2022-08-05 | 重庆康佳光电技术研究院有限公司 | Led驱动方法及驱动装置 |
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