CN106783796B - 一种芯片封装结构及其制备方法 - Google Patents
一种芯片封装结构及其制备方法 Download PDFInfo
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- CN106783796B CN106783796B CN201611116597.1A CN201611116597A CN106783796B CN 106783796 B CN106783796 B CN 106783796B CN 201611116597 A CN201611116597 A CN 201611116597A CN 106783796 B CN106783796 B CN 106783796B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 68
- 239000010410 layer Substances 0.000 claims abstract description 460
- 239000012790 adhesive layer Substances 0.000 claims abstract description 159
- 239000000463 material Substances 0.000 claims abstract description 87
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- 229910052802 copper Inorganic materials 0.000 description 18
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- 238000000034 method Methods 0.000 description 16
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- 239000000956 alloy Substances 0.000 description 13
- 229910045601 alloy Inorganic materials 0.000 description 13
- 229910052759 nickel Inorganic materials 0.000 description 13
- 229910052709 silver Inorganic materials 0.000 description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 11
- 239000010944 silver (metal) Substances 0.000 description 11
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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- 238000007747 plating Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
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- 229910000679 solder Inorganic materials 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (16)
Priority Applications (1)
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CN201611116597.1A CN106783796B (zh) | 2016-12-07 | 2016-12-07 | 一种芯片封装结构及其制备方法 |
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CN201611116597.1A CN106783796B (zh) | 2016-12-07 | 2016-12-07 | 一种芯片封装结构及其制备方法 |
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CN106783796A CN106783796A (zh) | 2017-05-31 |
CN106783796B true CN106783796B (zh) | 2019-04-26 |
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CN201611116597.1A Active CN106783796B (zh) | 2016-12-07 | 2016-12-07 | 一种芯片封装结构及其制备方法 |
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Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN109300837B (zh) * | 2017-07-25 | 2023-10-20 | 华天科技(昆山)电子有限公司 | 薄型3d扇出封装结构及晶圆级封装方法 |
CN109585402B (zh) * | 2018-12-28 | 2024-06-04 | 华进半导体封装先导技术研发中心有限公司 | 一种芯片扇出型封装结构及封装方法 |
CN112366140B (zh) * | 2020-11-11 | 2022-09-23 | 苏州钜升精密模具有限公司 | 一种用于5g智能设备的多存储芯片堆叠封装构件及其制备方法 |
CN115188781B (zh) * | 2022-09-14 | 2022-11-22 | 山东中清智能科技股份有限公司 | 一种图像传感器封装结构及其制备方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009071004A (ja) * | 2007-09-13 | 2009-04-02 | Panasonic Corp | 半導体装置とその製造方法 |
CN103681359A (zh) * | 2012-09-19 | 2014-03-26 | 宏启胜精密电子(秦皇岛)有限公司 | 层叠封装结构及其制作方法 |
CN103681365A (zh) * | 2012-08-31 | 2014-03-26 | 宏启胜精密电子(秦皇岛)有限公司 | 层叠封装结构及其制作方法 |
CN104241153A (zh) * | 2014-09-16 | 2014-12-24 | 中国科学院微电子研究所 | 板级扇出型结构的封装方法 |
CN105895539A (zh) * | 2016-06-08 | 2016-08-24 | 华进半导体封装先导技术研发中心有限公司 | 芯片倒装封装中间结构和倒装封装结构及倒装封装方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI416636B (zh) * | 2009-10-22 | 2013-11-21 | Unimicron Technology Corp | 封裝結構之製法 |
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2016
- 2016-12-07 CN CN201611116597.1A patent/CN106783796B/zh active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009071004A (ja) * | 2007-09-13 | 2009-04-02 | Panasonic Corp | 半導体装置とその製造方法 |
CN103681365A (zh) * | 2012-08-31 | 2014-03-26 | 宏启胜精密电子(秦皇岛)有限公司 | 层叠封装结构及其制作方法 |
CN103681359A (zh) * | 2012-09-19 | 2014-03-26 | 宏启胜精密电子(秦皇岛)有限公司 | 层叠封装结构及其制作方法 |
CN104241153A (zh) * | 2014-09-16 | 2014-12-24 | 中国科学院微电子研究所 | 板级扇出型结构的封装方法 |
CN105895539A (zh) * | 2016-06-08 | 2016-08-24 | 华进半导体封装先导技术研发中心有限公司 | 芯片倒装封装中间结构和倒装封装结构及倒装封装方法 |
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