CN106774581A - Low pressure difference linear voltage regulator and integrated system-on-chip - Google Patents
Low pressure difference linear voltage regulator and integrated system-on-chip Download PDFInfo
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- CN106774581A CN106774581A CN201710056684.0A CN201710056684A CN106774581A CN 106774581 A CN106774581 A CN 106774581A CN 201710056684 A CN201710056684 A CN 201710056684A CN 106774581 A CN106774581 A CN 106774581A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
This application discloses low pressure difference linear voltage regulator and integrated system-on-chip.The low pressure difference linear voltage regulator is used to be converted into the voltage supplied that feeder ear is provided the output voltage of output end, including：Base modules, for producing bias current and bandgap voltage reference；Amplification module, for output voltage to be compared with the bandgap voltage reference, to obtain the error signal of the two；And output module, for the voltage drop according to error signal control adjustment pipe, so that regulated output voltage.The output module includes the first transistor and transistor seconds that are connected in series between the feeder ear and earth terminal, and the intermediate node of the two is used as the output end, there is provided the output voltage.The low pressure difference linear voltage regulator can be with built-in compensating electric capacity, reduction volume and power consumption and the driving force of raising capacitive load.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly, to the low pressure difference linearity for integrated system-on-chip (SOC)
Voltage-stablizer (LDO) circuit.
Background technology
Integrated system-on-chip (SOC) is the system of integrated processor, memory and major peripheral circuit in one single chip.
For example, SOC can be single-chip wireless system, including for multiple analog circuits and multiple digital circuit blocks, for providing
The major function of function of Bluetooth communication and mobile communication.Due to the functional completeness and efficient Integrated Trait of SOC, SOC is various
It is widely used in electronic product.
The park mode of lower power consumption is provided in the chip design of SOC, to ensure the low power consumption of electronic product.However,
In park mode, in addition it is also necessary to maintain the work of a part of digital circuit, to maintain the state of Digital Logic.SOC is
Operating voltage of the system supply voltage higher than digital circuit.Therefore, low pressure difference linear voltage regulator (LDO) circuit is used in SOC
By system power supply voltage conversion into digital circuit operating voltage.LDO circuit maintains the power supply of digital circuit in the hibernation mode.
For the conventional architectures of LDO circuit, low-power consumption and small area are unavoidably two factors for mutually restricting.
Fig. 1 is shown according to a kind of schematic circuit of the LDO circuit of prior art.The LDO circuit 100 includes benchmark mould
Block 110, amplification module 120, output module 130 and compensating module 140.Base modules 110 include band-gap reference circuit (BGR)
111 and biasing circuit 112, it is respectively configured to provide reference voltage and bias current.Amplification module 120 includes operational amplifier U1,
For the feedback signal of output voltage Vout to be compared with reference voltage, to obtain the error signal of the two.Output module 130
Including the adjustment pipe Q1 and resistance R1 and R2 that are connected in series.The output end of the adjustment pipe provides output voltage Vout, resistance R1 and
R2 constitutes potential-divider network to obtain the feedback signal of output voltage.Adjustment pipe adjusts the voltage drop of pipe according to error signal control,
So as to regulated output voltage Vout.Compensating module 140 includes the electric capacity Co and resistance Ro of series connection, such as piece of compensating module 140
Outer electric capacity and its dead resistance are in series, and form a pole and zero to play a part of stabilization compensation.
The band-gap reference circuit 111 used in LDO circuit can be realized using various frameworks.Fig. 2 is shown shown in Fig. 1
A kind of schematic circuit of the band-gap reference circuit used in LDO circuit.The band-gap reference circuit 111 includes 3 metal oxygens
Compound semiconductor field effect transistor (MOSFET) M1 to M3,10 bipolar transistor B1 to B3, an operational amplifier U11 and
Two resistance R11 and R21, wherein bipolar transistor B2 include one group of totally 8 bipolar transistor.During LDO circuit works, fortune
Calculating amplifier and transistor will consume substantial amounts of electric energy.Fig. 3 shows another band gap base used in LDO circuit shown in Fig. 1
The schematic circuit of quasi- circuit.The band-gap reference circuit 111 include 5 MOSFET MP1 to MP3 and MN1, MN2,10 it is double
Gated transistors B1 to B3 and two resistance R11 and R21, wherein bipolar transistor B2 include one group of totally 8 bipolar transistor.The band
Gap reference circuit 111 eliminates an operational amplifier U11, is adapted to the application of extensive uA ranks power consumption requirements, but for super
For low-power consumption (nA rank power consumptions performance) application, resistance can occupy huge area, substantially be unsatisfactory for actual product demand.
Additionally, in existing LDO circuit, the adjustment pipe of output module 130 uses p-type power transistor mostly.Using P
Type power transistor is more easily done amplifier gain high and low supply voltage, but during for super low-power consumption, ring can be caused on the contrary
Road is unstable, particularly needs to reach hundreds of pf in capacitive load and under load current and the applied environment of very little, substantially can not
The demand of stability can be realized under nA rank power consumptions.
Therefore, it is intended that further reducing the volume and power consumption of LDO circuit, and the driving force of capacitive load is improved, from
And reduces cost and the raising market competitiveness.
The content of the invention
In view of the above problems, it is to provide a kind of low pressure difference linear voltage regulator that the purpose of the present invention is, wherein using novelty
Circuit structure be able to built-in compensating electric capacity, reduce volume and power consumption and improve capacitive load driving force.
According to the first aspect of the invention, there is provided a kind of low pressure difference linear voltage regulator, for the power supply for providing feeder ear
Voltage conversion into output end output voltage, including：Base modules, for producing bias current and bandgap voltage reference；Amplify
Module, is connected with the base modules, for output voltage to be compared with the bandgap voltage reference, to obtain the two
Error signal；And output module, it is connected with the amplification module, for the voltage according to error signal control adjustment pipe
Drop, so that regulated output voltage, wherein, the output module includes：It is connected in series between the feeder ear and earth terminal
The first transistor and transistor seconds, the control end of the first transistor receive the error signal, the transistor seconds
The bias current is obtained from the amplification module using mirror-image fashion, so that for the first transistor provides the biased electrical
The intermediate node of stream, the first transistor and the transistor seconds is used as the output end, there is provided the output voltage.
Preferably, the base modules include：Be connected in series in third transistor between the feeder ear and earth terminal,
4th transistor and at least one the 5th transistors；And it is connected in series in the 6th crystal between the feeder ear and earth terminal
Pipe, the 7th transistor, resistance and at least one the 8th transistors, wherein, the third transistor and the 6th transistor constitute electricity
Stream mirror, the 4th transistor and the 7th transistor constitute current mirror, and described at least one the 5th transistors are connected in parallel with each other,
Described at least one the 8th transistors are connected in parallel with each other, also, at least one the 5th transistor and described at least one
The control end of the 8th transistor is connected to each other and is grounded, and the reference current flows through the 6th transistor.
Preferably, the quantity ratio of described at least one the 5th transistors and at least one the 8th transistor is more than 1：8
And less than or equal to 1：1.
Preferably, the base modules also include：It is connected in series in the 9th crystal between the feeder ear and earth terminal
Pipe, the tenth transistor and the 11st transistor, wherein, the 6th transistor described in the 9th transistor AND gate constitutes current mirror, from
And the reference current is obtained, the tenth transistor connects into diode structure, the control termination of the 11st transistor
The intermediate node of ground, the 9th transistor and the tenth transistor provides the bandgap voltage reference.
Preferably, by setting the proportionate relationship of the breadth length ratio of the 6th transistor described in the 9th transistor AND gate, obtain
The bandgap voltage reference of required numerical value.
Preferably, the number range of the bandgap voltage reference is 1V to 1.8V.
Preferably, the third transistor, the 6th transistor, the 9th transistor are respectively the metal oxygen of p-type
Compound semiconductor field effect transistor, the first transistor, the transistor seconds, the 4th transistor, the described 7th
Transistor is respectively the mos field effect transistor of N-type, and the tenth transistor is the metal of N-type or p-type
Oxide semiconductor field effect transistor, the 5th transistor, the 8th transistor and the 11st transistor difference
It is positive-negative-positive bipolar transistor.
Preferably, the amplification module includes：Operational amplifier, the in-phase input end of the operational amplifier and anti-phase defeated
Enter end and receive the bandgap voltage reference and the output voltage respectively, output end provides the error signal.
Preferably, the amplification module also includes：The 12nd be connected in series between the feeder ear and earth terminal is brilliant
Body pipe and the 13rd transistor, wherein, the tenth two-transistor obtains described inclined using mirror-image fashion from the base modules
Put electric current.
Preferably, the transistor seconds forms current mirror with the 13rd transistor.
Preferably, the tenth two-transistor is the mos field effect transistor of p-type, the described 13rd
Transistor is the mos field effect transistor of N-type.
Preferably, also include：Compensating module, is connected with the amplification module, for compensating the output voltage, its
In, the compensating module is included in the be connected in series the 14th crystalline substance between the output end of the feeder ear and the amplification module
Body pipe and electric capacity, the 14th transistor work in linear zone and make so as to play compensation as compensation resistance and the electric capacity
With.
Preferably, the 14th transistor is the mos field effect transistor of p-type.
According to the second aspect of the invention, there is provided a kind of base modules, including：It is connected in series in the feeder ear and ground connection
Third transistor, the 4th transistor and at least one the 5th transistors between end；And be connected in series in the feeder ear and
The 6th transistor, the 7th transistor, resistance and at least one the 8th transistors between earth terminal, wherein, the 3rd crystal
Pipe and the 6th transistor constitute current mirror, and the 4th transistor and the 7th transistor constitute current mirror, and described at least one the
Five transistors are connected in parallel with each other, and described at least one the 8th transistors are connected in parallel with each other, also, described at least one the 5th
The control end of transistor and at least one the 8th transistor is connected to each other and is grounded, and the reference current flows through the described 6th
Transistor.
Preferably, the quantity ratio of described at least one the 5th transistors and at least one the 8th transistor is more than 1：8
And less than or equal to 1：1.
Preferably, the base modules also include：It is connected in series in the 9th crystal between the feeder ear and earth terminal
Pipe, the tenth transistor and the 11st transistor, wherein, the 6th transistor described in the 9th transistor AND gate constitutes current mirror, from
And the reference current is obtained, the tenth transistor connects into diode structure, the control termination of the 11st transistor
The intermediate node of ground, the 9th transistor and the tenth transistor provides the bandgap voltage reference.
Preferably, by setting the proportionate relationship of the breadth length ratio of the 6th transistor described in the 9th transistor AND gate, obtain
The bandgap voltage reference of required numerical value.
Preferably, the number range of the bandgap voltage reference is 1V to 1.8V.
Preferably, the third transistor, the 6th transistor, the 9th transistor are respectively the metal oxygen of p-type
Compound semiconductor field effect transistor, the first transistor, the transistor seconds, the 4th transistor, the described 7th
Transistor is respectively the mos field effect transistor of N-type, and the tenth transistor is the metal of N-type or p-type
Oxide semiconductor field effect transistor, the 5th transistor, the 8th transistor and the 11st transistor difference
It is positive-negative-positive bipolar transistor.
According to the third aspect of the invention we, there is provided a kind of integrated system-on-chip, including：Processor；Memory；Peripheral electricity
Road；And above-mentioned low pressure difference linear voltage regulator, for being that the processor and the memory are powered.
Low pressure difference linear voltage regulator according to embodiments of the present invention, output module include be connected in series in the feeder ear and
The first transistor and transistor seconds between earth terminal, transistor seconds bias current for the first transistor is provided, the
The intermediate node of one transistor and the transistor seconds is used as output end, there is provided output voltage.Using being operated in linear zone
Compensation resistance in transistor seconds substitution existing structure, while can reaching the super low-power consumption of nA ranks, reduces domain
Area occupied.
In a preferred embodiment, in the output module of low pressure difference linear voltage regulator, the first transistor uses N-type
MOSFET, instead of the p-type MOSFET in conventional architectures.Because the source electrode of N-type MOSFET is exported, therefore low pressure difference linear voltage regulator
Output resistance greatly reduce, such that it is able to realize being compensated in piece, and reach the need that stability is realized under nA rank power consumptions
Ask.
The low pressure difference linear voltage regulator can realize operating current as little as 200nA with built-in compensating electric capacity, and domain realizes area
Less than 0.04mm2.Due to holding without outer contact pin dispatch from foreign news agency, a pin resource for chip can be saved, and capacitive load capacity reaches
To 1nF, the application requirement that SOC powers to internal logic can be met.Thus, the LDO circuit has the extremely strong market competitiveness.
In a further preferred embodiment, in the base modules of low pressure difference linear voltage regulator, current mirror can be reduced
The quantity ratio of middle transistor, and transistor is connected into diode structure to produce bandgap voltage reference, so as to correspondingly subtract
The numerical value of small resistor and its area occupied of domain.
Brief description of the drawings
By description referring to the drawings to the embodiment of the present invention, of the invention above-mentioned and other purposes, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 shows the schematic circuit of the LDO circuit according to prior art.
Fig. 2 shows a kind of schematic circuit of the band-gap reference circuit used in LDO circuit shown in Fig. 1.
Fig. 3 shows the schematic circuit of another band-gap reference circuit used in LDO circuit shown in Fig. 1.
Fig. 4 shows the schematic diagram of base modules according to a first embodiment of the present invention.
Fig. 5 shows a kind of example schematic circuit of base modules according to a first embodiment of the present invention.
Fig. 6 shows another example schematic circuit of base modules according to a first embodiment of the present invention.
Fig. 7 shows the schematic circuit of LDO circuit according to a second embodiment of the present invention.
Fig. 8 shows the schematic circuit of the operational amplifier used in LDO circuit shown in Fig. 7.
Fig. 9 shows the working waveform figure of LDO circuit according to a second embodiment of the present invention.
Figure 10 shows the corresponding phase margin waveform of the output load capacitance of LDO circuit according to a second embodiment of the present invention
Figure.
Specific embodiment
Various embodiments of the present invention are more fully described hereinafter with reference to accompanying drawing.In various figures, identical element
Represented using same or similar reference.For the sake of clarity, the various pieces in accompanying drawing are not necessarily to scale.
In this application, MOSFET includes first end, the second end and control end, in the conducting state of MOSFET, electric current from
First end flow to the second end.The first end of p-type MOSFET, the second end and control end are respectively source electrode, drain and gate, N-type
The first end of MOSFET, the second end and control end are respectively drain electrode, source electrode and grid.Bipolar transistor includes first end, second
End and control end, in the conducting state of bipolar transistor, electric current flow to the second end from first end.The of positive-negative-positive bipolar transistor
One end, the second end and control end are respectively emitter stage, colelctor electrode and base stage, the first end of npn type bipolar transistor, the second end and
Control end is respectively colelctor electrode, emitter stage and base stage.
The present invention is further described with reference to the accompanying drawings and examples.
Fig. 4 shows the schematic diagram of base modules according to a first embodiment of the present invention.As shown in figure 4, the base modules 210
Circuit 2103, pressure stream change-over circuit 2104 and stream pressure conversion are produced including current mirror 2101, operational amplifier 2102, pressure difference
Circuit 2105.
Fig. 5 and 6 is shown respectively the schematic circuit of the different instances of base modules according to a first embodiment of the present invention.
As shown in figure 5, current mirror 2101 include p-type MOSFET MP1 to MP3, operational amplifier 2102 include N-type MOSFET MN1 and
MN2, pressure difference generation circuit 2103 includes bipolar transistor B1 and B2, and pressure stream change-over circuit 2104 includes resistance R11, flows pressure conversion
Circuit 2105 includes N-type MOSFET MN3 and bipolar transistor B3.Example shown in Fig. 6 is to flow with the difference of example shown in Fig. 5
Voltage conversion circuit 2105 includes p-type MOSFET MP6 and bipolar transistor B3, and then the two is identical for other aspects.
Referring to Figure 4 and 5, an output end of current mirror 2101, the i.e. drain electrode of p-type MOSFET MP1, with operational amplifier
2102 offset side is connected, there is provided the bias current of operational amplifier 2102.Meanwhile, the bias current is by operational amplifier
2102 N-type MOSFET MN1 flow into the emitter stage of bipolar transistor B1, and the electric current for producing circuit 2103 as pressure difference is input into.
The in-phase input end of operational amplifier 2102, the i.e. source electrode of N-type MOSFET MN1, circuit 2103 is produced with pressure difference
One output end, the i.e. emitter stage of bipolar transistor B1 is connected.The inverting input of operational amplifier 2102, i.e. N-type
The source electrode of MOSFET MN2, the output end with pressure stream change-over circuit 2104, i.e. one end of resistance R11 is connected.Operational amplifier
One output end of 2102 output end, the i.e. drain electrode of N-type MOSFET MN2 and current mirror 2101, i.e. p-type MOSFET MP2's
Drain and gate is connected.
The input of pressure stream change-over circuit 2104, the i.e. other end of resistance R11, with pressure difference generation circuit 2103 are defeated
Go out end, i.e. the emitter stage of bipolar transistor B2 is connected.Pressure difference produces the base stage of the bipolar transistor B1 and B2 in circuit 2103
All it is connected to the ground with colelctor electrode.
The drain electrode of another output end of current mirror 2101, i.e. p-type MOSFET MP3 is defeated with stream voltage conversion circuit 2105
Enter end, i.e. the drain and gate of N-type MOSFET MN3 is connected, and provides bandgap voltage reference VBG1.Stream voltage conversion circuit
The source electrode of 2105 N-type MOSFET MN3 is connected with the emitter stage of bipolar transistor B3.It is double in stream voltage conversion circuit 2105
The base stage and colelctor electrode of gated transistors B3 are all connected to the ground.
As shown in figure 5, p-type MOSFET MP1, N-type MOSFET MN1 and bipolar transistor B1 are connected in series in supply voltage
Between AVDD and ground AGND.In the conducting state of three, electric current is via p-type MOSFET MP1, N-type MOSFET MN1 and bipolar crystalline substance
Body pipe B1, ground AGND is flow to from feeder ear.
P-type MOSFET MP2, N-type MOSFET MN2, resistance R11 and bipolar transistor B2 are connected in series in supply voltage
Between AVDD and ground AGND.In three conducting states of transistor, electric current via p-type MOSFET MP2, N-type MOSFET MN2,
Resistance R11 and bipolar transistor B2, ground AGND is flow to from feeder ear.
P-type MOSFET MP3, N-type MOSFET MN3 and bipolar transistor B3 are connected in series in supply voltage AVDD and ground
Between AGND.In the conducting state of three, electric current via p-type MOSFET MP3, N-type MOSFET MN3 and bipolar transistor B3,
Ground AGND is flow to from feeder ear.
The grid of p-type MOSFET MP1, MP2 and MP3 is connected to each other, and is connected to the drain electrode of p-type MOSFET MP2, that
This forms mirrored transistor.The breadth length ratio of p-type MOSFET MP1 and MP2 is set to equal, it is ensured that the electric current for flowing through is equal.P-type
The breadth length ratio of MOSFET MP2 and MP3 is configured according to the desired value of bandgap voltage reference VBG1.
The grid of N-type MOSFET MN1 and MN2 is connected to each other, and is connected to the drain electrode of N-type MOSFET MN1, each other shape
It is mirrored into transistor.The breadth length ratio of N-type MOSFET MN1 and MN2 is set to equal, it is ensured that the electric current for flowing through is equal.
The base stage of bipolar transistor B1 and B2 is connected to each other, and is further grounded AGND.The base stage of bipolar transistor B3
It is connected to each other with colelctor electrode, and is further grounded AGND.
The grid of N-type MOSFET MN3 is connected with drain electrode, forms diode structure.
Alternatively, as shown in fig. 6, the grid of p-type MOSFET MP6 is connected with drain electrode, diode structure is formed.
In this embodiment, bias current and bandgap voltage reference VBG1 needed for base modules 210 produce LDO circuit.
Because p-type MOSFET MP1 and MP2 constitute mirrored transistor, N-type MOSFET MN1 and MN2 constitute mirrored transistor, therefore, N
The voltage VB of the source electrode of the voltage VA and MN2 of the source electrode of type MOSFET MN1 is equal.
The bias current that base modules 210 are produced：
IB1=IB2=(VB-VBE (B2))/R=(VBE (B1)-VBE (B2))/R (1)
VBE=VTln(IB/ISB) (2)
N*ISB1=ISB2 (3)
With reference to above formula, obtain：
IB1=IB2=VTlnN/R (4)
Wherein, ISB1, ISB2 are bipolar transistor B1, the saturation current of bipolar transistor B2, and VBE is bipolar transistor
The base-emitter voltage of B1, bipolar transistor B2, N is the number ratio of bipolar transistor B1 and bipolar transistor B2, VTNormal
The lower about 26mV of temperature, R is the resistance value of resistance R11.
The band-gap reference circuit in prior art shown in many aspects and Fig. 2 and 3 of the band-gap reference circuit of the embodiment
It is different.
The first aspect of the embodiment is, in band-gap reference circuit 210, bipolar transistor B1 and bipolar transistor B2
Number be respectively 1 and 3, the i.e. number of the two and compare N=1：3.According to above-mentioned formula (4), it is assumed that the resistance value R=of resistance R11
1.4M, it is possible to obtain the bias current of IB1=20nA.
If according to traditional scheme, the number of bipolar transistor B1 and bipolar transistor B2 compares N=1：8, it is desirable to obtain IB1=
The bias current of 20nA, then need to set the resistance value R=2.7M of resistance R11.The present invention can reduce compared with traditional scheme
The resistance value of resistance R11, such that it is able to save the resistor area of half.
The second aspect of the embodiment is, as shown in figure 5, N-type MOSFET MN3 connect into diode structure, such as Fig. 6
Shown, p-type MOSFET MP6 connect into diode structure, to replace the resistance R21 in Fig. 2 and 3.
The p-type MOSFET MP3 of base modules 210 as p-type MOSFET MP2 mirror image pipe, mirror image p-type MOSFET MP2
Electric current, flow to bipolar transistor B3 and N-type MOSFET MN3, produce bandgap voltage reference VBG1.By setting p-type MOSFET
The proportionate relationship of the breadth length ratio of MP3 and the breadth length ratio of p-type MOSFET MP2, bandgap voltage reference VBG1 can obtain 1V to 1.8V
Between any magnitude of voltage.
The present invention N-type MOSFET MN3 of diode type of attachment, replace the resistance of traditional structure, are greatly saved
Chip area.According to the resistance of traditional structure, if to obtain the voltage of 1.2V, the resistance value of the bias current needs of 20nA is about
It is 30M, actual demand can not be met at all.
Fig. 7 shows the schematic circuit of LDO circuit according to embodiments of the present invention.The LDO circuit 200 includes benchmark mould
Block 210, amplification module 220, compensating module 230 and output module 240.Base modules 210 are used to produce bias current IB1 and band
Gap reference voltage V BG1, amplification module 220 is used to be compared output voltage Vout with bandgap voltage reference VBG1, to obtain
The error signal of the two.Output module 240 adjusts the voltage drop of pipe according to error signal control, so that regulated output voltage
Vout.Compensating module 230 is used as resistance by being operated in the MOSFET of linear zone, and it is steady to play to produce a zero point with electric capacity C1
The effect of fixed compensation.
In LDO circuit 200, band-gap reference circuit 210 itself is not used single operational amplifier, only output module
240 use an operational amplifier, thus, whole LDO circuit includes an operational amplifier, such that it is able to simplify circuit knot
Structure.Further, output module 240 is managed using N-type MOSFET as adjustment, thereby may be ensured that the stabilization of output voltage Vout
Property.
Amplification module 220 includes p-type MOSFET MP4, N-type MOSFET MN4 and operational amplifier U1.
P-type MOSFET MP4 and N-type MOSFET MN4 are connected in series between voltage supplied AVDD and ground AGND.P-type
The grid of MOSFET MP4 and MP3 is connected to each other, and the drain electrode of N-type MOSFET MN4 is connected to each other with grid.Operational amplifier U1
In-phase input end be connected with the drain electrode of p-type MOSFET MP3, inverting input receives output voltage Vout.
Compensating module 230 includes p-type MOSFET MP5 and electric capacity C1.
P-type MOSFET MP5 and electric capacity C1 be connected in series in supply voltage AVDD and operational amplifier U1 output end it
Between.Further, the grid of p-type MOSFET MP5 is connected with the grid of p-type MOSFET MP3.
Compensating module 230 replaces the compensation resistance of traditional structure using the p-type MOSFET MP5 for being operated in linear zone, enters
One step reduces chip area.Compensating module 230 generates a zero point for Left half-plane, for loop compensation.
Output module 240 includes N-type MOSFET MN6 and N-type MOSFET MN5.
N-type MOSFET MN6 and N-type MOSFET MN5 are connected in series between supply voltage AVDD and ground AGND.Further
Ground, the grid of N-type MOSFET MN6 is connected to the output end of operational amplifier U1, and the grid of N-type MOSFET MN5 is connected to N-type
The grid of MOSFET MN4, so as to form mirrored transistor.The intermediate node of N-type MOSFET MN6 and N-type MOSFET MN5 is carried
For output voltage Vout.
Output module 240 replaces the divider resistance of traditional structure using N-type MOSFET MN5.According to the partial pressure of traditional structure
Resistance, if LDO circuit will export the voltage of 1.2V, the resistance value of the divider resistance that 20nA output currents need is about 60M, no
Actual demand can be met.
The first aspect of the embodiment is, using N-type MOSFET MN6, to replace the p-type MOSFET conducts of traditional structure
Power tube is exported, and uses N-type MOSFET MN5, the divider resistance in substitution Fig. 1.
The second aspect of the embodiment is, using the p-type MOSFET MP5 for being operated in linear zone, the benefit in substitution Fig. 1
Repay resistance Ro.
During the work of LDO circuit 200, base modules 210 produce bandgap voltage reference VBG1.In amplification module 220
The in-phase input end of operational amplifier U1 be connected to receive bandgap voltage reference VBG1, inverting input with base modules 210
It is connected to receive the N-type MOSFET of output voltage Vout, output end and output module 240 with the output end of output module 240
The grid of MN6 is connected.
The N-type MOSFET MN5 current mirrors of output module 240 directly produce bias current, for biasing N-type MOSFET
MN6.The output voltage Vout of LDO circuit 200 is directly connected to the inverting input of operational amplifier U1.In the work of feedback control loop
Under, output voltage Vout is directly equal to the bandgap voltage reference VBG1 of the in-phase input end of operational amplifier U1.Operation amplifier
Be compared for output voltage Vout and bandgap voltage reference VBG1 by device U1, and output module is arrived in output after both differences are amplified
240, the voltage drop of the N-type MOSFET MN6 in controlled output module 240, so that regulated output voltage Vout.
In the loop of LDO circuit 200 exist two limits, one be operational amplifier U1 output limit P1, one is
The output limit P2 of LDO circuit 200, is respectively calculated as follows：
Wherein, Rop is operational amplifier U1 output ends equivalent resistance over the ground, and Cop is operational amplifier U1 output ends pair
The equivalent capacity on ground, Rout is equivalent resistance of the output end of LDO circuit 200 to ground, and Cout is the output end of LDO circuit 200 to ground
Equivalent capacity.
Due to there are two limits in loop bandwidth, loop phase nargin can be caused not enough, so as to export to produce
Vibration can not stablize.The method of compensation is that a zero point is manufactured with compensation circuit, goes to compensate phase margin, so that loop phase
Position nargin meets the requirement of stability.
In traditional architectures, zero point value is calculated as follows：
Wherein, Z1 is compensation phase margin, and Cout and Resr is respectively the output end of LDO circuit 200 to the equivalent capacity on ground
With ESR internal resistances.
Output capacitance and resistance in compensation circuit are used to manufacture zero point.Compensation phase margin Z1 offsets limit P1 to loop
The influence of stability, at the same using limit P2 as loop dominant pole so that loop phase nargin meets the requirement of stability.So
And, the bulky capacitor of the compensation method external uF ranks of requirement of the prior art.Due to defeated as power tube using p-type MOSFET
Go out, Rout is larger, limit P2 can be caused smaller, suffer close with P1, be more not easy compensation and reach steady-working state.
In the LDO circuit of the embodiment, compensating electric capacity is built in chip, therefore, the capacitance of compensating electric capacity is not
The bulky capacitor of uF ranks can be used.N-type MOSFET MN6 are used in output module 240, replaces the p-type MOSFET of traditional structure to make
It is power tube.Because the source electrode of N-type MOSFET is exported so that output resistance Rout is greatly reduced, and limit P2 limits are away from limit
P1, so that the embodiment can be by the use of limit P1 as dominant pole, limit P2 is used as secondary dominant pole.
Further, the p-type MOSFET MP5 and electric capacity C1 of compensating module 230 produce a zero point to compensate limit P2 pairs
The influence of phase margin, so that system loop obtains stabilization.
Fig. 8 shows the schematic circuit of the operational amplifier used in LDO circuit shown in Fig. 7.
The operational amplifier U1 used in amplification module 220 uses one-level amplifier structure, as shown in Figure 5.The operation amplifier
Device U1 includes p-type MOSFET MP11 and MP12, N-type MOSFET MN11 to MN13.P-type MOSFET MP11 and N-type MOSFET
MN11 is connected in series between supply voltage AVDD and node N1, and in the conducting state of the two, electric current is via p-type MOSFET
MP11 and N-type MOSFET MN11, node N1 is flow to from feeder ear.P-type MOSFET MP12 and N-type MOSFET MN12 series connection connects
It is connected between supply voltage AVDD and node N1, in the conducting state of the two, electric current is via p-type MOSFET MP12 and N-type
MOSFET MN12, node N1 is flow to from feeder ear.N-type MOSFET MN13 are connected between node N1 and ground AGND.
The grid of p-type MOSFET MP11 and MP12 is connected to each other, and is connected to the drain electrode of p-type MOSFET MP11, that
This forms mirrored transistor.The breadth length ratio of p-type MOSFET MP11 and MP12 is set to equal, it is ensured that the electric current for flowing through is equal.
Respectively as in-phase input end and inverting input, the two constitutes difference to the grid of N-type MOSFET MN11 and MN12
It is right.P-type MOSFET MP11 and MP12 as the differential pair current mirror load.
The grid of N-type MOSFET MN13 is connected with the grid of the N-type MOSFET MN4 in amplification module 220, so as to produce
Raw bias current.
The intermediate node of p-type MOSFET MP12 and N-type MOSFET MN12 is used as output end, there is provided error signal.
Fig. 9 shows the working waveform figure of LDO circuit according to embodiments of the present invention.The output voltage Vout of the LDO circuit
The 1.2V waveforms of stabilization are maintained, and operating current is less than 200nA.
Figure 10 shows the corresponding phase margin oscillogram of the output load capacitance of LDO circuit according to embodiments of the present invention.
The LDO circuit capacitive load be 1nF within can well ensure the stability of a system.
According to embodiments of the invention as described above, these embodiments do not have all of details of detailed descriptionthe, not yet
It is only described specific embodiment to limit the invention.Obviously, as described above, can make many modifications and variations.This explanation
Book is chosen and specifically describes these embodiments, is in order to preferably explain principle of the invention and practical application, so that affiliated
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.Protection model of the invention
The scope that enclosing should be defined by the claims in the present invention is defined.
Claims (14)
1. a kind of low pressure difference linear voltage regulator, the supply voltage for feeder ear to be provided is converted into the output voltage of output end,
Including：
Base modules, for producing bias current and bandgap voltage reference；
Amplification module, is connected with the base modules, for output voltage to be compared with the bandgap voltage reference, with
Obtain the error signal of the two；And
Output module, is connected with the amplification module, for the voltage drop according to error signal control adjustment pipe, so that stabilization
Output voltage,
Wherein, the output module includes：
The first transistor and transistor seconds between the feeder ear and earth terminal are connected in series in,
The control end of the first transistor receives the error signal,
The transistor seconds obtains the bias current using mirror-image fashion from the amplification module, so as to be the described first crystalline substance
Body pipe provides the bias current,
The intermediate node of the first transistor and the transistor seconds is used as the output end, there is provided the output voltage.
2. low pressure difference linear voltage regulator according to claim 1, wherein, the base modules include：
It is connected in series in third transistor between the feeder ear and earth terminal, the 4th transistor and at least one the 5th crystal
Pipe；And
It is connected in series in the 6th transistor, the 7th transistor, resistance and at least one between the feeder ear and earth terminal
Eight transistors,
Wherein, the third transistor and the 6th transistor constitute current mirror, and the 4th transistor and the 7th transistor are constituted
Current mirror, described at least one the 5th transistors are connected in parallel with each other, and described at least one the 8th transistors are connected in parallel with each other,
Also, the control end of described at least one the 5th transistors and at least one the 8th transistor is connected to each other and is grounded,
The reference current flows through the 6th transistor.
3. low pressure difference linear voltage regulator according to claim 2, wherein, described at least one the 5th transistors and it is described extremely
A few quantity ratio for 8th transistor is more than 1：8 and less than or equal to 1：1.
4. low pressure difference linear voltage regulator according to claim 3, wherein, the base modules also include：
The 9th transistor between the feeder ear and earth terminal, the tenth transistor and the 11st transistor are connected in series in,
Wherein, the 6th transistor described in the 9th transistor AND gate constitutes current mirror, so that the reference current is obtained,
Tenth transistor connects into diode structure, and the control end of the 11st transistor is grounded,
The intermediate node of the 9th transistor and the tenth transistor provides the bandgap voltage reference.
5. low pressure difference linear voltage regulator according to claim 4, it is brilliant by setting described in the 9th transistor AND gate the 6th
The proportionate relationship of the breadth length ratio of body pipe, the bandgap voltage reference of numerical value needed for obtaining.
6. low pressure difference linear voltage regulator according to claim 5, the number range of the bandgap voltage reference is arrived for 1V
1.8V。
7. low pressure difference linear voltage regulator according to claim 4, wherein, the third transistor, the 6th transistor,
9th transistor is respectively the mos field effect transistor of p-type,
The first transistor, the transistor seconds, the 4th transistor, the 7th transistor are respectively the gold of N-type
Category oxide semiconductor field effect transistor,
Tenth transistor is the mos field effect transistor of N-type or p-type, the 5th transistor, institute
State the 8th transistor and the 11st transistor respectively positive-negative-positive bipolar transistor.
8. low pressure difference linear voltage regulator according to claim 1, wherein, the amplification module includes：
Operational amplifier, the in-phase input end and inverting input of the operational amplifier receive the bandgap voltage reference respectively
With the output voltage, the output end offer error signal.
9. low pressure difference linear voltage regulator according to claim 8, wherein, the amplification module also includes：
The tenth two-transistor and the 13rd transistor between the feeder ear and earth terminal are connected in series in,
Wherein, the tenth two-transistor obtains the bias current using mirror-image fashion from the base modules.
10. low pressure difference linear voltage regulator according to claim 9, wherein, the transistor seconds and the described 13rd brilliant
Body pipe forms current mirror.
11. low pressure difference linear voltage regulators according to claim 9, wherein, the tenth two-transistor is the metal oxygen of p-type
Compound semiconductor field effect transistor, the 13rd transistor is the mos field effect transistor of N-type.
12. low pressure difference linear voltage regulators according to claim 1, also include：
Compensating module, is connected with the amplification module, for compensating the output voltage,
Wherein, the compensating module is included in be connected in series between the output end of the feeder ear and the amplification module
14 transistors and electric capacity, the 14th transistor work in linear zone so as to play benefit with the electric capacity as compensation resistance
The effect of repaying.
13. low pressure difference linear voltage regulators according to claim 12, wherein, the 14th transistor is the metal of p-type
Oxide semiconductor field effect transistor.
A kind of 14. integrated system-on-chips, including：
Processor；
Memory；
Peripheral circuit；And
Low pressure difference linear voltage regulator according to any one of claim 1 to 13, for for the processor and described depositing
Reservoir is powered.
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| CN109450234A (en) * | 2018-12-14 | 2019-03-08 | 杭州士兰微电子股份有限公司 | Ideal diode and its control circuit |
| CN110320956A (en) * | 2019-08-02 | 2019-10-11 | 深圳贝特莱电子科技股份有限公司 | A kind of interior LDO adjusting circuit without capacitor outside piece of chip |
| CN111367345A (en) * | 2020-05-26 | 2020-07-03 | 江苏长晶科技有限公司 | Compensation method for improving full load stability of low dropout linear regulator and circuit thereof |
| CN111669136A (en) * | 2019-03-07 | 2020-09-15 | 雅特力科技(重庆)有限公司 | Multi-stage amplifier with stabilizing circuit |
| CN112783257A (en) * | 2021-01-04 | 2021-05-11 | 深圳市南方硅谷半导体有限公司 | Series compensation circuit in high-voltage linear voltage converter |
| CN114326892A (en) * | 2021-12-10 | 2022-04-12 | 湖南国科微电子股份有限公司 | Power supply circuit and electronic equipment |
| CN114389450A (en) * | 2020-10-21 | 2022-04-22 | 圣邦微电子（北京）股份有限公司 | Bootstrap switch converter and driving circuit thereof |
| CN115454186A (en) * | 2022-09-15 | 2022-12-09 | 芯洲科技（北京）有限公司 | Linear voltage regulator for power supply system and power supply system |
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| CN115454186A (en) * | 2022-09-15 | 2022-12-09 | 芯洲科技（北京）有限公司 | Linear voltage regulator for power supply system and power supply system |
| CN117075669A (en) * | 2023-09-20 | 2023-11-17 | 江苏帝奥微电子股份有限公司 | High PSRR reference current generation circuit and method without starting circuit |
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