CN108958348B - A kind of band gap reference of high PSRR - Google Patents
A kind of band gap reference of high PSRR Download PDFInfo
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- CN108958348B CN108958348B CN201810915216.9A CN201810915216A CN108958348B CN 108958348 B CN108958348 B CN 108958348B CN 201810915216 A CN201810915216 A CN 201810915216A CN 108958348 B CN108958348 B CN 108958348B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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Abstract
A kind of band gap reference of high PSRR, belongs to electronic circuit technology field.Including power supply automatic biasing module, starting module, band-gap reference nucleus module and biasing module, supply voltage is converted to the first power rail signal as the power rail of biasing module by the 7th NMOS tube by power supply auto bias circuit, starting module and power supply automatic biasing module are that biasing module establishes biasing together, and biasing module provides biasing for band-gap reference nucleus module；The second switch and third switching tube of start-up circuit work when power supply is established and prevent entire circuit from resting on nought state, enter the backed off after random of normal operating conditions in circuit；Resistor network in start-up circuit is used to adjust the negative temperature coefficient voltage of band-gap reference nucleus module, and the positive temperature coefficient voltage superposition that the negative temperature coefficient voltage and band-gap reference nucleus module after adjusting generate generates reference voltage.The present invention has the characteristics that higher power supply rejection ability, structure is simple, precision is high and stability is high.
Description
Technical field
The invention belongs to electronic circuit technology fields, and in particular to a kind of band-gap reference circuit of high PSRR
Design.
Background technique
It is in high performance analog integrated circuit, numerical model analysis, number and power-supply management system design field, reference voltage source
Extremely important and common module, Chang Yingyong simulation in the circuits such as digital quantizer, power converter, power amplifier,
Its performance quality directly affects the precision and stabilization of whole system.Due to band-gap reference source circuit output and error amplifier or
Person is that operational amplifier links together, and becomes a part of error amplifier Differential Input, if power supply ripple or made an uproar
The inhibition that sound cannot access in band-gap reference circuit, then ripple voltage and power supply noise can become error amplifier
Input signal a part, be then amplified the output signal for seriously affecting circuit.In power management chip application, at present
Trend gradually move towards low operating supply voltage and low-power consumption.And with the reduction of operating voltage, signal noise is to band-gap reference
Precision will seem more prominent.Therefore, under lower and lower supply voltage, high power supply inhibits the band gap reference of PSR to become
It obtains more and more important.
Traditional band gap reference is as shown in Figure 1, include error amplifier A1, the mirror image that PMOS tube M1, M2 and M3 are constituted
Current source, resistance R14, R15 and positive-negative-positive bipolar junction transistor Q1, Q2, Q3.The reference voltage V then obtainedREFExpression formula
Are as follows:
Wherein VEBQ3It is the emitter and base voltage difference of bipolar junction transistor Q3；K is that Boltzmann is normal
Number, q are the electricity of unit charge, and T is temperature, and N is the size ratio of positive-negative-positive bipolar junction transistor Q1 and Q2.By adjusting resistance
The ratio R of R14, R1515/R14, available one substantially temperature independent reference voltage VREF。
Traditional band-gap reference circuit itself has good power supply rejection characteristic, in actual circuit, power supply rejection ratio
The frequency characteristic of (Power Supply Rejection Ratio, PSRR) performance not phase in entire input voltage range
Together, Earl benefit voltage and channel-length modulation generally can all lead to the variation of power supply rejection ratio PSRR.That is crystal
The output impedance of pipe changes with the variation of steady state bias situation (dram-source voltage or collector emitter voltage).
The core concept for improving power supply rejection ratio PSRR is to increase reference output voltage VREFTo the effective impedance of input supply voltage VDD.
If designing high-precision complete bandgap reference circuit, it usually needs additional circuit is added to improve the power supply of circuit electricity
Rejection ability is pressed, the complexity that this method will lead to circuit increases and additional power consumption introduces；On the other hand, in conventional belt
In amplifier band-gap reference generation circuit, due to asymmetry, amplifier will receive the influence of input " imbalance ", and being somebody's turn to do " imbalance " will affect electricity
The overall performance on road, while also will limit its precision.
Summary of the invention
The purpose of the present invention needs the additional circuit that is added for improving power supply aiming at above-mentioned traditional bandgap reference circuit
The problem of circuit complicated and power consumption increase caused by voltage rejection ratio, proposes a kind of band-gap reference of high PSRR
Power supply rejection ratio is improved in source in band gap reference internal circuit, while band gap reference proposed by the present invention can not use
Amplifier structure, avoid the introducing of amplifier input imbalance and the problem of confinement bandgap a reference source precision.
The technical solution of the present invention is as follows:
A kind of band gap reference of high PSRR, including power supply automatic biasing module, starting module, band-gap reference core
Module and biasing module,
The power supply automatic biasing module includes first resistor R1, second resistance R2, the first PMOS tube MP1, the second PMOS tube
MP2, third PMOS tube MP3, first capacitor C1, the second capacitor C2, the 7th NMOS tube MNH1 and first switch tube,
Generate the 7th NMOS tube MNH1's after the cascaded structure that supply voltage VDD passes through first resistor R1 and second resistance R2
Gate bias signal connects the grid of the 7th NMOS tube MNH1 and by being grounded GND after first capacitor C1；
The drain electrode of 7th NMOS tube MNH1 connects supply voltage VDD, and source electrode exports the first power rail signal VDD1 conduct
The power rail of the biasing module；
First PMOS tube MP1, the second PMOS tube MP2 and third PMOS tube MP3 are connected into diode type of attachment and successively go here and there
The gate bias signal of connection, the 7th NMOS tube MNH1 passes through the first PMOS tube MP1, the second PMOS tube MP2 and third PMOS tube MP3
Cascaded structure pass through first switch tube after be grounded GND；
Second capacitor C2 connects between the control terminal and ground GND of first switch tube；
The starting module include second switch and third switching tube and including 3rd resistor R3, the 5th resistance R5,
The resistor network of 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9 and the tenth resistance R10,
Second switch and third switching tube constitute current mirror with first switch tube respectively, open in power up phase conducting second
Pipe and third switching tube are closed to generate the first enabling signal and the second enabling signal, after the completion of powering on shutdown second switch and
Third switching tube；
One end of 3rd resistor R3 connects second enabling signal, and the other end connects one end of the 5th resistance R5 and work
For the input terminal of the resistor network；
One end of 6th resistance R6 connects the other end of the 5th resistance R5 and first enabling signal, the other end connect
One end of 7th resistance R7 and one end of the 8th resistance R8；
One end of 9th resistance R9 connects the other end and the 8th resistance R8 of one end of the tenth resistance R10, the 7th resistance R7
The other end, the other end connect the tenth resistance R10 the other end simultaneously be grounded GND；
The power supply automatic biasing module and the starting module are that the biasing module establishes biasing, and the biasing module is
The band-gap reference nucleus module provides biasing；
The band-gap reference nucleus module is for generating positive temperature coefficient voltage and negative temperature parameter current, the negative temperature
Coefficient current connects the input terminal of the resistor network and generates negative temperature coefficient voltage, the subzero temperature on the resistor network
It spends coefficient voltages and the positive temperature coefficient voltage superposition generates reference voltage VREF。
Specifically, the 7th NMOS tube MNH1 is pressure pipe.
Specifically, the biasing module includes the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS tube MP6, the tenth
One PMOS tube MP11, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 6th NPN
Type triode NPN6, eleventh resistor R11, twelfth resistor R12 and thirteenth resistor R13,
The source electrode of 4th PMOS tube MP4 connects the 5th PMOS tube MP5, the 6th PMOS tube MP6 and the 11st PMOS tube MP11
Source electrode and connect the first power rail signal VDD1, drain electrode connection the 7th NMOS tube MNH1 gate bias signal pass through
Signal after the cascaded structure of first PMOS tube MP1, the second PMOS tube MP2 and third PMOS tube MP3, grid connection the 11st
The grid of PMOS tube MP11 and drain electrode and the drain electrode of third NMOS tube MN3；
The grid of 6th PMOS tube MP6 connects the drain electrode of the 6th NMOS tube MN6 and grid and the leakage of the 5th PMOS tube MP5
Pole and the current mirror for connecting the starting module, the grid of the 6th NMOS tube MN6 of drain electrode connection simultaneously generate second source rail letter
Number VDD2 provides biasing for the band-gap reference nucleus module；
After the grid of third NMOS tube MN3 connects the grid of the 4th NMOS tube MN4 and drains and pass through eleventh resistor R11
The first power rail signal VDD1 is connected, source electrode is grounded GND after passing through twelfth resistor R12；
The grid leak of 5th NMOS tube MN5 is shorted and connects the source electrode of the 4th NMOS tube MN4, and source electrode is grounded GND；
The base stage of 6th NPN type triode NPN6 connects the reference voltage VREF, collector the 6th NMOS tube of connection
The source electrode of MN6, emitter are grounded GND after passing through thirteenth resistor R13.
Specifically, the first switch tube is the first NPN type triode NPN1, the base stage of the first NPN type triode NPN1
Sum aggregate electrode interconnection simultaneously connects the gate bias signal of the 7th NMOS tube MNH1 by the first PMOS tube MP1, the second PMOS tube MP2
With the signal after the cascaded structure of third PMOS tube MP3, emitter ground connection.
Specifically, the band-gap reference nucleus module includes the 4th NPN type triode NPN4, the 5th NPN type triode
NPN5, the 4th resistance R4, third capacitor C3, the 4th capacitor C4, the first NMOS tube MN1, the second NMOS tube MN2, the 7th PMOS tube
MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9 and the tenth PMOS tube MP10,
The base stage of 4th NPN type triode NPN4 connects the base stage of the 5th NPN type triode NPN5, the first NMOS tube MN1
Drain electrode and the tenth PMOS tube MP10 grid and drain and export the reference voltage VREF, collector connection the 7th
The grid of PMOS tube MP7 emits with the grid of drain electrode and the 8th PMOS tube MP8 and by being grounded GND after third capacitor C3
Pole passes through the emitter of the 5th NPN type triode NPN5 of connection after the 4th resistance R4；
The source electrode of 8th PMOS tube MP8 connects the 7th PMOS tube MP7, the 9th PMOS tube MP9 and the tenth PMOS tube MP10's
Source electrode simultaneously connects the second source rail signal VDD2, the collector and the 9th of the 5th NPN type triode NPN5 of drain electrode connection
The grid of PMOS tube MP9 and by being grounded GND after the 4th capacitor C4；
The grid leak of second NMOS tube MN2 is shorted and connects the leakage of the grid and the 9th PMOS tube MP9 of the first NMOS tube MN1
Pole, source electrode connect the source electrode of the first NMOS tube MN1 and are grounded GND.
Specifically, the second switch is the second NPN type triode NPN2, the third switching tube is third NPN type
Triode NPN3,
The base stage of second NPN type triode NPN2 connects the control terminal of the first switch tube, described in emitter output
First enabling signal, collector connect the grid of the 5th PMOS tube MP5 in the biasing module as biasing module foundation
Offset signal；
The base stage of third NPN type triode NPN3 connects the control terminal of the first switch tube, described in emitter output
Second enabling signal, collector connect the collector of the 4th NPN type triode NPN4 in the band-gap reference nucleus module, the
The emitter of four NPN type triode NPN4 connects the input terminal of the resistor network after passing through the 4th resistance R4.
The operation principle of the present invention is that:
Supply voltage VDD is converted to the first power rail by the 7th NMOS tube MNH1 by power supply automatic biasing module in the present invention
Power rail of the signal VDD1 as biasing module, biasing module are band-gap reference core mould further according to the first power rail signal VDD1
Block provides biasing；The second switch and third switching tube of starting module work when power supply is established and prevent entire circuit from stopping
Nought state is stayed in, enters the backed off after random of normal operating conditions in circuit；Power supply automatic biasing module and starting module are described together
Biasing module establishes biasing；Start-up circuit also adjusts the negative temperature coefficient electricity that band-gap reference nucleus module generates by resistor network
Pressure, the positive temperature coefficient voltage superposition that the negative temperature coefficient voltage after adjusting is generated with band-gap reference nucleus module is to generate
One temperature independent reference voltage VREF；Since the second source rail signal VDD2 of band-gap reference nucleus module is by inclined
The 6th PMOS tube MP6 set in module is isolated with the first power rail signal VDD1, and the first power rail signal VDD1 is by
Seven NMOS tube MNH1 are isolated with supply voltage VDD, so that the reference voltage V generatedREFWith higher power supply rejection ratio.
The invention has the benefit that the reference voltage V that the present invention generatesREFDue to be isolated with supply voltage VDD without
By the influence of noise from supply voltage VDD, there is higher power supply to inhibit PSR ability；By in band-gap reference core mould
Increase feedback loop in block and stabilizes reference voltage VREFVoltage value, further improve band gap reference power supply inhibit
Than；Circuit structure of the present invention is simple, and avoids to input to lack of proper care using amplifier structure bring amplifier and introduce and confinement bandgap base
The problem of quasi- source precision.
Detailed description of the invention
Fig. 1 is the schematic diagram of the band gap reference of conventional belt amplifier structure.
Fig. 2 is a kind of a kind of realization circuit of band gap reference of high PSRR proposed by the present invention in embodiment
Structure chart.
Fig. 3 is a kind of power supply rejection ratio simulation result diagram of the band gap reference of high PSRR proposed by the present invention.
Fig. 4 is a kind of temperature characterisitic simulation result diagram of the band gap reference of high PSRR proposed by the present invention.
Specific embodiment
The present invention is described in detail in the following with reference to the drawings and specific embodiments.
A kind of band gap reference of high PSRR proposed by the present invention, including power supply automatic biasing module, starting module,
Band-gap reference nucleus module and biasing module, wherein the structure of power supply automatic biasing module is as shown in Fig. 2, power supply automatic biasing module packet
Include first resistor R1, second resistance R2, the first PMOS tube MP1, the second PMOS tube MP2, third PMOS tube MP3, first capacitor C1,
Second capacitor C2, the 7th NMOS tube MNH1 and first switch tube, supply voltage VDD pass through first resistor R1's and second resistance R2
The gate bias signal that the 7th NMOS tube MNH1 is generated after cascaded structure connects the grid of the 7th NMOS tube MNH1 and passes through first
GND is grounded after capacitor C1；The drain electrode of 7th NMOS tube MNH1 connects supply voltage VDD, and source electrode exports the first power rail signal
Power rail of the VDD1 as biasing module；First PMOS tube MP1, the second PMOS tube MP2 and third PMOS tube MP3 are connected into diode
Type of attachment is simultaneously sequentially connected in series, and the gate bias signal of the 7th NMOS tube MNH1 passes through the first PMOS tube MP1, the second PMOS tube
The cascaded structure of MP2 and third PMOS tube MP3 are grounded GND after passing through first switch tube；Second capacitor C2 connects in first switch
Between the control terminal and ground GND of pipe.
The structure of start-up circuit as shown in Fig. 2, include second switch and third switching tube and including 3rd resistor R3,
The resistance net of 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9 and the tenth resistance R10
Network, second switch and third switching tube constitute current mirror with first switch tube respectively, and second switch is connected in power up phase
With third switching tube to generate the first enabling signal and the second enabling signal, shutdown second switch and third after the completion of powering on
Switching tube；One end of 3rd resistor R3 is denoted as node C the second enabling signal of connection, and the other end is denoted as the 5th electricity of node D connection
The negative temperature parameter current for hindering one end of R5 and generating as the input terminal of resistor network connection band-gap reference nucleus module, passes through
Adjust the negative temperature coefficient voltage in resistor network adjusting band-gap reference nucleus module；One end of 6th resistance R6 is denoted as node B
The other end and the first enabling signal of the 5th resistance R5 are connected, the other end connects one end and the 8th resistance R8 of the 7th resistance R7
One end；One end of 9th resistance R9 connects one end of the tenth resistance R10, the other end of the 7th resistance R7 and the 8th resistance R8's
The other end, the other end connect the other end of the tenth resistance R10 and are grounded GND.
Wherein triode form or metal-oxide-semiconductor form can be used in first switch tube, second switch and third switching tube, this
Embodiment is by taking NPN type triode form as an example, as shown in Fig. 2, first switch tube is the first NPN type triode NPN1, the first NPN
The base stage sum aggregate electrode interconnection of type triode NPN1 is denoted as node A and connects the gate bias signal process of the 7th NMOS tube MNH1
Signal after the cascaded structure of first PMOS tube MP1, the second PMOS tube MP2 and third PMOS tube MP3, emitter ground connection.The
Two switching tubes are the second NPN type triode NPN2, and third switching tube is third NPN type triode NPN3, the second NPN type triode
The control terminal of the base stage connection first switch tube of NPN2, emitter export the first enabling signal, collector connection biasing mould
Block simultaneously helps the biasing module to establish offset signal；The control of the base stage connection first switch tube of third NPN type triode NPN3
End processed, emitter export the second enabling signal, and collector connects the 4th NPN type triode in band-gap reference nucleus module
The collector of NPN4, the input terminal that the emitter of the 4th NPN type triode NPN4 passes through connection resistor network after the 4th resistance R4.
Power supply automatic biasing module and starting module can regard a branch as, power in power vd D, circuit start process
In, when supply voltage VDD is powered on more than the first PMOS tube MP1, the gate source voltage of the second PMOS tube MP2 and third PMOS tube and
The sum of the base-emitter voltage of one NPN type triode NPN1 3Vgs+VbeAfterwards, this branch can be connected, the work of circuit
Point is begun setting up, and until supply voltage VDD powers on completion, the electric current of this branch and each node voltage are assured that.
In view of the application conditions of circuit, the power rail of this branch of power supply automatic biasing module and starting module be can choose
For VDD=12V, and if using 0.35um BCD technique, the supply voltage of standard is 5V, i.e. the first power rail signal VDD1
It can choose and need for 5V, the 7th NMOS tube MNH1 for realizing that voltage is converted at this time into pressure pipe, preferably pressure resistance LDMOS pipe.
It is band-gap reference core that biasing module establishes offset signal under the control of power supply automatic biasing module and starting module
Module provides biasing, gives a kind of way of realization of biasing module, including the 4th PMOS tube MP4, the 5th PMOS as shown in Figure 2
Pipe MP5, the 6th PMOS tube MP6, the 11st PMOS tube MP11, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube
MN5, the 6th NMOS tube MN6, the 6th NPN type triode NPN6, eleventh resistor R11, twelfth resistor R12 and thirteenth resistor
The source electrode of R13, the 4th PMOS tube MP4 connect the source of the 5th PMOS tube MP5, the 6th PMOS tube MP6 and the 11st PMOS tube MP11
Pole simultaneously connects the first power rail signal VDD1, and the gate bias signal of the 7th NMOS tube MNH1 of drain electrode connection passes through the first PMOS
Signal after the cascaded structure of pipe MP1, the second PMOS tube MP2 and third PMOS tube MP3, grid connect the 11st PMOS tube
The grid of MP11 and drain electrode and the drain electrode of third NMOS tube MN3；The grid of 6th PMOS tube MP6 connects the 6th NMOS tube MN6
Drain electrode and the 5th PMOS tube MP5 grid and drain and connect the current collection of the second NPN type triode NPN2 in starting module
Pole, it is that band-gap reference nucleus module mentions that drain electrode, which connects the grid of the 6th NMOS tube MN6 and generates second source rail signal VDD2,
For biasing；After the grid of third NMOS tube MN3 connects the grid of the 4th NMOS tube MN4 and drains and pass through eleventh resistor R11
The first power rail signal VDD1 is connected, source electrode is grounded GND after passing through twelfth resistor R12；The grid leak of 5th NMOS tube MN5 is short
The source electrode of the 4th NMOS tube MN4 is connect and connects, source electrode is grounded GND；The base stage connection benchmark electricity of 6th NPN type triode NPN6
Press VREF, the source electrode of the 6th NMOS tube MN6 of collector connection, emitter is by being grounded GND after thirteenth resistor R13.
Band-gap reference nucleus module is for generating positive temperature coefficient voltage and negative temperature parameter current, negative temperature parameter current
The input terminal for connecting resistor network in starting module generates negative temperature coefficient voltage, the negative temperature system of generation on resistor network
Number voltage and positive temperature coefficient voltage superposition generate reference voltage VREF, the one of band-gap reference nucleus module is given as shown in Figure 2
Kind of way of realization, including the 4th NPN type triode NPN4, the 5th NPN type triode NPN5, the 4th resistance R4, third capacitor C3,
4th capacitor C4, the first NMOS tube MN1, the second NMOS tube MN2, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube
The base stage of MP9 and the tenth PMOS tube MP10, the 4th NPN type triode NPN4 connects the base stage of the 5th NPN type triode NPN5, the
The drain electrode of one NMOS tube MN1 and the grid of the tenth PMOS tube MP10 and drain electrode and outputting reference voltage VREF, collector connection
The grid of the grid of 7th PMOS tube MP7 and drain electrode and the 8th PMOS tube MP8 and by being grounded GND after third capacitor C3,
Emitter passes through the emitter of the 5th NPN type triode NPN5 of connection after the 4th resistance R4；The source electrode of 8th PMOS tube MP8 connects
The source electrode of 7th PMOS tube MP7, the 9th PMOS tube MP9 and the tenth PMOS tube MP10 simultaneously connect second source rail signal VDD2,
The collector of the 5th NPN type triode NPN5 of drain electrode connection and the grid of the 9th PMOS tube MP9 are simultaneously followed by by the 4th capacitor C4
Ground GND；The grid leak of second NMOS tube MN2 is shorted and connects the drain electrode of the grid and the 9th PMOS tube MP9 of the first NMOS tube MN1,
Its source electrode connects the source electrode of the first NMOS tube MN1 and is grounded GND.
The course of work and working principle of the present embodiment are as follows.
Power supply automatic biasing module provides constant gate bias voltage for the 7th NMOS tube MNH1, reduces the 7th NMOS tube
The gate source voltage Vgs of MNH1 generates the first power rail signal VDD1.It is completed when the first power rail signal VDD1 is established, biasing module
Two gate source voltage Vgs voltages are generated by the 4th NMOS tube MN4 and the 5th NMOS tube MN5 of two diode connections, thus
One bias current is generated on twelfth resistor R12, provides bias point for the 11st PMOS tube MP11.Flow through the 4th PMOS tube
The first NPN type triode NPN1 that the electric current of MP4 and the electric current of power supply automatic biasing module are superimposed upon base-collector junction short circuit is generated
Base voltage is that establish base stage inclined by the second NPN type triode NPN2 and third NPN type triode NPN3 by current-mirror structure
It sets.The resistance on the first NPN type triode NPN1 and the second NPN type triode NPN2 and node B to ground constitutes Wildar current mirror,
The 5th PMOS tube MP5 that the electric current of mirror image power supply automatic biasing module is connected to diode, to establish the 5th for biasing module
The biasing of the grid voltage of PMOS tube MP5 and the 6th PMOS tube MP6.First NPN type triode NPN1 and third NPN type triode
The resistance on NPN3 and C node to ground equally constitutes Wildar current mirror, is similarly the metal-oxide-semiconductor being attached thereto and provides gate bias,
Wilson current mirror is readily modified as common-source common-gate current mirror in some embodiments.From the electric current of the 6th PMOS tube MP6 mirror image point to
4 branches of band-gap reference nucleus module are respectively the MOS in band-gap reference nucleus module by the metal-oxide-semiconductor that diode connects
Tube grid and transistor base provide bias voltage.
In starting module, the second NPN type triode NPN2 and third NPN type triode NPN3 are starting pipe, with power supply
Voltage VDD is powered on, and the electric current for flowing through the second NPN type triode NPN2 and third NPN type triode NPN3 also becomes larger therewith, B, C
Node is that the voltage of the first enabling signal and the second enabling signal generated is raised therewith；Second NPN type after final start completion
Triode NPN2 and third NPN type triode NPN3 can be turned off, so flowing through the second NPN type triode NPN2 and under stable state
The electric current of three NPN type triode NPN3 is 0.
The working principle of band-gap reference nucleus module is as follows:
4th NPN type triode NPN4, the 5th NPN type triode NPN5 and the 4th resistance R4 are for generating positive temperature coefficient
PTAT current accesses the resistor network in starting module.4th resistance R4 both ends pressure drop be the 4th NPN type triode NPN4 and
The difference Δ V of the base emitter voltage of 5th NPN type triode NPN5BE, it is typically chosen the 4th NPN type triode NPN4 and
The number in parallel of five NPN type triode NPN5 is 8:1, so flowing through the expression formula of the electric current of the 4th resistance R4 are as follows:
Electric current due to flowing through the second NPN type triode NPN2 and third NPN type triode NPN3 under stable state is 0, D node
The electric current of output is only the sum of the electric current for flowing through the 4th NPN type triode NPN4 and the 5th NPN type triode NPN5.The present embodiment
The middle current mirror mirror ratio for forming the 7th PMOS tube MP7 and the 8th PMOS tube MP8 is set as 1:1, so this two branch electricity
It flows identical.So the voltage on node D is a negative temperature coefficient voltage
RDFor D node (i.e. the input terminal of resistor network) to the resistance on ground.Bandgap voltage reference is a negative temperature coefficient
Voltage and a positive temperature coefficient voltage scale coefficient are added to obtain.Due to the base emitter voltage V of triodeBEHave
Negative temperature coefficient feature, so can by the base emitter voltage that D point voltage is superimposed with the 5th NPN type triode NPN5 again
To obtain bandgap voltage reference VREF, i.e., the base voltage of the 4th NPN type triode NPN4 and the 5th NPN type triode NPN5 is just
It is the reference voltage V that the present invention generates for bandgap voltage referenceREF:
According to circuit technology NPN triode Δ VbeAnd VbeTemperature coefficient be
The available temperature independent bandgap voltage reference V of ratio of resistance is adjusted according to the proportionality coefficient of formulaREF,
I.e. in resistor network node B to ground equivalent resistance be used for trim and change the D node in above formula to ground resistance RD, to adjust
Negative temperature coefficient voltage in whole band-gap reference nucleus module.
5th NPN type triode NPN5, the 9th PMOS tube MP9, the first NMOS tube MN1 and in band-gap reference nucleus module
Two NMOS tube MN2 constitute a negative feedback loop, are used for stable reference voltage VREFVoltage value, prevent reference voltage VREFIn power supply
Biggish fluctuation is generated when shake or load variation.As reference voltage VREFWhen voltage value is interfered and generates variation, by negative
The effect of feedback control loop is quickly reference voltage VREFRetract initial value.4th capacitor C4 is used for the frequency stability of feedback loop
Compensation.
Band gap reference realizes that high power supply inhibits the core concept of PSR to be desirable to the small signal disturbance from supply voltage VDD
It is as few as possible that reference voltage V is transmitted to by transistorREFPlace, for traditional band-gap reference electricity being made of amplifier clamper
Road, the PSR for improving benchmark just needs to improve the gain of amplifier and the PSR of amplifier, and the PSR that this circuit improves reference circuit is main
It is realized by the 6th PMOS tube MP6 in the 7th NMOS tube MNH1 and biasing module.Supply voltage VDD passes through the 7th NMOS tube
MNH1 reduces a drain-source voltage Vgs and obtains the first power rail signal VDD1, when there are noises to generate small signal by supply voltage VDD
When disturbance, noise is kept apart by the 7th NMOS tube MNH1 by drain terminal and the first power rail signal VDD1, to will not be crosstalked into
On first power rail signal VDD1；First power rail signal VDD1 passes through the 6th PMOS tube MP6 again and generates second source rail signal
VDD2 forms isolation, is further ensured that second source rail signal VDD2 will not change with the crosstalk of supply voltage VDD, so this
Invent the reference voltage V generatedREFSubstantially it not will receive the influence of noise from supply voltage VDD, there is high good power supply to inhibit
PSR ability.
Fig. 3 is the simulation scenarios of the power supply rejection ability of band gap reference proposed by the present invention, it can be seen that the present invention mentions
127B can be reached when the power supply rejection ratio PSRR low frequency of band gap reference out, still have 47dB in the case where 1MHz, had non-
Often good power supply inhibits PSR performance.
Fig. 4 is the temperature characterisitic simulation scenarios of band gap reference proposed by the present invention, in -40 DEG C~125 DEG C temperature ranges
It is interior, the temperature coefficient of band gap reference are as follows:
Wherein VMAXAnd VMINRespectively indicate reference voltage V in Fig. 4REFMaximum value and minimum value.
In conclusion band gap reference proposed by the present invention, is isolated by two layers by the benchmark of supply voltage VDD and generation
Voltage VREFKeep apart, so that the reference voltage V that the present invention generatesREFSubstantially the noise shadow from supply voltage VDD is not will receive
It rings, there is better power supply to inhibit PSR ability；The subzero temperature of band-gap reference nucleus module is adjusted by the resistor network of starting module
Coefficient voltages are spent, the design of feedback loop is increased in band-gap reference nucleus module, are used for stable reference voltage VREFVoltage
Value, further increases the power supply rejection ratio of band gap reference；Not increasing additional circuit can be achieved with improving power supply rejection ratio
Effect, circuit structure is simple, and avoid using amplifier structure bring amplifier input imbalance introduce and confinement bandgap benchmark
The problem of source precision.
Those skilled in the art disclosed the technical disclosures can make various do not depart from originally according to the present invention
Various other specific variations and combinations of essence are invented, these variations and combinations are still within the scope of the present invention.
Claims (6)
1. a kind of band gap reference of high PSRR, which is characterized in that including power supply automatic biasing module, starting module, band
Gap benchmark nucleus module and biasing module,
The power supply automatic biasing module includes first resistor (R1), second resistance (R2), the first PMOS tube (MP1), the 2nd PMOS
Manage (MP2), third PMOS tube (MP3), first capacitor (C1), the second capacitor (C2), the 7th NMOS tube (MNH1) and first switch
Pipe,
Supply voltage (VDD) is by generating the 7th NMOS tube after first resistor (R1) and the cascaded structure of second resistance (R2)
(MNH1) gate bias signal connects the grid of the 7th NMOS tube (MNH1) and is grounded (GND) afterwards by first capacitor (C1)；
The drain electrode of 7th NMOS tube (MNH1) connects supply voltage (VDD), and source electrode exports the first power rail signal (VDD1) and makees
For the power rail of the biasing module；
First PMOS tube (MP1), the second PMOS tube (MP2) and third PMOS tube (MP3) are connected into diode type of attachment and successively
Series connection, the gate bias signal of the 7th NMOS tube (MNH1) is by the first PMOS tube (MP1), the second PMOS tube (MP2) and third
The cascaded structure of PMOS tube (MP3) is grounded (GND) after passing through first switch tube；
Second capacitor (C2) connects between the control terminal and ground (GND) of first switch tube；
The starting module include second switch and third switching tube and including 3rd resistor (R3), the 5th resistance (R5),
6th resistance (R6), the 7th resistance (R7), the 8th resistance (R8), the 9th resistance (R9) and the tenth resistance (R10) resistor network,
Second switch and third switching tube constitute current mirror with first switch tube respectively, and second switch is connected in power up phase
With third switching tube to generate the first enabling signal and the second enabling signal, shutdown second switch and third after the completion of powering on
Switching tube；
One end of 3rd resistor (R3) connects second enabling signal, and the other end connects one end of the 5th resistance (R5) and work
For the input terminal of the resistor network；
One end of 6th resistance (R6) connects the other end of the 5th resistance (R5) and first enabling signal, the other end connect
One end of 7th resistance (R7) and one end of the 8th resistance (R8)；
One end of 9th resistance (R9) connects the other end and the 8th resistance of one end of the tenth resistance (R10), the 7th resistance (R7)
(R8) the other end, the other end connect the other end of the tenth resistance (R10) and ground connection (GND)；
The power supply automatic biasing module and the starting module are that the biasing module establishes biasing, and the biasing module is described
Band-gap reference nucleus module provides biasing；
The band-gap reference nucleus module is for generating positive temperature coefficient voltage and negative temperature parameter current, the negative temperature coefficient
Electric current connects the input terminal of the resistor network and generates negative temperature coefficient voltage, the negative temperature system on the resistor network
Number voltage and the positive temperature coefficient voltage superposition generate reference voltage (VREF)。
2. the band gap reference of high PSRR according to claim 1, which is characterized in that the 7th NMOS tube
It (MNH1) is pressure pipe.
3. the band gap reference of high PSRR according to claim 1, which is characterized in that the biasing module includes
4th PMOS tube (MP4), the 5th PMOS tube (MP5), the 6th PMOS tube (MP6), the 11st PMOS tube (MP11), third NMOS tube
(MN3), the 4th NMOS tube (MN4), the 5th NMOS tube (MN5), the 6th NMOS tube (MN6), the 6th NPN type triode (NPN6),
Eleventh resistor (R11), twelfth resistor (R12) and thirteenth resistor (R13),
The source electrode of 4th PMOS tube (MP4) connects the 5th PMOS tube (MP5), the 6th PMOS tube (MP6) and the 11st PMOS tube
(MP11) source electrode simultaneously connects the first power rail signal (VDD1), and the grid of drain electrode the 7th NMOS tube (MNH1) of connection is inclined
Signal of the confidence number after the cascaded structure of the first PMOS tube (MP1), the second PMOS tube (MP2) and third PMOS tube (MP3),
The grid of its grid the 11st PMOS tube (MP11) of connection and drain electrode and the drain electrode of third NMOS tube (MN3)；
The grid of 6th PMOS tube (MP6) connect the drain electrode of the 6th NMOS tube (MN6) and the grid of the 5th PMOS tube (MP5) and
The current mirror of the starting module is drained and connects, the grid of drain electrode the 6th NMOS tube (MN6) of connection simultaneously generates second source
Rail signal (VDD2) provides biasing for the band-gap reference nucleus module；
The grid of third NMOS tube (MN3) connects the grid of the 4th NMOS tube (MN4) and drains and pass through eleventh resistor (R11)
After connect the first power rail signal (VDD1), source electrode is grounded (GND) afterwards by twelfth resistor (R12)；
The grid leak of 5th NMOS tube (MN5) is shorted and connects the source electrode of the 4th NMOS tube (MN4), and source electrode is grounded (GND)；
The base stage of 6th NPN type triode (NPN6) connects the reference voltage (VREF), collector connects the 6th NMOS tube
(MN6) source electrode, emitter are grounded (GND) afterwards by thirteenth resistor (R13).
4. the band gap reference of high PSRR according to claim 1, which is characterized in that the first switch tube is
First NPN type triode (NPN1), the base stage sum aggregate electrode interconnection of the first NPN type triode (NPN1) simultaneously connect the 7th NMOS tube
(MNH1) gate bias signal is by the first PMOS tube (MP1), the string of the second PMOS tube (MP2) and third PMOS tube (MP3)
Signal after being coupled structure, emitter ground connection.
5. the band gap reference of high PSRR according to claim 3, which is characterized in that the band-gap reference core
Module includes the 4th NPN type triode (NPN4), the 5th NPN type triode (NPN5), the 4th resistance (R4), third capacitor
(C3), the 4th capacitor (C4), the first NMOS tube (MN1), the second NMOS tube (MN2), the 7th PMOS tube (MP7), the 8th PMOS tube
(MP8), the 9th PMOS tube (MP9) and the tenth PMOS tube (MP10),
The base stage of 4th NPN type triode (NPN4) connects base stage, the first NMOS tube of the 5th NPN type triode (NPN5)
(MN1) grid of drain electrode and the tenth PMOS tube (MP10) and drain electrode simultaneously export the reference voltage (VREF), collector connects
The grid for connecing the 7th PMOS tube (MP7) is followed by with the grid of drain electrode and the 8th PMOS tube (MP8) and by third capacitor (C3)
Ground (GND), emitter connect the emitter of the 5th NPN type triode (NPN5) by the 4th resistance (R4) afterwards；
The source electrode of 8th PMOS tube (MP8) connects the 7th PMOS tube (MP7), the 9th PMOS tube (MP9) and the tenth PMOS tube
(MP10) source electrode simultaneously connects the second source rail signal (VDD2), drain electrode the 5th NPN type triode (NPN5) of connection
Collector and the grid of the 9th PMOS tube (MP9) are simultaneously grounded (GND) afterwards by the 4th capacitor (C4)；
The grid leak of second NMOS tube (MN2) is shorted and connects the grid of the first NMOS tube (MN1) and the leakage of the 9th PMOS tube (MP9)
Pole, source electrode connect the source electrode of the first NMOS tube (MN1) and ground connection (GND).
6. the band gap reference of high PSRR according to claim 5, which is characterized in that the second switch is
Second NPN type triode (NPN2), the third switching tube are third NPN type triode (NPN3),
The base stage of second NPN type triode (NPN2) connects the control terminal of the first switch tube, emitter output described the
One enabling signal, collector connect the grid of the 5th PMOS tube (MP5) in the biasing module as biasing module foundation
Offset signal；
The base stage of third NPN type triode (NPN3) connects the control terminal of the first switch tube, emitter output described the
Two enabling signals, collector connect the collector of the 4th NPN type triode (NPN4) in the band-gap reference nucleus module, the
The emitter of four NPN type triodes (NPN4) connects the input terminal of the resistor network by the 4th resistance (R4) afterwards.
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| CN115016592B (en) * | 2022-06-29 | 2023-08-11 | 北京领创医谷科技发展有限责任公司 | Band gap reference source circuit |
| CN117008676B (en) * | 2023-08-17 | 2024-05-31 | 荣湃半导体（上海）有限公司 | Self-starting circuit for band-gap reference circuit |
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