CN111367345A - Compensation method for improving full load stability of low dropout linear regulator and circuit thereof - Google Patents

Compensation method for improving full load stability of low dropout linear regulator and circuit thereof Download PDF

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CN111367345A
CN111367345A CN202010452401.6A CN202010452401A CN111367345A CN 111367345 A CN111367345 A CN 111367345A CN 202010452401 A CN202010452401 A CN 202010452401A CN 111367345 A CN111367345 A CN 111367345A
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compensation
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load
resistor
pmos
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CN111367345B (en
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杨国江
王海波
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Jiangsu Changjing Technology Co.,Ltd.
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract

The invention discloses a compensation method for improving the full load stability of a low dropout linear regulator and a circuit thereof, wherein a method combining dynamic compensation and fixed compensation is adopted, the dynamic compensation adopts an MOS tube as a load detection tube of active compensation to mirror load current, and the MOS tube, a compensation capacitor in an RC fixed compensation network and an additionally arranged compensation capacitor form active compensation together, so that the compensation of a heavy load part in a load range is realized; the fixed compensation of the bias current source is realized by arranging a bias current source formed by MOS (metal oxide semiconductor) tubes to form a compensation resistor, replacing the compensation resistor in an RC (resistor-capacitor) fixed compensation network, completing the compensation of a light load part together with a compensation capacitor in the RC fixed compensation network, and combining dynamic compensation and fixed compensation, so that the optimal compensation in a full load range including light load and heavy load can be realized together.

Description

Compensation method for improving full load stability of low dropout linear regulator and circuit thereof
Technical Field
The invention relates to a linear voltage regulator, in particular to a compensation method for improving the full load stability of a low dropout linear regulator (LDO) and a circuit thereof, belonging to the technical field of integrated circuits.
Background
As portable electronic products are widely used in various aspects of work and life, higher requirements are made on the performance of the power supply, especially on the integration level, the system cost, performance indexes and the like. The linear voltage regulator LDO belongs to a voltage reduction circuit in a power supply, and in principle, the LDO adjusts its output impedance according to the change of a load resistance, thereby maintaining the output voltage stable. Two basic circuits of the LDO are the first structure LDOA of the conventional LDO shown in fig. 1 and the second structure LDOB of the conventional LDO shown in fig. 2, respectively, and the internal structures of the two structures and the compensation circuit are different, which results in slightly different positions of the compensation circuit, but the compensation principle is consistent and both are fixed RC compensation. In the LDOA of FIG. 1, the output of the error amplifier EA2 is connected to the NMOS transistor N2, and the compensation is a fixed RC compensation for N2; in the LDOB of FIG. 2, the output of the error amplifier EA is connected with the PMOS transistor P1, the compensation is a fixed RC compensation adopted for P1, and the compensation effects of the two fixed RC compensations are similar under light and heavy loads.
When the load current changes in a large range (becomes larger or smaller), the LDO needs a fast response to meet the load requirement, and then whether the LDO circuit can maintain a stable output is an important technique to have a proper compensation to ensure the loop stability of the LDO system without oscillation. However, in the conventional LDO circuit, the compensation resistor R and the compensation capacitor C in the internal compensation circuit are both fixed, that is, the zero point of the compensation is fixed, the compensation zero point is fz =1/2 pi RC, and the output pole fo =1/(2 pi RloadCout) = Iload/(2 pi Vout × Cout) varies with the load current, so that the fixed compensation zero point achieves the optimal compensation effect for a specific load condition, and the compensation effect for other load conditions is reduced, so that the stable conditions of light load and heavy load cannot be compatible when the output load varies in a large range. The relationship between stability and load is illustrated by a phase margin PM versus load current Iload. It is known that a system with a phase margin PM larger than 45 is stable, and below 45, the stability is poor, and even oscillation occurs when the phase margin PM is smaller than 0. Fig. 3 is a diagram illustrating a compensation effect of a conventional LDO with RC compensation biased to light load, because the compensation biased to light load is performed, the phase margin PM is much larger than 45 degrees at light load, and the loop stability is good, but at heavy load, the phase margin begins to decrease and is much smaller than 45 degrees, even a negative value may occur, which may cause the system to oscillate. Fig. 4 is a diagram illustrating a compensation effect of a conventional LDO with RC compensation biased to heavy load, because the compensation biased to heavy load results in a phase margin far greater than 45 degrees during heavy load, and a loop stability is good, but at a light load portion, the phase margin begins to drop far less than 45 degrees, and even a negative value may occur, which may cause a system to oscillate.
Disclosure of Invention
The invention aims to solve the defects in the prior art and provide a compensation method and a compensation circuit for improving the full-load stability of a low dropout linear regulator.
The technical scheme adopted by the invention is as follows: a compensation method for improving the stability of the whole load of a low dropout linear regulator is provided with an RC fixed compensation network consisting of a compensation resistor and a compensation capacitor, and is characterized in that a method of combining dynamic compensation and fixed compensation is adopted, namely, active compensation of mirror load current is adopted and fixed compensation of a bias current source is adopted, wherein, an MOS tube is adopted for the dynamic compensation to serve as a load detection tube for the active compensation to mirror the load current, the dynamic compensation, the compensation capacitor in the RC fixed compensation network and the compensation capacitor additionally arranged form active compensation, the zero point of the compensation is changed along with the load, and the compensation of a heavy load part in a load range can be realized; the fixed compensation of the bias current source is realized by arranging a bias current source formed by MOS (metal oxide semiconductor) tubes to form a compensation resistor, replacing the compensation resistor in an RC (resistor-capacitor) fixed compensation network, and completing the compensation of a light load part together with a compensation capacitor in the RC fixed compensation network, and the dynamic compensation and the fixed compensation are combined to jointly realize the optimal compensation in a full load range including the light load and the heavy load.
The compensation resistor formed by the bias current source formed by the MOS tube is arranged, the resistance value of the compensation resistor can be set through the bias current generated by the bias current source and the size of the MOS tube, and the optimal fixed compensation can be realized together with the compensation capacitor in the RC fixed compensation network.
One of the circuits for realizing the method is that the low dropout linear regulator comprises an error amplifier EA2, a PMOS tube P2, a power tube Ppower2, an NMOS tube N2, a compensation capacitor Cc2, feedback divider resistors Rfb11 and Rfb22, an equivalent series resistor Resr2 of an output capacitor Cout2, a load resistor Rload2 and an output capacitor Cout 2; the positive input end of an error amplifier EA2 is connected with a reference voltage Vref, the output end of the error amplifier EA2 is connected with one end of a compensation capacitor Cc2 and the grid of an NMOS tube N2, the source and the substrate of an NMOS tube N2 are grounded, the drain of an NMOS tube N2 is connected with the drain of a PMOS tube P2 and the grid of a power tube Ppower2, the grid of the PMOS tube P2 is connected with a bias voltage bias2, the source and the substrate of the PMOS tube P2 are connected with the source and the substrate of a power tube Ppower2 and are connected with a power supply VIN, the drain of the power tube Ppower2 is connected with one end of a feedback voltage dividing resistor Rfb11 and one end of an equivalent series resistor Resr2 and one end of a load resistor Rload2 and outputs a voltage Vout2, the other end of the load resistor Rload2 is grounded, the other end of the feedback resistor Rfb11 is connected with the negative input end of the error amplifier EA2 and one end of a feedback voltage dividing resistor Rfb 695 2, the other end of the feedback voltage dividing resistor Rfb;
the dynamic compensation device is characterized in that a PMOS tube P3, a PMOS tube P4, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5, an NMOS tube N6, an NMOS tube N7 and a compensation capacitor Cc22 are arranged, wherein the PMOS tube P3, the NMOS tube N3, the NMOS tube N4, the NMOS tube N7, the compensation capacitor Cc22 and the compensation capacitor Cc2 are used for realizing dynamic compensation together; the PMOS tube P4, the NMOS tube N5 and the NMOS tube N6 form a bias current source, and fixed compensation is realized together with the compensation capacitor Cc 2;
the source and the substrate of a PMOS tube P3 are connected with the source and the substrate of a PMOS tube P4 and connected with a power supply VIN, the grid of the PMOS tube P3 is connected with the grid of a power tube Ppower2, the drain of a PMOS tube P3 is connected with the drain and the grid of an NMOS tube N3 and the grid of an NMOS tube N4 and the grid of an NMOS tube N7, the drain of the PMOS tube P4 is connected with the drain and the grid of an NMOS tube N6 and connected with the grid of an NMOS tube N5, the source and the substrate of an NMOS tube N3 and the source and the substrate of an NMOS tube N6 are both grounded, the source and the substrate of an NMOS tube N4 and the source and the substrate of an NMOS tube N5 are both grounded, the drain of an NMOS tube N4 is connected with the drain of an NMOS tube N5 and the other end of a compensation capacitor Cc2, the drain of an NMOS tube N7 is connected with the output end of an error amplifier EA2, the source and the substrate of an NMOS tube N5962 are connected with one end of a compensation capacitor.
In one of the circuits, a compensation resistor formed by a bias current source composed of a PMOS transistor P4, an NMOS transistor N5 and an NMOS transistor N6 can be set according to the sizes of a bias current Ibias2 generated by the bias current source and NMOS transistors N5 and N6, and can realize optimal fixed compensation together with a compensation capacitor Cc 2: ron5=1/{(W/L5)*[ 2μnCoxIbias2/(W/L6)]1/2In which Ron5Is the linear on-resistance of the NMOS transistor N5, i.e. the compensation resistance formed as the bias current source, munIs the mobility of NMOS tube carriers, CoxIs gate oxide capacitance per unit area, W/L5Is the width-to-length ratio, W/L, of the NMOS transistor N56Is the width-to-length ratio of the NMOS transistor N6.
The second circuit for realizing the method comprises an error amplifier EA, a PMOS tube P1, a power tube Ppower, an NMOS tube N1, a compensation capacitor Cc1, feedback divider resistors Rfb1, Rfb2, an output capacitor Cout, a load resistor Rload and an equivalent series resistor Resr of the output capacitor Cout; the positive input end of the error amplifier EA is connected with a reference voltage Vref, the output of the error amplifier EA is connected with the grid of a PMOS tube P1, the source and the substrate of the PMOS tube P1 are connected with the source and the substrate of a power tube Ppower and are connected with a power supply VIN, the drain of the PMOS tube P1 is connected with the drain of an NMOS tube N1 and one end of a compensation capacitor Cc1, the source and the substrate of an NMOS tube N1 are grounded, the grid of an NMOS tube N1 is connected with a bias voltage bias, the drain of the power tube Ppower is connected with one end of a feedback divider resistor Rfb1, one end of an equivalent series resistor Resr and one end of a load resistor Rload and outputs a voltage Vout, the other end of the load resistor Rload is grounded, the other end of the feedback divider resistor Rfb1 is connected with the negative input end of the error amplifier EA and one end of a feedback divider resistor Rfb2, the other end of the feedback divider resistor Rfb2 is grounded;
the dynamic compensation device is characterized in that a PMOS tube P11, a PMOS tube P12, a PMOS tube P13, a PMOS tube Pc, an NMOS tube N11 and a compensation capacitor Cc11 are arranged, wherein the PMOS tube P13, the PMOS tube Pc, the compensation capacitor Cc11 and the compensation capacitor Cc1 realize dynamic compensation together; the PMOS tube P11, the PMOS tube P12 and the NMOS tube N11 form a bias current source, and the bias current source and the compensation capacitor Cc1 jointly realize fixed compensation;
the source electrode and the substrate of the PMOS tube P11 are connected with a power supply VIN, the grid electrode and the drain electrode of the PMOS tube P11 are connected with the grid electrode of the PMOS tube P12 and the drain electrode of the NMOS tube N11, the grid electrode of the NMOS tube N11 is connected with a bias voltage bias, the source electrode and the substrate of the NMOS tube N11 are grounded, the grid electrode of the PMOS tube P13 is connected with the grid electrode of the PMOS tube Pc, the drain electrode of the PMOS tube P1 and the grid electrode of the power tube Ppower, the drain electrode of the PMOS tube P13 is grounded through a compensation capacitor Cc11, the source electrode and the substrate of the PMOS tube P13 are connected with the source electrode and the substrate of the PMOS tube P12, the source electrode and the substrate of the PMOS tube Pc and the output end of an error amplifier EA2, and the drain electrode of the PMOS tube P.
In the second circuit, the compensation resistor formed by the bias current source composed of the PMOS transistor P11, the PMOS transistor P12 and the NMOS transistor N11 can be set according to the bias current Ibias generated by the bias current source and the sizes of the PMOS transistors P12 and P11, and can realize the best fixed compensation together with the compensation capacitor Cc 1: ronP12= 1/{(W/LP12)*[ 2μpCoxIbias/(W/LP11)]1/2In which RonP12Is the linear on-resistance of PMOS transistor P12, i.e. the compensation resistance formed as the bias current source, mupIs the mobility of the carrier of the PMOS tube, CoxIs gate oxide capacitance per unit area, W/LP12Is the width-to-length ratio, W/L, of the PMOS tube P12P11Is the width-to-length ratio of the PMOS transistor P11.
In the first circuit and the second circuit, all MOS tubes adopt enhancement type field effect tubes.
The invention has the advantages and obvious effects that: the invention adopts a method of combining dynamic compensation and fixed compensation, namely, active compensation of mirror image load current and fixed compensation of a bias current source are combined, the dynamic compensation adopts an MOS tube as a load detection tube of the active compensation to mirror the load current, the dynamic compensation, a compensation capacitor in an RC fixed compensation network and an additionally arranged compensation capacitor form active compensation together, the zero point of the compensation changes along with the load, and the compensation of a heavy-load part in a load range can be realized; the fixed compensation of the bias current source is realized by arranging a bias current source formed by MOS (metal oxide semiconductor) tubes to form a compensation resistor, replacing the compensation resistor in an RC (resistor-capacitor) fixed compensation network, completing the compensation of a light load part together with a compensation capacitor in the RC fixed compensation network, and combining dynamic compensation and fixed compensation, so that the optimal compensation in a full load range including light load and heavy load can be realized together.
Drawings
Fig. 1 is a first compensation circuit of a conventional LDO.
Fig. 2 is a second compensation circuit of the conventional LDO.
FIG. 3 is a diagram illustrating the compensation effect of a conventional LDO with RC compensation biased toward light load.
FIG. 4 is a diagram illustrating the compensation effect of a conventional LDO using RC to compensate for a heavy load.
FIG. 5 is a diagram showing the compensation effect of the present invention for both light and heavy loads.
Fig. 6 is a compensation circuit of the present invention for the circuit of fig. 1.
Fig. 7 is a compensation circuit of the present invention for the circuit of fig. 2.
Detailed Description
The invention adopts a method combining dynamic compensation and fixed compensation, the dynamic compensation adopts an MOS tube as a load detection tube of active compensation to mirror load current, the MOS tube, a compensation capacitor in an RC fixed compensation network and an additionally arranged compensation capacitor form active compensation together, the zero point of the compensation of the active compensation follows the change of a load, and the compensation of a heavy load part in a load range can be realized; the fixed compensation of the bias current source is realized by arranging a bias current source formed by MOS tubes to form a compensation resistor, replacing the compensation resistor in the RC fixed compensation network, and completing the compensation of a light load part together with a compensation capacitor in the RC fixed compensation network. The fixed compensation zero point is mainly used for compensating for light load, and the compensation effect is invalid because the load detection tube is approximately turned off under the light load. Therefore, the active compensation of the mirror load current and the fixed compensation of the bias current source are compensated together, because the active compensation zero point of the mirror load current changes along with the load, the optimal compensation of a heavy load part in a load range can be realized, the fixed compensation of a light load part is set through the bias current source, the optimal intersection point A (shown in figure 5) is set, the optimal phase margin from light load to heavy load can be ensured, and the condition that the fixed zero point of the fixed resistor is incompatible with light load and heavy load in the prior art is made up. The actual compensation effect is shown in fig. 5.
Fig. 6 is a circuit for implementing the present invention based on the prior art of fig. 1. The P4, the N6 and the N5 form a bias current source circuit, the N5 is matched with the compensation capacitor Cc2 to form a fixed compensation zero point, wherein the on-resistance of the N5 is a fixed resistance in fixed compensation. N5 mirrors the bias current in N6, and its on-resistance can be set according to the bias current. The bias voltage bias2 is converted into bias current Ibias2 through P4, and the current is the same because P4 and N6 are connected in series, i.e. IP4=IN6= Ibias 2. Gate potentials of N5 and N6 are the same, Vgs6=Vgs5. The current in N6 is the saturation region current, and the formula is as follows: i isN6=μnCox(Vgs6-Vthn)2/2*( W/L6). N5 is operating in the linear region, and the corresponding linear region current formula is as follows: i isN5=μnCox(Vgs5-Vthn)*Vds5*W/L5，
μnIs the mobility of electron carriers, CoxThe capacitance of a gate oxide layer in unit area is obtained, W/L is the width-to-length ratio of an output tube, Vgs is the voltage difference of a gate source of an NMOS tube, Vthn is the threshold value of the NMOS tube, and Vds is the voltage difference between drain sources of an MOS.
The resistance for linear conduction of N5 is:
Ron5=Vds5/IN5= 1/[ W/L5*μnCox(Vgs5-Vthn)]=1/{( W/L5)*[ 2μnCoxIN6/（W/L6）]1/2}
=1/{( W/L5)*[ 2μnCoxIbias2/（W/L6）]1/2}；
compensation zero fzN5=1/(2πRonN5Cc)= ( W/L5)*[ 2μnCoxIbias2/（W/L6）]1/2/(2πCc2)；
Therefore, the position of the compensation zero point can be adjusted by adjusting the bias current Ibias2 and the size ratio of N6 and N5, the size ratio conditions of Ibias2 and N6 and N5 are fixed, the zero point is correspondingly fixed, and the zero point is set to perform optimal compensation for light load.P 3 mirrors the Ppower current, and is simultaneously mirrored to N4 and N7 through N3, so that N4 and N7 mirror the load current Iload2 of Ppower 2. The ratio of currents of Ppower and P3 is 1: n, P3 and N3 are equal IN current, IP3= IN3= N x Iload. Where N5 and Cc2 form the compensation zero.
IN3=μnCox(Vgs3-Vthn)2/2*( W/L3),
IN4=μnCox(Vgs4-Vthn)*Vds4*W/L4,
The resistance for linear conduction of N4 is:
Ron4=Vds4/IN4= 1/[ W/L4*μnCox(Vgs-Vth)]=1/{( W/L4)*[ 2μnCoxIN6/（W/L3）]1/2}
=1/{( W/L4)*[ 2μnCoxn*Iload/（W/L3）]1/2}；
compensation zero fzN4=1/(2πRonN4Cc2)= ( W/L4)*[ 2μnCoxn*Iload/（W/L3）]1/2/(2πCc2)；
Similarly, N7 and C22 form the compensation zero:
fzN7=1/(2πRonN7Cc22)= ( W/L7)*[ 2μnCoxn*Iload/（W/L3）]1/2/(2πCc2)；
an output pole fo2=1/(2 pi rlload 2Cout2) = Iload2/(2 pi Vout 2Cout 2);
since Ppower outputs the load current, as the load current Iload increases, the on-resistances of N4 and N7 decrease, and the corresponding compensation zero fzN4And fzN7Enlarging; similarly, the load current decreases, the on-resistances of N4 and N7 increase, and the corresponding compensation zero fzN4And fzN7The effect of the output pole fo2 can be effectively eliminated. It is therefore possible to set an excellent phase margin in the band-load range. Since the optimum value of the on-resistance setting of N5 is a fixed value, and the on-resistances of N4 and N7 increase with the decrease of the load current, especially approaching infinity at no load, while the on-resistance of N5 does not change, the compensation of N5 and Cc2 is mainly used at light load, and the compensation of N4 and Cc2, N7 and Cc22 is mainly used at heavy load, so that two compensations will have approximately a certain load value corresponding to a crossing point a, and the position of the point in the graph of the phase margin to the load current can be changed by adjusting the proportions of the bias current Ibias2 and N5 and N6, thereby realizing excellent phase margin, i.e. excellent full load compensation effect, in the full load range from light load to heavy load.
Fig. 7 is another embodiment circuit of the present invention based on the prior art of fig. 2. Wherein, P11, N11 and P12 constitute a bias current source, bias voltage bias is converted into bias current Ibias through N11, N11 and P11 are connected in series, the currents are equal, namely IN11=IP11= Ibias. The P12 is matched with the compensation capacitor Cc1 to form a compensation zero point, and the on-resistance of P12 is the fixed resistance in the fixed compensation. The on-resistance of P12 may be set according to the bias current and the size of the mirror tubes P12 and P11. RonP12= 1/{( W/LP12)*[ 2μpCoxIbias/（W/LP11）]1/2}，The optimum position of the compensation zero can thus be adjusted accordingly.
Pc and P13 mirror the load current Iload of Ppower, and Pc and Cc1, P13 and C11 form a compensation zero point.
Compensation zero fzP12=1/(2πRonP12Cc1)= ( W/LP12)*[ 2μpCoxIbias2/（W/LP11）]1/2/(2πCc1)；
Compensation zero fzPc=1/(2πRonPcCc1)= ( W/LPc)*[ 2μpCoxn*Iload/（W/LPpower）]1/2/(2πCc1)；
fzP13=1/(2πRonP13Cc11)= ( W/L13)*[ 2μpCoxn*Iload/（W/LPpower）]1/2/(2πCc1)；
An output pole fo =1/(2 pi RloadCout) = Iload/(2 pi Vout Cout);
as the load current increases, the on-resistances of Pc and P13 decrease accordingly, and the corresponding compensation zero point becomes large, so that an excellent phase margin can be set in the band-load range. Since the optimum value of the on-resistance setting of the P12 is a fixed value, and the on-resistances of Pc and P13 decrease with the increase of the load current, the compensation of P12 and Cc1 is mainly used in light load, and Pc and Cc1, P13 and Cc11 are mainly used in heavy load, so that two kinds of compensation approximately have a certain load value corresponding to a cross point a, and the position of the cross point in the phase margin versus load current diagram can be changed by adjusting the bias current of P12 and the proportion of P12 and P11, thereby realizing excellent phase margin, namely excellent full load compensation effect, in the full load range from light load to heavy load.
Fig. 6 and 7 are compensation circuits in which active load compensation and bias current source fixed compensation are combined on the basis of a linear regulator provided with an RC fixed compensation network formed by a compensation resistor and a compensation capacitor in the prior art, and the circuit structures of the prior art parts of the linear regulator with the RC fixed compensation network in fig. 6 and 7 are slightly different, which results in a difference in the position of added compensation, but the compensation principles are the same, namely active compensation introducing mirror load current and fixed compensation of a bias current source, and the problem that light load and heavy load stability cannot be compatible is obviously improved by combining the two compensation circuits. In fig. 6, the output of EA2 directly drives the NMOS transistor N2, so for N2 compensation, active compensation of mirror load current N4 and N7 requires mirroring the current of Ppower2, directly mirroring the current of Ppower2 through P3, and the current of P3 is equal to the current of N3, which can be proportional to the current of Ppower2 by detecting the gate of N3. The fixed compensation of the bias current source adopts the bias current of a mirror P4, and since the N6 and the P4 are equal in current, the N5 is proportional to the bias current of the P4 by detecting the grid of the N6. In fig. 7, because the EA output drives the PMOS transistor P1, for the compensation of P1, the active compensation of the mirror load current Pc and P13 requires the current of the mirror power supply Ppower, and the gate of the Ppower can be directly detected, i.e. proportional to the Ppower current can be realized; the fixed compensation of the bias current source adopts the bias current of the mirror N11, and since the N11 and the P11 are equal in current, the P12 is proportional to the bias current of the N11 by detecting the gate of the P11.

Claims (8)

1. A compensation method for improving the stability of the whole load of a low dropout linear regulator is provided with an RC fixed compensation network consisting of a compensation resistor and a compensation capacitor, and is characterized in that a method of combining dynamic compensation and fixed compensation is adopted, namely, active compensation of mirror load current is adopted and fixed compensation of a bias current source is adopted, wherein, an MOS tube is adopted for the dynamic compensation to serve as a load detection tube for the active compensation to mirror the load current, the dynamic compensation, the compensation capacitor in the RC fixed compensation network and the compensation capacitor additionally arranged form active compensation, the zero point of the compensation is changed along with the load, and the compensation of a heavy load part in a load range can be realized; the fixed compensation of the bias current source is realized by arranging a bias current source formed by MOS (metal oxide semiconductor) tubes to form a compensation resistor, replacing the compensation resistor in an RC (resistor-capacitor) fixed compensation network, and completing the compensation of a light load part together with a compensation capacitor in the RC fixed compensation network, and the dynamic compensation and the fixed compensation are combined to jointly realize the optimal compensation in a full load range including the light load and the heavy load.
2. The compensation method for improving the full load stability of the LDO according to claim 1, wherein the compensation resistor formed by the bias current source formed by the MOS transistor, the resistance value of which is set by the bias current generated by the bias current source and the size of the MOS transistor, is capable of achieving the optimal fixed compensation together with the compensation capacitor in the RC fixed compensation network.
3. The circuit for realizing the compensation method for improving the full load stability of the low dropout linear regulator according to claim 1, wherein the low dropout linear regulator comprises an error amplifier EA2, a PMOS tube P2, a power tube Ppower2, an NMOS tube N2, a compensation capacitor Cc2, feedback voltage dividing resistors Rfb11 and Rfb22, and an equivalent series resistor Resr2 of an output capacitor Cout2, a load resistor Rload2 and an output capacitor Cout 2; the positive input end of an error amplifier EA2 is connected with a reference voltage Vref, the output end of the error amplifier EA2 is connected with one end of a compensation capacitor Cc2 and the grid of an NMOS tube N2, the source and the substrate of an NMOS tube N2 are grounded, the drain of an NMOS tube N2 is connected with the drain of a PMOS tube P2 and the grid of a power tube Ppower2, the grid of the PMOS tube P2 is connected with a bias voltage bias2, the source and the substrate of the PMOS tube P2 are connected with the source and the substrate of a power tube Ppower2 and are connected with a power supply VIN, the drain of the power tube Ppower2 is connected with one end of a feedback voltage dividing resistor Rfb11 and one end of an equivalent series resistor Resr2 and one end of a load resistor Rload2 and outputs a voltage Vout2, the other end of the load resistor Rload2 is grounded, the other end of the feedback resistor Rfb11 is connected with the negative input end of the error amplifier EA2 and one end of a feedback voltage dividing resistor Rfb 695 2, the other end of the feedback voltage dividing resistor Rfb;
the dynamic compensation device is characterized in that a PMOS tube P3, a PMOS tube P4, an NMOS tube N3, an NMOS tube N4, an NMOS tube N5, an NMOS tube N6, an NMOS tube N7 and a compensation capacitor Cc22 are arranged, wherein the PMOS tube P3, the NMOS tube N3, the NMOS tube N4, the NMOS tube N7, the compensation capacitor Cc22 and the compensation capacitor Cc2 are used for realizing dynamic compensation together; the PMOS tube P4, the NMOS tube N5 and the NMOS tube N6 form a bias current source, and fixed compensation is realized together with the compensation capacitor Cc 2;
the source and the substrate of a PMOS tube P3 are connected with the source and the substrate of a PMOS tube P4 and connected with a power supply VIN, the grid of the PMOS tube P3 is connected with the grid of a power tube Ppower2, the drain of a PMOS tube P3 is connected with the drain and the grid of an NMOS tube N3 and the grid of an NMOS tube N4 and the grid of an NMOS tube N7, the drain of the PMOS tube P4 is connected with the drain and the grid of an NMOS tube N6 and connected with the grid of an NMOS tube N5, the source and the substrate of an NMOS tube N3 and the source and the substrate of an NMOS tube N6 are both grounded, the source and the substrate of an NMOS tube N4 and the source and the substrate of an NMOS tube N5 are both grounded, the drain of an NMOS tube N4 is connected with the drain of an NMOS tube N5 and the other end of a compensation capacitor Cc2, the drain of an NMOS tube N7 is connected with the output end of an error amplifier EA2, the source and the substrate of an NMOS tube N5962 are connected with one end of a compensation capacitor.
4. The circuit of the compensation method for improving the full load stability of the low dropout linear regulator according to claim 3, wherein the compensation resistor formed by the bias current source composed of the PMOS transistor P4, the NMOS transistor N5 and the NMOS transistor N6 is configured according to the sizes of the bias current Ibias2 generated by the bias current source and the NMOS transistors N5 and N6, so that the compensation resistor and the compensation capacitor Cc2 can jointly realize the optimal fixed compensation: ron5=1/{( W/L5)*[ 2μnCoxIbias2/（W/L6）]1/2In which Ron5Is the linear on-resistance of the NMOS transistor N5, i.e. the compensation resistance formed as the bias current source, munIs the mobility of NMOS tube carriers, CoxIs gate oxide capacitance per unit area, W/L5Is the width-to-length ratio, W/L, of the NMOS transistor N56Is the width-to-length ratio of the NMOS transistor N6.
5. The circuit of the compensation method for improving the full load stability of the low dropout linear regulator according to claim 3, wherein all MOS transistors in the circuit adopt enhancement mode field effect transistors.
6. The circuit for realizing the compensation method for improving the full load stability of the low dropout linear regulator according to claim 1, wherein the low dropout linear regulator comprises an error amplifier EA, a PMOS tube P1, a power tube Ppoper, an NMOS tube N1, a compensation capacitor Cc1, feedback voltage dividing resistors Rfb1 and Rfb2, and an equivalent series resistor Resr of an output capacitor Cout, a load resistor Rload and an output capacitor Cout; the positive input end of the error amplifier EA is connected with a reference voltage Vref, the output of the error amplifier EA is connected with the grid of a PMOS tube P1, the source and the substrate of the PMOS tube P1 are connected with the source and the substrate of a power tube Ppower and are connected with a power supply VIN, the drain of the PMOS tube P1 is connected with the drain of an NMOS tube N1 and one end of a compensation capacitor Cc1, the source and the substrate of an NMOS tube N1 are grounded, the grid of an NMOS tube N1 is connected with a bias voltage bias, the drain of the power tube Ppower is connected with one end of a feedback divider resistor Rfb1, one end of an equivalent series resistor Resr and one end of a load resistor Rload and outputs a voltage Vout, the other end of the load resistor Rload is grounded, the other end of the feedback divider resistor Rfb1 is connected with the negative input end of the error amplifier EA and one end of a feedback divider resistor Rfb2, the other end of the feedback divider resistor Rfb2 is grounded;
the dynamic compensation device is characterized in that a PMOS tube P11, a PMOS tube P12, a PMOS tube P13, a PMOS tube Pc, an NMOS tube N11 and a compensation capacitor Cc11 are arranged, wherein the PMOS tube P13, the PMOS tube Pc, the compensation capacitor Cc11 and the compensation capacitor Cc1 realize dynamic compensation together; the PMOS tube P11, the PMOS tube P12 and the NMOS tube N11 form a bias current source, and the bias current source and the compensation capacitor Cc1 jointly realize fixed compensation;
the source electrode and the substrate of the PMOS tube P11 are connected with a power supply VIN, the grid electrode and the drain electrode of the PMOS tube P11 are connected with the grid electrode of the PMOS tube P12 and the drain electrode of the NMOS tube N11, the grid electrode of the NMOS tube N11 is connected with a bias voltage bias, the source electrode and the substrate of the NMOS tube N11 are grounded, the grid electrode of the PMOS tube P13 is connected with the grid electrode of the PMOS tube Pc, the drain electrode of the PMOS tube P1 and the grid electrode of the power tube Ppower, the drain electrode of the PMOS tube P13 is grounded through a compensation capacitor Cc11, the source electrode and the substrate of the PMOS tube P13 are connected with the source electrode and the substrate of the PMOS tube P12, the source electrode and the substrate of the PMOS tube Pc and the output end of an error amplifier EA2, and the drain electrode of the PMOS tube P.
7. The circuit of the compensation method for improving the full load stability of the low dropout linear regulator according to claim 6, wherein the compensation resistor formed by the bias current source composed of the PMOS transistor P11, the PMOS transistor P12 and the NMOS transistor N11 is configured according to the bias current Ibias generated by the bias current source and the sizes of the PMOS transistors P12 and P11, so as to achieve the optimal fixed compensation together with the compensation capacitor Cc 1: ronP12= 1/{(W/LP12)*[ 2μpCoxIbias/(W/LP11)]1/2In which RonP12Is the linear on-resistance of PMOS transistor P12, i.e. the compensation resistance formed as the bias current source, mupIs the mobility of the carrier of the PMOS tube, CoxIs gate oxide capacitance per unit area, W/LP12Is the width-to-length ratio, W/L, of the PMOS tube P12P11Is the width-to-length ratio of the PMOS transistor P11.
8. The circuit according to claim 6, wherein all the MOS transistors in the circuit are enhancement mode FETs.
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113176802A (en) * 2021-04-16 2021-07-27 中山大学 Self-feedback multi-loop fully-integrated low-dropout linear regulator circuit
CN113190076A (en) * 2021-04-27 2021-07-30 无锡力芯微电子股份有限公司 Phase compensation circuit and method for satisfying self-adaptive linear voltage regulator under different loads
CN113741608A (en) * 2021-08-30 2021-12-03 普冉半导体(上海)股份有限公司 Linear voltage regulator circuit
CN113970949A (en) * 2021-12-27 2022-01-25 江苏长晶科技股份有限公司 High-speed linear voltage stabilizer with quick response
CN114510107A (en) * 2022-04-21 2022-05-17 江苏长晶科技股份有限公司 LDO circuit for improving full-load stability
CN115079760A (en) * 2022-04-18 2022-09-20 深圳市中科蓝讯科技股份有限公司 Low dropout regulator and chip
CN115167603A (en) * 2022-08-09 2022-10-11 北京同芯科技有限公司 Loop high-stability LDO circuit and method based on dynamic zero point following compensation
CN115480610A (en) * 2022-11-04 2022-12-16 国仪量子(合肥)技术有限公司 Pulse signal conditioning circuit and electronic equipment
KR102671240B1 (en) 2021-04-27 2024-06-03 우시 이텍 마이크로일렉트로닉스 컴퍼니 리미티드 Phase compensation circuit and method for self-adaptive linear regulator to meet different load requirements

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201616035U (en) * 2009-04-28 2010-10-27 Bcd半导体制造有限公司 Enhanced miller compensation low dropout linear regulator
CN103309384A (en) * 2012-03-16 2013-09-18 擎泰科技股份有限公司 Voltage regulator with adaptive miller compensation
WO2015130361A1 (en) * 2014-02-28 2015-09-03 Google Inc. Compensating a voltage regulator
CN106774581A (en) * 2017-01-25 2017-05-31 杭州士兰微电子股份有限公司 Low pressure difference linear voltage regulator and integrated system-on-chip
CN107688366A (en) * 2017-08-28 2018-02-13 广州慧智微电子有限公司 A kind of implementation method of LDO circuit and LDO

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201616035U (en) * 2009-04-28 2010-10-27 Bcd半导体制造有限公司 Enhanced miller compensation low dropout linear regulator
CN103309384A (en) * 2012-03-16 2013-09-18 擎泰科技股份有限公司 Voltage regulator with adaptive miller compensation
WO2015130361A1 (en) * 2014-02-28 2015-09-03 Google Inc. Compensating a voltage regulator
CN106774581A (en) * 2017-01-25 2017-05-31 杭州士兰微电子股份有限公司 Low pressure difference linear voltage regulator and integrated system-on-chip
CN107688366A (en) * 2017-08-28 2018-02-13 广州慧智微电子有限公司 A kind of implementation method of LDO circuit and LDO

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113176802A (en) * 2021-04-16 2021-07-27 中山大学 Self-feedback multi-loop fully-integrated low-dropout linear regulator circuit
CN113190076A (en) * 2021-04-27 2021-07-30 无锡力芯微电子股份有限公司 Phase compensation circuit and method for satisfying self-adaptive linear voltage regulator under different loads
KR102671240B1 (en) 2021-04-27 2024-06-03 우시 이텍 마이크로일렉트로닉스 컴퍼니 리미티드 Phase compensation circuit and method for self-adaptive linear regulator to meet different load requirements
CN113741608B (en) * 2021-08-30 2022-11-08 普冉半导体(上海)股份有限公司 Linear voltage regulator circuit
CN113741608A (en) * 2021-08-30 2021-12-03 普冉半导体(上海)股份有限公司 Linear voltage regulator circuit
CN113970949A (en) * 2021-12-27 2022-01-25 江苏长晶科技股份有限公司 High-speed linear voltage stabilizer with quick response
CN113970949B (en) * 2021-12-27 2022-03-29 江苏长晶科技股份有限公司 High-speed linear voltage stabilizer with quick response
CN115079760A (en) * 2022-04-18 2022-09-20 深圳市中科蓝讯科技股份有限公司 Low dropout regulator and chip
CN114510107A (en) * 2022-04-21 2022-05-17 江苏长晶科技股份有限公司 LDO circuit for improving full-load stability
CN115167603A (en) * 2022-08-09 2022-10-11 北京同芯科技有限公司 Loop high-stability LDO circuit and method based on dynamic zero point following compensation
CN115167603B (en) * 2022-08-09 2022-12-27 北京同芯科技有限公司 Loop high-stability LDO circuit and method based on dynamic zero point following compensation
WO2024031742A1 (en) * 2022-08-09 2024-02-15 北京同芯科技有限公司 High-loop-stability ldo circuit based on load-dependent zero mobile compensation, and method
CN115480610A (en) * 2022-11-04 2022-12-16 国仪量子(合肥)技术有限公司 Pulse signal conditioning circuit and electronic equipment

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