CN208752489U - A kind of electric power management circuit in battery management chip - Google Patents
A kind of electric power management circuit in battery management chip Download PDFInfo
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- CN208752489U CN208752489U CN201821849359.6U CN201821849359U CN208752489U CN 208752489 U CN208752489 U CN 208752489U CN 201821849359 U CN201821849359 U CN 201821849359U CN 208752489 U CN208752489 U CN 208752489U
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Abstract
The electric power management circuit that the utility model is provided in a kind of battery management chip provides supply voltage, current offset, including pre- Voltage stabilizing module, linear voltage stabilization module and bias current generation module for the disparate modules in chip；Input voltage successively generates pre- voltage of voltage regulation VPR, voltage of voltage regulation VREG and bias current Ibias by pre- Voltage stabilizing module, linear voltage stabilization module and bias current generation module respectively.The utility model has the advantages that: circuit can produce stable voltage under conditions of high input voltage, to provide stable power supply for each module in power management IC.Outputting current steadily, driving capability are big.Electric power management circuit in battery management chip is low in energy consumption, facilitates the overall power for controlling chip.Circuit structure is easily achieved, and is suitble to engineer application.
Description
Technical field
The utility model relates to electronic circuit fields, and in particular to the electric power management circuit in a kind of battery management chip.
Background technique
It is well known that supply voltage needed for functional module in battery management system is lower, often in 5V or less.But
The total voltage of the series-connected cell group inputted under certain applications is then higher, such as: electric bicycle 36V, 48V, electric car are
400V etc..Therefore, how the higher voltage of battery pack is converted into low pressure required for suitable battery management system accessory power supply just
It is the difficult point of Major Systems design.
The modules such as simulation, number, control logic in battery management chip (BMIC) need to work at lower voltages,
This just needs to convert above-mentioned high voltage to the voltage or electric current suitable for the work of these modules.And this just needs corresponding power supply
Manage circuit.
And the electric power management circuit in battery management chip has the disadvantage in that in the prior art
1) high input voltage is being down to the supply voltage used for modules such as simulation, number, control logics in BMIC
During, often the complexity of circuit design is higher, and can generate larger power consumption；
2) variation of high input voltage power supply often has an impact the size of pressure stabilizing output, while circuit is in height input electricity
Circuit is often complex when the functions such as overcurrent, overheat protector are realized in pressure；
3) variation of environment temperature can have an impact the bias current size that circuit provides, and lead to current offset size not
Accurately.
Utility model content
In order to solve the above problem:
It is according to the present utility model in a first aspect, the utility model proposes the power managements in a kind of battery management chip
Circuit: including pre- Voltage stabilizing module, linear voltage stabilization module and bias current generation module；
Pre- Voltage stabilizing module carries out pre- pressure stabilizing to input voltage VPP, obtains a relatively low voltage VPR；
Linear voltage stabilization module includes band-gap reference function, obtains the pressure stabilizing electricity of low-temperature coefficient by pre- voltage of voltage regulation VPR
Press VREG；
Bias current generation module converts voltage of voltage regulation VREG to the bias current Ibias of low-temperature coefficient.
Preferably, the input voltage VPP is up to 80V or higher voltage.
Preferably, the pre- Voltage stabilizing module includes pre- pressure stabilizing starting module and pre- pressure stabilizing nucleus module.
Pre- pressure stabilizing starting module carries out circuit start, and starting bias current is generated after circuit start；
In order to reduce the power consumption of pre- pressure stabilizing starting module:
Mega-ohms resistance is set in pre- pressure stabilizing starting module；The resistance of the mega-ohms is series at pre- pressure stabilizing starting module
Power supply and ground access in.
Pre- pressure stabilizing nucleus module generates pre- voltage of voltage regulation VPR；Passed through after current mirror mirror by the way that bias current will be started
Zener diode and resistance generate pre- voltage of voltage regulation VPR.
Preferably, the linear voltage stabilization module includes that circuit for starting up band gap basis, band-gap reference circuit and voltage of voltage regulation are raw
At module.
Circuit for starting up band gap basis starts band-gap reference circuit；
Band-gap reference circuit generates bandgap voltage reference VBGR；
Bandgap voltage reference VBGR is generated voltage of voltage regulation by electric resistance partial pressure and voltage amplification by voltage of voltage regulation generation module
VREG。
In order to preferably detect the electric power management circuit working condition in the utility model battery management chip:
It is further preferred that the linear voltage stabilization module further includes overcurrent protection module, overcurrent protection module detection load
Whether electric current is more than preset limit.
Preferably, the bias current generation module includes ICTAT generation circuit, IPTAT generation circuit and reference current
Generation module；
ICTAT generation circuit generates the electric current ICTAT being inversely proportional with absolute temperature；
The electric current IPTAT that IPTAT generation circuit generates and absolute temperature is proportional；
ICTAT and IPTAT is combined by proper ratio and is generated bias current Ibias by reference current generation module.
In order to preferably detect the electric power management circuit working condition in the utility model battery management chip:
It is further preferred that the bias current generation module further includes overheat protector module；Overcurrent protection module detection
Whether the temperature of the electric power management circuit in battery management chip is more than limitation.
It is further preferred that the pre- pressure stabilizing starting module includes resistance R1, R2, NMOS transistor MN1, MN2；
A termination input voltage VPP of resistance R1, the drain electrode of the grid and MN2 of another termination MN1 of resistance R1；MN2's
Source level ground connection, MN2 grid connecting resistance R2 one end and MN1 source electrode；The other end of resistance R2 is grounded；The drain electrode conduct of MN1
The output end of pre- pressure stabilizing starting module 111 connects pre- pressure stabilizing nucleus module 112, output starting bias current Ib.
It is further preferred that the pre- pressure stabilizing nucleus module includes PMOS transistor MP1-MP6；NMOS transistor MN3-
MN5；Zener diode D1 and resistance R3；
The drain electrode of grid, MP2 of MP2 is connected with the grid of MP4, while connecting the output of pre- pressure stabilizing starting module 111
End, input starting bias current Ib；The drain electrode of the source electrode of MP2, the grid of MP1, MP1 is connected with the grid of MP3；The source of MP1
The source level of grade and MP3 meet input voltage VPP；The drain electrode of MP3 is connected with the source electrode of MP4；
The drain electrode of grid, MN3 of MN3 is connected with the grid of MN5, while connecting the drain electrode of MP4, and as first node
Output voltage Vb1；The drain electrode of the source electrode of MN3, the grid of MN4, MN4 is connected with the grid of MN6, and exports as second node
Voltage Vb2；The source level of MN4 and the source level ground connection of MN6；The drain electrode of MN6 is connected with the source electrode of MN5；
The drain electrode of grid, MP5 of MP5 is connected with the grid of MP6, while connecting the drain electrode of MN5；The drain electrode of MP6 connects
One end of zener diode D1 exports pre- voltage of voltage regulation VPR as output end；The one of the other end connection resistance R3 of diode D1
End；The other end of resistance R3 is grounded.
It is further preferred that pre- voltage of voltage regulation VPR is generated linearly by NMOS transistor MN9 in the linear voltage stabilization module
The supply voltage VAPR of Voltage stabilizing module；Pre- voltage of voltage regulation VPR connects the grid of MN9；Input voltage VPP connects the drain of MN9；MN9's
Source electrode meets supply voltage VAPR.
Still more preferably, the circuit for starting up band gap basis includes PMOS transistor MP8, MP11；NMOS transistor
MN7,MN8；
The drain electrode that the grid that the source level of MP8 meets supply voltage VAPR, MP8 connects the source level, MP8 of node B1 and MP11 meets MP11
Grid and MN7 drain electrode；The drain electrode of MP11 meets bandgap voltage reference VBGR；The grid of MN7 connects the source of first node Vb1, MN7
Grade connects the drain electrode of MN8；The grid of MN8 connects the source level ground connection of second node Vb2, MN8.
Still more preferably, the band-gap reference circuit includes PMOS transistor MP9, MP10；NPN triode Q1, Q2；
Resistance R6, R7；
MP9 and MP10 forms current mirror；The source level of MP9 and the source level of MP10 meet supply voltage VAPR；The grid of MP9 with
The drain electrode of MP9, the grid of MP10 and Q1 collector are connected to node B1；The drain electrode of MP10 and Q2 collector are connected to node B2；
The base stage of Q1 and the base stage of Q2 meet bandgap voltage reference VBGR；The emitter of Q1 is connected to VPTAT by the emitter of R6 and Q2；
The other end ground connection of termination VPTAT, R7 of R7.
Still more preferably, the voltage of voltage regulation generation module includes PMOS transistor MP13；NMOS transistor MN10,
MN11,MN12；NPN triode Q3, Q4；Resistance R4, R5, RL；Potentiometer RT, capacitor CL；
The drain electrode of the grid, MP13 of MP13 meets node B3；The source level of MP13 meets input voltage VPP；The grid of MN11 connects pre-
The source electrode that the drain electrode of voltage of voltage regulation VPR, MN11 meet node B3, MN11 connects the collector of Q3；The grid of MN12 connects pre- voltage of voltage regulation
The source electrode that the drain electrode of VPR, MN12 meet input voltage VPP, MN12 connects the collector of Q4；The electric current that the collector of Q3 flows through is IOC；
The source level that the grid that the drain electrode of MN10 meets supply voltage VAPR, MN10 meets node B2, MN10 meets node A；A terminated nodes of R4
A, one end of another termination potentiometer RT of R4；The other end of potentiometer RT passes through R5 ground connection, the adjusting terminal strip of potentiometer RT
Gap reference voltage VBGR；The base stage of Q3 and Q4 meets the emitter output voltage of voltage regulation VREG of node A, Q3 and Q4；The one of RL and CL
Terminate the other end ground connection of voltage of voltage regulation VREG, RL and CL.
Still more preferably, the overcurrent protection module includes PMOS transistor MP12；NPN triode Q5-Q7；Resistance
R8, zener diode D4；
The drain electrode that the grid that the source level of MP12 meets input voltage VPP, MP12 meets node B3, MP12 meets node B；Q5 and Q6 group
At current mirror, the collector of Q5 meets node B2；The base stage of Q5, the base stage of Q6, Q6 collector connect one end of D4；The other end of D4
Meet node B；The emitter of Q5 and the emitter ground connection of Q6；The other end of terminated nodes B, R8 and the collector of Q6 and base of R8
Extremely it is connected；The emitter of Q7 is grounded.
Still more preferably, the ICTAT generation circuit includes PMOS transistor MP31；NPN triode Q35；Resistance
R32；
The drain electrode that the drain electrode that the source level of MP31 connects the grid and MP31 of voltage of voltage regulation VREG, MP31 meets node C1, MP31 connects
The collector of Q35；The electric current of the drain electrode of MP31 is ICTAT；The emitter that the base stage of Q35 meets node C2, Q35 is grounded by R32.
Still more preferably, the IPTAT generation circuit includes PMOS transistor MP32-MP34；NMOS transistor
MN31,MN32；NPN triode Q31-Q34, Q36；Resistance R31；
MP32, MP33 and MP34 form current mirror, Q33 and Q34 composition current mirror, MN31 and MN32 and form current mirror；
The grid of MP32, the grid of MP33, the drain electrode of MP33 and pole MP34 grid be connected to node C3；The source of MP32
The source level of grade, the source level of MP33 and MP34 meets voltage of voltage regulation VREG；The drain electrode of the drain of MP32 and MN32, MN32 grid,
The grid of MN31 is connected；The source electrode of MN32 and the source electrode ground connection of MN31；The drain electrode of MN31 connects the emitter of Q36；The base stage of Q36 connects
The collector of node C3, Q36 meet voltage of voltage regulation VREG；The collector of Q33 meets node C3；The base stage of Q33, the base stage of Q34 and Q34
Collector meet node C2；The emitter of the base stage of Q31, the collector of Q32 and Q34 is connected in node B；The base stage of Q32, Q31
Collector and the emitter of Q33 be connected in node A；The emitter of Q31 is grounded by R31；The emitter of Q32 is grounded.
Still more preferably, the reference current generation module includes PMOS transistor MP37, MP38；The grid of MP37
The grid for meeting node C3, MP38 meets node C1；The source level of MP37 and the source level of MP38 meet voltage of voltage regulation VREG；The drain of MP37 and
The drain of MP38 links together output bias current Ibias.
Still more preferably, the overheat protector module includes PMOS transistor MP35, MP36；NMOS transistor
MN33,；NPN triode Q37；Resistance R33, R34；Logic circuit T31；
The grid of MP35 and the grid of MP36 meet node C3；The source electrode of MP35 and the source electrode of MP36 meet voltage of voltage regulation VREG；
The drain electrode of MP35 connects the base stage of Q37 and one end of R33；One end of another termination R34 of R33 and the drain electrode of MN33；R34's is another
The source electrode of end and MN33 are grounded；The collector of Q37 connects the drain electrode of MP36 and the input of T31；The emitter of Q37 is grounded；T31's is defeated
It is out logical signal VOTP；The state of logical signal VOTP show the electric power management circuit in battery management chip temperature whether
More than limitation.
The specific technical solution of the utility model is as follows:
Second aspect according to the present utility model, the utility model proposes the power managements in application battery management chip
The battery management chip of circuit, the electric power management circuit in battery management chip provide supply voltage, electric current for chip internal module
Biasing.
Preferably, the electric power management circuit in battery management chip provides overcurrent protection, excess temperature guarantor for battery management chip
The function of shield.
Preferably, the electric power management circuit in battery management chip is to the analog- and digital- module mould in battery management chip
Number converter, high voltage multiplexers, digital filter, logic circuit control circuit, communication bus provide voltage or electric current.
It is further preferred that the battery management chip is used to monitor the electricity of each battery unit in multi-section lithium ion battery
Pressure and electric current calculate the state-of-charge of battery unit, and carry out to each battery unit balanced.
Still more preferably, the battery management chip is monitored in multi-section lithium ion battery by high voltage multiplexers
The voltage and current of each battery unit.
The utility model has the advantage that
1, circuit can produce stable voltage under conditions of high input voltage, to for each module in power management IC
Stable power supply is provided.Output voltage varies less under the wide variation of input voltage.
Especially the variation of 8~80V of input voltage when, output voltage only changes 9.4mV.
2, outputting current steadily, driving capability are big.
3, the electric power management circuit in battery management chip is low in energy consumption, facilitates the overall power for controlling chip.
4, circuit structure is easily achieved, and is suitble to engineer application.
Detailed description of the invention
It, below will be right in order to illustrate more clearly of specific embodiment of the present invention or technical solution in the prior art
Specific embodiment or attached drawing needed to be used in the description of the prior art are briefly described, it should be apparent that, it is described below
In attached drawing be that some embodiments of the utility model are not paying creativeness for those of ordinary skill in the art
Under the premise of labour, it is also possible to obtain other drawings based on these drawings.
Electric power management circuit functional block diagram in Fig. 1 the utility model battery management chip.
The pre- Voltage stabilizing module schematic diagram of electric power management circuit in Fig. 2 the utility model battery management chip.
The linear voltage stabilization module principle figure of electric power management circuit in Fig. 3 the utility model battery management chip.
The bias current generation module schematic diagram of electric power management circuit in Fig. 4 the utility model battery management chip.
The Application Example of electric power management circuit in Fig. 5 the utility model battery management chip.
Specific embodiment
The utility model is made further to illustrate in detail, completely below with reference to examples and drawings.
It is practical new below in conjunction with this to keep the objectives, technical solutions, and advantages of the embodiments of the present invention clearer
Attached drawing in type embodiment, the technical scheme in the utility model embodiment is clearly and completely described, it is clear that is retouched
The embodiment stated is the utility model a part of the embodiment, instead of all the embodiments.Usually here in attached drawing description and
The component of the utility model embodiment shown can be arranged and be designed with a variety of different configurations.Therefore, below to attached
The detailed description of the embodiments of the present invention provided in figure is not intended to limit the range of claimed invention,
But it is merely representative of the selected embodiment of the utility model.Based on the embodiments of the present invention, ordinary skill people
Member's every other embodiment obtained without creative efforts, belongs to the model of the utility model protection
It encloses.
Below by several specific embodiments to the power management electricity in battery management chip provided by the utility model
Road elaborates.
The utility model is for having for cell tube in battery management chip (BMIC Battery Management IC)
It manages other circuit modules in chip and voltage, electric current and the function of protection is provided.It can be provided for modules such as analog circuits in chip
Supply voltage provides current offset for other modules.Meanwhile the utility model is also equipped with the function of overcurrent protection, overheat protector.
As shown in the electric power management circuit functional block diagram in Fig. 1 the utility model battery management chip, battery management chip
In electric power management circuit include pre- Voltage stabilizing module 11, linear voltage stabilization module 12 and bias current generation module 13.Input voltage
(input voltage VPP here is the voltage of series-connected cell group, up to 80V or higher voltage) and pass through pre- Voltage stabilizing module
11, linear voltage stabilization module 12 and bias current generation module 13 generate pre- voltage of voltage regulation VPR, voltage of voltage regulation VREG and biasing respectively
Electric current Ibias.That is: input voltage generates pre- voltage of voltage regulation VPR after pre- Voltage stabilizing module 11；Pre- voltage of voltage regulation VPR is linear steady
Die block 12 generates voltage of voltage regulation VREG；Voltage of voltage regulation VREG generates bias current Ibias through bias current generation module 13.
The effect of pre- Voltage stabilizing module 11 is to carry out pre- pressure stabilizing to input voltage, obtains a relatively low voltage VPR；
Linear voltage stabilization module 12 includes band-gap reference module, converts pre- voltage of voltage regulation VPR to the pressure stabilizing of low-temperature coefficient
Voltage VREG；
It should be understood that voltage of voltage regulation VREG here also makees other than being supplied to bias current generation module 13
Voltage is provided to other circuit modules in battery management chip for supply voltage, the modules such as analog circuit provide for example, in chip
Supply voltage.
Bias current generation module 13 converts voltage of voltage regulation VREG to the bias current Ibias of low-temperature coefficient.
Bias current Ibias provides current offset to other circuit modules in battery management chip.
Explanation is introduced to modules below:
Pre- Voltage stabilizing module 11:
As shown in the pre- Voltage stabilizing module schematic diagram of the electric power management circuit in Fig. 2 the utility model battery management chip: pre-
Voltage stabilizing module 11 includes pre- pressure stabilizing starting module 111 and pre- pressure stabilizing nucleus module 112.
Pre- pressure stabilizing starting module 111 generates starting bias current for carrying out circuit start after circuit start；
Pre- pressure stabilizing nucleus module 112 is for generating pre- voltage of voltage regulation VPR；It is by that will start bias current through current mirror
Pre- voltage of voltage regulation VPR is generated by zener diode and resistance after mirror image.
It is specific:
Pre- pressure stabilizing starting module 111 includes resistance R1, R2, NMOS transistor MN1, MN2；A termination input electricity of resistance R1
Press VPP, the drain electrode of the grid and MN2 of another termination MN1 of resistance R1；The source level ground connection of MN2, MN2 grid connecting resistance R2
The source electrode of one end and MN1；The other end of resistance R2 is grounded；The drain electrode of MN1 is connected as the output end of pre- pressure stabilizing starting module 111
Pre- pressure stabilizing nucleus module 112, output starting bias current Ib.
When circuit start, the grid voltage of MN1 is gradually risen, and MN1 conducting, under the action of resistance R2, MN2 is also led
It is logical.After circuit powers on stabilization, electric current Ist are as follows:
Illustrate: electric current Ist here is the electric current for flowing through resistance R1.
The size of electric current Ist is directly related with input voltage, special: a megaohm of rank is selected in the circuit of design
Resistance R1 can significantly reduce electric current Ist.
That is: in order to reduce the initial current (electric current Ist) in start-up circuit, the resistance by the way that mega-ohms are arranged is realized, tool
Body is that the resistance of mega-ohms is series in the power supply of pre- pressure stabilizing starting module and the access on ground.Initial current (electric current Ist) reduces
Mean that the power consumption of pre- pressure stabilizing starting module significantly reduces.
As input voltage is increased to 80V from 0V, Ist only increases 4uA.And start bias current Ib can be by the grid source of MN2
Voltage Vgs2 and R2 are calculated, and in circuit set Ib to realize lower power consumption for Vgs2/R2 (Ib=Vgs2/R2)
For 200nA.
Pre- pressure stabilizing nucleus module 112:
Including PMOS transistor MP1-MP6；NMOS transistor MN3-MN5；MP1, MP2, MP3, MP4 constitute cascade
For current-mirror structure, it can be achieved that more accurate current-mirror function, MN3 to MN6 is similarly common-source common-gate current mirror structure, MP5 and
MP6 forms common current mirror.A series of image current IPR that starting bias current Ib is finally obtained through current mirrors, and by steady
Pressure diode D1 and resistance R3 converts electrical current into pre- voltage of voltage regulation VPR.
The drain electrode of grid, MP2 of MP2 is connected with the grid of MP4, while connecting the output of pre- pressure stabilizing starting module 111
End, input starting bias current Ib；The drain electrode of the source electrode of MP2, the grid of MP1, MP1 is connected with the grid of MP3；The source of MP1
The source level of grade and MP3 meet input voltage VPP；The drain electrode of MP3 is connected with the source electrode of MP4；
The drain electrode of grid, MN3 of MN3 is connected with the grid of MN5, while connecting the drain electrode of MP4, and as first node
Output voltage Vb1；The drain electrode of the source electrode of MN3, the grid of MN4, MN4 is connected with the grid of MN6, and exports as second node
Voltage Vb2；The source level of MN4 and the source level ground connection of MN6；The drain electrode of MN6 is connected with the source electrode of MN5；
The drain electrode of grid, MP5 of MP5 is connected with the grid of MP6, while connecting the drain electrode of MN5；The drain electrode of MP6 connects
One end of zener diode D1 exports pre- voltage of voltage regulation VPR as output end；The one of the other end connection resistance R3 of diode D1
End；The other end of resistance R3 is grounded.
It can be obtained by Fig. 2:
VPR=VD1+a·IbR3
Wherein a is the mirroring ratios coefficient of current mirror, IPR=aIb.
Linear voltage stabilization module 12:
As shown in the linear voltage stabilization module principle figure of the electric power management circuit in Fig. 3 the utility model battery management chip:
Linear voltage stabilization module 12 includes circuit for starting up band gap basis 121, band-gap reference circuit 122 and voltage of voltage regulation generation module 123.
Circuit for starting up band gap basis 121 is for starting band-gap reference circuit 122；
Band-gap reference circuit 122 is for generating bandgap voltage reference VBGR；
Bandgap voltage reference VBGR is generated pressure stabilizing electricity by electric resistance partial pressure and voltage amplification by voltage of voltage regulation generation module 123
Press VREG.
Its main working process are as follows: after circuit for starting up band gap basis 121 starts power up, band-gap reference circuit 122 is opened
Beginning work, circuit for starting up band gap basis 121 is closed after powering on；The band gap voltage VBGR of band-gap reference circuit 122 passes through steady
Piezoelectricity presses generation module 123 to generate voltage of voltage regulation VREG.
Further in order to preferably detect the electric power management circuit working condition in the utility model battery management chip,
It further include overcurrent protection module 124.Overcurrent protection module 124 is for detecting whether load current is more than preset limit.
Pre- voltage of voltage regulation VPR generates the power supply of linear voltage stabilization module by NMOS transistor MN9 in linear voltage stabilization module 12
Voltage VAPR；Pre- voltage of voltage regulation VPR connects the grid of MN9；Input voltage VPP connects the drain of MN9；The source electrode of MN9 connects supply voltage
VAPR；
Circuit for starting up band gap basis 121 includes PMOS transistor MP8, MP11；NMOS transistor MN7, MN8；The source level of MP8
The grid for meeting supply voltage VAPR, MP8 connects the source level of node B1 and MP11, the drain electrode of MP8 connect MP11 grid and MN7 leakage
Pole；The drain electrode of MP11 meets bandgap voltage reference VBGR；The source level that the grid of MN7 meets first node Vb1, MN7 connects the drain electrode of MN8；
The grid of MN8 connects the source level ground connection of second node Vb2, MN8.
Band-gap reference circuit 122 includes PMOS transistor MP9, MP10；NPN triode Q1, Q2；Resistance R6, R7；MP9 and
MP10 forms current mirror；The source level of MP9 and the source level of MP10 meet supply voltage VAPR；The drain electrode of the grid and MP9 of MP9, MP10
Grid and Q1 collector be connected to node B1；The drain electrode of MP10 and Q2 collector are connected to node B2；The base stage of Q1 and Q2's
Base stage meets bandgap voltage reference VBGR；The emitter of Q1 is connected to VPTAT by the emitter of R6 and Q2；A termination of R7
The other end of VPTAT, R7 are grounded.
Voltage of voltage regulation generation module 123 includes PMOS transistor MP13；NMOS transistor MN10, MN11, MN12；NPN tri-
Pole pipe Q3, Q4；Resistance R4, R5, RL；Potentiometer RT, capacitor CL；The drain electrode of the grid, MP13 of MP13 meets node B3；The source of MP13
Grade meets input voltage VPP；The source electrode that the drain electrode that the grid of MN11 meets pre- voltage of voltage regulation VPR, MN11 meets node B3, MN11 connects Q3's
Collector；The source electrode that the drain electrode that the grid of MN12 meets pre- voltage of voltage regulation VPR, MN12 meets input voltage VPP, MN12 connects the current collection of Q4
Pole；The electric current that the collector of Q3 flows through is IOC；The grid that the drain electrode of MN10 meets supply voltage VAPR, MN10 meets node B2, MN10
Source level meet node A；One end of another termination potentiometer RT of terminated nodes A, R4 of R4；The other end of potentiometer RT passes through
R5 ground connection, potentiometer RT adjusting terminal strip gap reference voltage VBGR；The base stage of Q3 and Q4 connects the emitter of node A, Q3 and Q4
Export voltage of voltage regulation VREG；The other end ground connection of termination voltage of voltage regulation VREG, RL and CL of RL and CL.
Overcurrent protection module 124 includes PMOS transistor MP12；NPN triode Q5-Q7；Resistance R8, zener diode D4；
The drain electrode that the grid that the source level of MP12 meets input voltage VPP, MP12 meets node B3, MP12 meets node B；Q5 and Q6 forms electric current
Mirror, the collector of Q5 meet node B2；The base stage of Q5, the base stage of Q6, Q6 collector connect one end of D4；Another terminated nodes of D4
B；The emitter of Q5 and the emitter ground connection of Q6；The other end of terminated nodes B, R8 of R8 and the collector of Q6 and base stage phase
Even；The emitter of Q7 is grounded.
Pre- voltage of voltage regulation VPR driving MN9 generates the supply voltage VAPR of linear voltage stabilization module.MP8 and MP11 are as band gap
The start-up circuit of benchmark, raises VBGR when powering on, and MP11 is closed after the completion of powering on.Q1, Q2, MP9, MP10, R6 and R7
Collectively constitute band-gap reference circuit.Q1 and Q2 is bipolar junction transistor, includes the band gap of silicon in base emitter voltage VBE
Voltage generates positive temperature coefficient electricity by the difference DELTA VBE of Q1 and Q2 base emitter voltage at resistance R1 and R2 intermediate node
VPTAT, the linear term in the negative temperature coefficient in VBE to compensate Q1 are pressed, obtained VBGR is
Wherein, k is Boltzmann constant, and q is the quantity of electric charge, and N is Q1 and Q2 emitter junction area ratio.
VBGR is connected to potentiometer RT (that is: resistance pressure-dividing network), together with power MOS pipe MN10 and band-gap reference in A point
Realize pressure stabilizing.The further pressure stabilizing of cascode structure being made up of later MN11, MN12, Q3, Q4, significantly improves output
The supply-voltage rejection ratio (PSRR) of voltage.Voltage of voltage regulation VREG:
VREG=xVBGR-VBE3
Wherein resistance pressure-dividing network proportionality coefficient x is determined by resistance R4, R5, RT.
Compensating electric capacity CL and C0 (mono- terminated nodes B2 of C0, other end ground connection) are respectively used to circuit dominant pole and time main pole
Point compensates, and to ensure that circuit all has reliable phase margin under unloaded and full load conditions, ensure that loop stability.
RT is that one 4 resistance trims circuit, for avoiding technique change or mismatch from impacting the output voltage size of circuit.
Resistance pressure-dividing network proportionality coefficient x can be changed by adjusting RT, to change voltage of voltage regulation VREG size to meet application requirement.
Current foldback circuit detects whether load current is more than pre- limit using the branch current IOC in load current
System, is connected to B point by MP12 and MP13 mirror image.When electric current is excessively high, the raising of B point voltage causes Q5, Q6 to be connected, thus will
Circuit shutdown.The threshold value of overcurrent protection can be arranged by adjusting resistance R8.
Bias current generation module 13:
Such as the bias current generation module schematic diagram institute of the electric power management circuit in Fig. 4 the utility model battery management chip
Show, bias current generation module 13 includes ICTAT generation circuit 131, IPTAT generation circuit 132 and reference current generation module
133。
Illustrate: PTAT (proportional to absolute temperature and absolute temperature is proportional) CTAT
(complementary to absolute temperature current and absolute temperature are inversely proportional)
ICTAT generation circuit 131 is used to generate the electric current ICTAT being inversely proportional with absolute temperature；
IPTAT generation circuit 132 is used for and the electric current IPTAT that absolute temperature is proportional；
ICTAT and IPTAT is combined by proper ratio and is generated bias current Ibias by reference current generation module 133.
Further in order to preferably detect the electric power management circuit working condition in the utility model battery management chip,
It further include overheat protector module 134.Overcurrent protection module 134 is used to detect the temperature of the electric power management circuit in battery management chip
Whether degree is more than limitation.
ICTAT generation circuit 131 includes PMOS transistor MP31；NPN triode Q35；Resistance R32；The source level of MP31 connects
The drain electrode that the drain electrode of the grid and MP31 of voltage of voltage regulation VREG, MP31 meets node C1, MP31 connects the collector of Q35；The leakage of MP31
The electric current of pole is ICTAT；The emitter that the base stage of Q35 meets node C2, Q35 is grounded by R32.
IPTAT generation circuit 132 includes PMOS transistor MP32-MP34；NMOS transistor MN31, MN32；NPN triode
Q31-Q34,Q36；Resistance R31.
MP32, MP33 and MP34 form current mirror, Q33 and Q34 composition current mirror, MN31 and MN32 and form current mirror；
The grid of MP32, the grid of MP33, the drain electrode of MP33 and pole MP34 grid be connected to node C3；The source of MP32
The source level of grade, the source level of MP33 and MP34 meets voltage of voltage regulation VREG；The drain electrode of the drain of MP32 and MN32, MN32 grid,
The grid of MN31 is connected；The source electrode of MN32 and the source electrode ground connection of MN31；The drain electrode of MN31 connects the emitter of Q36；The base stage of Q36 connects
The collector of node C3, Q36 meet voltage of voltage regulation VREG；The collector of Q33 meets node C3；The base stage of Q33, the base stage of Q34 and Q34
Collector meet node C2；The emitter of the base stage of Q31, the collector of Q32 and Q34 is connected in node B；The base stage of Q32, Q31
Collector and the emitter of Q33 be connected in node A；The emitter of Q31 is grounded by R31；The emitter of Q32 is grounded.
Reference current generation module 133 includes PMOS transistor MP37, MP38；The grid of MP37 connects node C3, MP38's
Grid meets node C1；The source level of MP37 and the source level of MP38 meet voltage of voltage regulation VREG；The drain of MP37 is connected with the drain of MP38
Output bias current Ibias together.
Overheat protector module 134 includes PMOS transistor MP35, MP36；NMOS transistor MN33,；NPN triode Q37；
Resistance R33, R34；Logic circuit T31.
The grid of MP35 and the grid of MP36 meet node C3；The source electrode of MP35 and the source electrode of MP36 meet voltage of voltage regulation VREG；
The drain electrode of MP35 connects the base stage of Q37 and one end of R33；One end of another termination R34 of R33 and the drain electrode of MN33；R34's is another
The source electrode of end and MN33 are grounded；The collector of Q37 connects the drain electrode of MP36 and the input of T31；The emitter of Q37 is grounded；T31's is defeated
It is out logical signal VOTP；The state of logical signal VOTP show the electric power management circuit in battery management chip temperature whether
More than limitation.
Bias current generation module 13 is powered by the voltage of voltage regulation VREG that linear voltage stabilization module 12 generates, and can be generated to temperature
Change insensitive current offset.The size of transistor MP33 and MP34 is identical, under the action of MP33, MP34, Q33, Q34,
A, B two o'clock voltage are equal in figure, then obtain positive temperature coefficient electric current by R31.Due to depositing for bipolar junction transistor base current
The electric current for flowing through Q31 and Q32 is not fully equal.Here collocation structure MP32, MN32, MN31, Q36 are introduced, mirror image is passed through
Electric current IPTAT and the base current for utilizing Q36 compensate the base current of mono- tunnel Q33 outflow, finally obtained positive temperature
Coefficient current are as follows:
Wherein Ie is the electric current for flowing through Q31, and r is current mirror ratio coefficient, and β is the electric current of bipolar junction transistor Q36
Gain coefficient.Negative temperature parameter current ICTAT is generated by Q35 and R32, the IPTAT for later being obtained mirror image by MP37, M3P8
It is combined with ICTAT in suitable ratio, obtains the electric current Ibias insensitive to temperature change.
Thermal-shutdown circuit utilizes the characteristic of positive temperature coefficient electric current, is made of MP35, MP36, Q37, R33, R34.Work as temperature
When degree increases, IPTAT increases, and the electric current that mirror image obtains increases the base voltage of Q7 under the action of R33 and R34.Work as temperature
When degree is more than limitation, Q37 conducting, then VOPT signal becomes high level from low level, which is sent to digital module in chip,
Chip power is closed.
The utility model is for that in the electric power management circuit battery management chip in battery management chip, can be in chip
The modules such as analog circuit provide supply voltage, provide current offset for other modules.Here, power supply electricity is provided for chip internal module
Pressure either voltage of voltage regulation VREG, is also possible to pre- voltage of voltage regulation VPR.Meanwhile the utility model be also equipped with overcurrent protection,
The function of overheat protector.As shown in the Application Example of the electric power management circuit in Fig. 5 the utility model battery management chip, this
Electric power management circuit in utility model battery management chip is more to the analog- and digital- module analog-digital converter in chip, high pressure
Path multiplexer, digital filter, logic circuit control circuit (register and controller), communication bus provide voltage or electric current.
Here battery management chip is used to monitor the voltage and current of each battery unit in multi-section lithium ion battery, to calculate electricity
The state-of-charge of pool unit, and each battery unit is carried out balanced.Particular by high voltage multiplexers monitoring more piece lithium from
The voltage and current of each battery unit in sub- battery.
Compared with prior art, the utility model has the advantages that:
1, circuit can produce stable voltage under conditions of high input voltage, to for each module in power management IC
Stable power supply is provided.Output voltage varies less under the wide variation of input voltage.
Especially the variation of 8~80V of input voltage when, output voltage only changes 9.4mV.
2, outputting current steadily, driving capability are big.
3, the electric power management circuit in battery management chip is low in energy consumption, facilitates the overall power for controlling chip.The circuit
There is extremely low power consumption at room temperature, facilitate the overall power for controlling power management IC, emulation obtains the current drain of circuit
In the range of 6.01 μ A to 15.78 μ A.
4, circuit structure is easily achieved, and is suitble to engineer application.
The above descriptions are merely preferred embodiments of the present invention, is not intended to limit the utility model, for this
For the technical staff in field, various modifications and changes may be made to the present invention.It is all in the spirit and principles of the utility model
Within, any modification, equivalent replacement, improvement and so on should be included within the scope of protection of this utility model.
In the description of the present invention, it should be understood that term " center ", " longitudinal direction ", " transverse direction ", " length ", " width
Degree ", " thickness ", " go up ", " under ", " preceding ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " bottom " " interior ", " outside ", " is suitable
Hour hands ", " " orientation or positional relationship of equal instructions is to be based on the orientation or positional relationship shown in the drawings, merely to just counterclockwise
In description the utility model and simplify description, rather than the equipment of indication or suggestion meaning or element there must be specific side
Position is constructed and operated in a specific orientation, therefore should not be understood as limiting the present invention.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more of the features." multiple " are meant that two or two in the description of the present invention,
More than, unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connection ", " is consolidated at " connected "
It is fixed " to wait terms shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or is integral；It can be
Mechanical connection, is also possible to be electrically connected；It can be directly connected, two can also be can be indirectly connected through an intermediary
The interaction relationship of connection or two elements inside element.It for the ordinary skill in the art, can basis
Concrete condition understands the concrete meaning of above-mentioned term in the present invention.
In the present invention unless specifically defined or limited otherwise, fisrt feature second feature its " upper " or it "
Under " may include that the first and second features directly contact, also may include the first and second features be not direct contact but logical
Cross the other characterisation contact between them.Moreover, fisrt feature second feature " on ", " top " and " above " be including the
One feature is right above second feature and oblique upper, or is merely representative of first feature horizontal height higher than second feature.First is special
Sign second feature " under ", " lower section " with " below " be directly below and diagonally below the second feature including fisrt feature, or only
Indicate that first feature horizontal height is less than second feature.
Claims (10)
1. the electric power management circuit in a kind of battery management chip, comprising:
Pre- Voltage stabilizing module,
Linear voltage stabilization module
With
Bias current generation module；
Input voltage successively generates pre- pressure stabilizing electricity by pre- Voltage stabilizing module, linear voltage stabilization module and bias current generation module respectively
Press VPR, voltage of voltage regulation VREG and bias current Ibias；
Pre- Voltage stabilizing module carries out pre- pressure stabilizing to input voltage VPP, obtains a relatively low voltage VPR；
Linear voltage stabilization module obtains the voltage of voltage regulation VREG of low-temperature coefficient by pre- voltage of voltage regulation VPR；
Bias current generation module converts voltage of voltage regulation VREG to the bias current Ibias of low-temperature coefficient；
The pre- Voltage stabilizing module includes pre- pressure stabilizing starting module and pre- pressure stabilizing nucleus module；
Pre- pressure stabilizing starting module carries out circuit start, and starting bias current is generated after circuit start；
Mega-ohms resistance is provided in pre- pressure stabilizing starting module；The resistance of the mega-ohms is series at pre- pressure stabilizing starting module
In the access on power supply and ground；
Pre- pressure stabilizing nucleus module generates pre- voltage of voltage regulation VPR；Pass through pressure stabilizing after current mirror mirror by the way that bias current will be started
Diode and resistance generate pre- voltage of voltage regulation VPR.
2. the electric power management circuit in battery management chip as described in claim 1, it is characterised in that:
The linear voltage stabilization module includes circuit for starting up band gap basis, band-gap reference circuit and voltage of voltage regulation generation module；
Circuit for starting up band gap basis starts band-gap reference circuit；
Band-gap reference circuit generates bandgap voltage reference VBGR；
Bandgap voltage reference VBGR is generated voltage of voltage regulation VREG by electric resistance partial pressure and voltage amplification by voltage of voltage regulation generation module.
3. the electric power management circuit in battery management chip as described in claim 1, it is characterised in that:
The bias current generation module includes ICTAT generation circuit, IPTAT generation circuit and reference current generation module；
ICTAT generation circuit generates the electric current ICTAT being inversely proportional with absolute temperature；
The electric current IPTAT that IPTAT generation circuit generates and absolute temperature is proportional；
Reference current generation module is by ICTAT and IPTAT by proper ratio in conjunction with the generation bias current Ibias.
4. the electric power management circuit in battery management chip as described in claim 1, it is characterised in that:
The pre- pressure stabilizing starting module includes resistance R1, R2, NMOS transistor MN1, MN2；
A termination input voltage VPP of resistance R1, the drain electrode of the grid and MN2 of another termination MN1 of resistance R1；The source level of MN2
It is grounded, the source electrode of one end of the grid connecting resistance R2 of MN2 and MN1；The other end of resistance R2 is grounded；The drain electrode of MN1 is as pre- steady
The output end of starting module 111 is pressed to connect pre- pressure stabilizing nucleus module 112, output starting bias current Ib.
5. the electric power management circuit in battery management chip as described in claim 1, it is characterised in that:
The pre- pressure stabilizing nucleus module includes PMOS transistor MP1-MP6；NMOS transistor MN3-MN5；Zener diode D1 and
Resistance R3；
The drain electrode of grid, MP2 of MP2 is connected with the grid of MP4, while connecting the output end of pre- pressure stabilizing starting module 111, defeated
Enter to start bias current Ib；The drain electrode of the source electrode of MP2, the grid of MP1, MP1 is connected with the grid of MP3；The source level of MP1 and
The source level of MP3 meets input voltage VPP；The drain electrode of MP3 is connected with the source electrode of MP4；
The drain electrode of grid, MN3 of MN3 is connected with the grid of MN5, while connecting the drain electrode of MP4, and exports as first node
Voltage Vb1；The drain electrode of the source electrode of MN3, the grid of MN4, MN4 is connected with the grid of MN6, and as second node output voltage
Vb2；The source level of MN4 and the source level ground connection of MN6；The drain electrode of MN6 is connected with the source electrode of MN5；
The drain electrode of grid, MP5 of MP5 is connected with the grid of MP6, while connecting the drain electrode of MN5；The drain electrode of MP6 connects pressure stabilizing
One end of diode D1 exports pre- voltage of voltage regulation VPR as output end；One end of the other end connection resistance R3 of diode D1；Electricity
Hinder the other end ground connection of R3.
6. the electric power management circuit in battery management chip as claimed in claim 2, it is characterised in that:
Pre- voltage of voltage regulation VPR generates the power supply electricity of linear voltage stabilization module by NMOS transistor MN9 in the linear voltage stabilization module
Press VAPR；Pre- voltage of voltage regulation VPR connects the grid of MN9；Input voltage VPP connects the drain of MN9；The source electrode of MN9 connects supply voltage
VAPR。
7. the electric power management circuit in battery management chip as claimed in claim 6, it is characterised in that:
The circuit for starting up band gap basis includes PMOS transistor MP8, MP11；NMOS transistor MN7, MN8；
The grid that the source level of MP8 meets supply voltage VAPR, MP8 connects the source level of node B1 and MP11, the drain electrode of MP8 connects the grid of MP11
The drain electrode of pole and MN7；The drain electrode of MP11 meets bandgap voltage reference VBGR；The source level that the grid of MN7 meets first node Vb1, MN7 connects
The drain electrode of MN8；The grid of MN8 connects the source level ground connection of second node Vb2, MN8.
8. the electric power management circuit in battery management chip as claimed in claim 6, it is characterised in that:
The band-gap reference circuit includes PMOS transistor MP9, MP10；NPN triode Q1, Q2；Resistance R6, R7；
MP9 and MP10 forms current mirror；The source level of MP9 and the source level of MP10 meet supply voltage VAPR；The grid of MP9 and MP9's
Drain electrode, the grid of MP10 and Q1 collector are connected to node B1；The drain electrode of MP10 and Q2 collector are connected to node B2；The base of Q1
The base stage of pole and Q2 meet bandgap voltage reference VBGR；The emitter of Q1 is connected to VPTAT by the emitter of R6 and Q2；The one of R7
Terminate the other end ground connection of VPTAT, R7.
9. the electric power management circuit in battery management chip as claimed in claim 6, it is characterised in that:
The voltage of voltage regulation generation module includes PMOS transistor MP13；NMOS transistor MN10, MN11, MN12；NPN triode
Q3,Q4；Resistance R4, R5, RL；Potentiometer RT, capacitor CL；
The drain electrode of the grid, MP13 of MP13 meets node B3；The source level of MP13 meets input voltage VPP；The grid of MN11 connects pre- pressure stabilizing
The source electrode that the drain electrode of voltage VPR, MN11 meet node B3, MN11 connects the collector of Q3；The grid of MN12 connect pre- voltage of voltage regulation VPR,
The source electrode that the drain electrode of MN12 meets input voltage VPP, MN12 connects the collector of Q4；The electric current that the collector of Q3 flows through is IOC；MN10
Drain electrode connect the grid of supply voltage VAPR, MN10 and connect the source level of node B2, MN10 and meet node A；Terminated nodes A, R4 of R4
Another termination potentiometer RT one end；The other end of potentiometer RT passes through R5 ground connection, the adjusting terminal strip gap base of potentiometer RT
Quasi- voltage VBGR；The base stage of Q3 and Q4 meets the emitter output voltage of voltage regulation VREG of node A, Q3 and Q4；A termination of RL and CL
The other end of voltage of voltage regulation VREG, RL and CL are grounded.
10. the electric power management circuit in battery management chip as claimed in claim 3, it is characterised in that:
The ICTAT generation circuit includes PMOS transistor MP31；NPN triode Q35；Resistance R32；
The drain electrode that the drain electrode that the source level of MP31 connects the grid and MP31 of voltage of voltage regulation VREG, MP31 meets node C1, MP31 connects Q35's
Collector；The electric current of the drain electrode of MP31 is ICTAT；The emitter that the base stage of Q35 meets node C2, Q35 is grounded by R32.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821849359.6U CN208752489U (en) | 2018-11-08 | 2018-11-08 | A kind of electric power management circuit in battery management chip |
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| CN201821849359.6U CN208752489U (en) | 2018-11-08 | 2018-11-08 | A kind of electric power management circuit in battery management chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113659973A (en) * | 2021-07-16 | 2021-11-16 | 西安电子科技大学芜湖研究院 | High-voltage multiplexer of driving circuit and battery monitoring switch |
| CN114253337A (en) * | 2021-12-08 | 2022-03-29 | 电子科技大学 | Band-gap reference circuit integrating over-temperature protection and resistance trimming protection functions |
| CN116048167A (en) * | 2021-12-17 | 2023-05-02 | 成都海光微电子技术有限公司 | Self-adaptive starting power supply circuit, integrated circuit and self-adaptive starting circuit |
-
2018
- 2018-11-08 CN CN201821849359.6U patent/CN208752489U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113659973A (en) * | 2021-07-16 | 2021-11-16 | 西安电子科技大学芜湖研究院 | High-voltage multiplexer of driving circuit and battery monitoring switch |
| CN113659973B (en) * | 2021-07-16 | 2023-08-15 | 西安电子科技大学芜湖研究院 | High-voltage multiplexer of drive circuit and battery monitoring switch |
| CN114253337A (en) * | 2021-12-08 | 2022-03-29 | 电子科技大学 | Band-gap reference circuit integrating over-temperature protection and resistance trimming protection functions |
| CN116048167A (en) * | 2021-12-17 | 2023-05-02 | 成都海光微电子技术有限公司 | Self-adaptive starting power supply circuit, integrated circuit and self-adaptive starting circuit |
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