CN106708467A - Width bit accumulator circuit, designing method thereof and programmable logic device - Google Patents
Width bit accumulator circuit, designing method thereof and programmable logic device Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
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Abstract
The invention provides a width bit accumulator circuit, a designing method thereof and a programmable logic device. The width bit accumulator circuit comprises a first input end A, a second input end B, a third input end C, a fourth input end PI, a first output end P0, a first summator, a first branched circuit connected with the first input end A, the second input end B and the third input end C, a second branched circuit connected with the fourth input end PI and a third branched circuit connected with the first output end P0, the first summator operates an output result of the first branched result and an output result of the second branched result and outputs first parallel data through the third branched circuit, and the first branched circuit, the second branched circuit and the third branched circuit are formed by hard core configuration. By implementing the invention, a width bit accumulator can be realized directly through hard core configuration, and an outside register and wire winding are not needed, so that time delay of outputting from the register to a logic operation unit is reduced, and the width bit accumulator is enabled to be better than accumulators realized through soft IP in time sequence performance.
Description
Technical field
The present invention relates to FPGA (Field Programmable Gate Array, PLD) technical field,
More particularly to a kind of bit accumulator circuit wide and its method for designing, PLD.
Background technology
Accumulator, is the special operand and computing knot that can be used to deposit arithmetic or logical operation in arithmetic unit
The register of fruit, can carry out adding, subtract, read, shifting, the operation such as cyclic shift and supplement, be the chief component of arithmetic unit.
Also had a wide range of applications in digital display circuit, be the important operation part in many digital display circuit data paths, especially existed
In high-performance microprocessor, digital signal processor, graphic image system, scientific algorithm and some specific data processing equipments
Even more indispensable part, there is very important status, can usually turn into the bottleneck of systematic function.
At present, DSP (Digital Signal Processor, digital signal processor) is embedded with existing FPGA
Accumulator function, but DSP embedded accumulator is all fixed, in actual applications, if during demand bit accumulator wide, needing
To be realized that this can consume the coiling resource of a large amount of FPGA by the configuration of DSP external resources, simultaneously as DSP outside around
Line length increases, and can increase register to the delay of DSP, so as to can influence to realize the maximum clock frequency of accumulator.
Therefore, those skilled in the art urgently provide a kind of bit accumulator wide, to solve existing bit accumulator needs wide
By the technical problem realized by exterior arrangement resource.
The content of the invention
It is existing to solve the invention provides a kind of bit accumulator circuit wide and its method for designing, PLD
Accumulator needs the technical problem that could be realized by DSP external circuit arrangements resource.
In order to solve the above technical problems, the invention provides a kind of bit accumulator circuit wide, including：First input end A,
Two input B, the 3rd input C, the 4th input PI, the first output end P0, first adder and with described first input
End A, the second input B and the 3rd input C connection tie point and the 4th input PI connection the second branch road,
The 3rd branch road being connected with the first output end P0, the first adder by the output result of the tie point with it is described
The output result of the second branch road carries out computing, and the first parallel data is exported by the 3rd branch road；
The tie point includes multiplier and first selector, the multiplier be used for the first input end A and
The data of the second input B inputs carry out multiplying, obtain the first operational data, and export to the first selector, institute
State the data that first selector is input into according to first choice signal sel0 from first operational data and the 3rd input C
A data output to the first adder is selected in two data；
Second branch road includes second selector, and the second selector is used for according to the second selection signal sel1 from institute
State and select a data output to the first adder at least three data of the 4th input PI inputs；
3rd branch road include the first output register preg1, the input of the first output register preg1 with
The output end connection of the first adder, the output end of the first output register preg1 and the first output end P0
Connection, for exporting the first parallel data.
Further, the bit accumulator circuit wide also includes the 4th branch road, the 4th branch road and first addition
The output end connection of device, the first output cascade data for the first adder to be exported carry out computing, and output second is simultaneously
Row data.
Further, the 4th branch road include third selector, second adder, the second output register preg2 with
And the second output end P1 being connected with the second output register preg2, the third selector is according to the 3rd selection signal
Sel2 selections are exported to the second adder by the first output cascade data by moving to right the M cascade data for obtaining,
The second adder moves to right the M cascade data for obtaining with second output register by what the third selector was exported
The data of preg2 outputs carry out add operation, and export to the second output register preg2.
Further, if at least three data of the 4th input PI inputs include：By the first input cascade data
Move to right the M cascade data for obtaining, the data of the first output register preg1 outputs and first output register
During three data of low M-bit data of the data of preg1 outputs, the second selector is one-out-three selector, the one-out-three
Selector selects one and exports to the first adder according to the second selection signal sel1 from three data.
Further, when the selection signal that the first choice signal sel0 is first operational data, described second
When selection signal sel1 is the selection signal of the data of the first output register preg1 outputs, the first adder will
The data that first operational data is exported with the first output register preg1 carry out add operation, export operation result
To the first output register preg1, the first parallel data is obtained.
Further, when the selection signal that the first choice signal sel0 is first operational data, described second
When selection signal sel1 is the selection signal of the low M-bit data of the data of the first output register preg1 output, described the
The low M-bit data of the data that one adder exports first operational data with the first output register preg1 is carried out
Add operation, output operation result obtains the 3rd parallel data to the first output register preg1.
Further, when the selection signal that the first choice signal sel0 is first operational data, described second
Selection signal sel1 is the selection signal of the low M-bit data of the data of the first output register preg1 outputs, the described 3rd
Selection signal sel2 be by the first output cascade data by the selection signal for moving to right M cascade data for obtaining when, institute
State the low M-bit data of the data that first adder exports first operational data with the first output register preg1
Add operation is carried out, the first adder exports the first output cascade data to the third selector according to operation result,
The third selector is connected with the second adder, by by moving to right M the first output cascade data output for obtaining extremely
The second adder, to move to right M the first output cascade data for obtaining defeated with described second by described for the second adder
Going out the data of register preg2 outputs carries out add operation, and output operation result is obtained to the second output register preg2
To the 4th parallel data.
In order to solve the above-mentioned technical problem, it is present invention also offers a kind of PLD including as described above
Bit accumulator circuit wide.
In order to solve the above-mentioned technical problem, present invention also offers a kind of bit accumulator circuit design method wide, the width
Bit accumulator circuit includes tie point, the second branch road, the first output register preg1 and first output register
The first output end P0 and first adder of preg1 connections, it is characterised in that methods described includes：
Multiplier and first selector are set in the tie point, and the multiplier is by first input end A and second
The data of input B inputs carry out the first operational data that multiplying obtains and export to the first selector, described first
Selector is according to first choice signal sel0 from first operational data and two data of data of the 3rd input C inputs
Select a data output to the first adder；
Second selector is set on second branch road, wherein the second selector is one-out-three selector, it is described
Second selector is used to select one at least three data being input into from the 4th input PI according to the second selection signal sel1
Data output is to the first adder, the data that the first adder will be exported according to the first selector and described
The data of two selectors output carry out computing, and the first parallel data is exported by the first output register preg1；
4th branch road, the 4th branch road and the first adder are set in the output end of the first adder
Output end is connected, and the first output cascade data for the first adder to be exported carry out computing, output second and line number
According to.
Further, it is described that the 4th is set between the first adder and the first output register preg1
Road includes：Third selector, second adder, the second output register are set in the output end of the first adder
Preg2 and the second output end P1 being connected with the second output register preg2, the third selector is according to the 3rd choosing
Signal sel2 selections are selected to be added by moving to right the M cascade data for obtaining and exporting to described second by the first output cascade data
Musical instruments used in a Buddhist or Taoist mass, the second adder moves to right the M cascade data for obtaining with the described second output by what the third selector was exported
The data of register preg2 outputs carry out add operation, and export to the second output register preg2, and described second is defeated
Go out register preg2 and export the second parallel data.
The beneficial effects of the invention are as follows：
The invention provides a kind of bit accumulator circuit wide and its method for designing, PLD, directly by matching somebody with somebody
Put and be capable of achieving FPGA coilings resource and register resources that width bit accumulator can be saved outside Digital Logic processing module；Further
, support bit accumulator function wide can be directly configured by stone, save soft IP resources；Further, being configured by stone can
The bit accumulator wide being directly realized by, it is not necessary to by outside register and coiling, reduces register output to logical operation list
Time delay between unit, makes its timing performance be better than the accumulator realized by soft IP.
Brief description of the drawings
The circuit connection diagram of the bit accumulator circuit wide that Fig. 1 is provided for first embodiment of the invention；
The circuit connection signal of the bit accumulator circuit wide of 2 cascaded-outputs that Fig. 2 is provided for first embodiment of the invention
Figure；
Fig. 3 connects for the circuit of the bit accumulator circuit wide of the maximum bit of bit wide 48 of output that first embodiment of the invention is provided
Connect schematic diagram；
Fig. 4 connects for the circuit of the bit accumulator circuit wide of the maximum bit of bit wide 66 of output that first embodiment of the invention is provided
Connect schematic diagram；
The method for designing flow chart of the bit accumulator circuit wide that Fig. 5 is provided for second embodiment of the invention.
Specific embodiment
Scheme proposed by the present invention is described in further detail below by specific embodiment combination accompanying drawing.
First embodiment：
Refer to Fig. 1, the circuit connection diagram of the bit accumulator circuit wide that Fig. 1 is provided for first embodiment of the invention,
As shown in Figure 1, in the present embodiment, the bit accumulator circuit wide that the present invention is provided includes：First input end A, the second input
B, the 3rd input C, the 4th input PI, the first output end P0, first adder adder0 and with the first input end
Second branch road of the tie point and the 4th input PI connections of A, the second input B and the 3rd input C connections,
The 3rd branch road being connected with the first output end P0, wherein, two inputs difference of first adder adder0adder0
Output end with tie point and the second branch road is connected, for the output result of tie point and the second branch road to be carried out at computing
Reason, the first output cascade data are exported according to operation result, and the first adder adder0 will also export it is first defeated
Go out cascade data to export to the 3rd branch road, the first parallel data is exported by the first output end P0.
As shown in figure 1, the tie point includes multiplier multipler and first selector mux0, the multiplier
The output end of multipler is connected with the first input end A and the second input B respectively, and described first is passed through for receiving
The data that input A and the second input B is input into parallel, and two data that will be received carry out multiplying, obtain first
Operational data；Further, the multiplier multipler exports to the first selector first operational data
One of input in mux0, another input of the first selector mux0 is connected with the 3rd input C,
The first operational data that the first selector mux0 is exported according to first choice signal sel0 from the multiplier multipler
And the 3rd input C inputs two data of data in select a data output to the first adder adder0.
Second branch road includes the input and the 4th input of second selector mux1, the second selector mux1
PI is connected, and output end is connected with the input of the first adder adder0, for according to the second selection signal sel1 from institute
State and select a data output to the first adder adder0 at least three data of the 4th input PI inputs.
3rd branch road include the first output register preg1, the input of the first output register preg1 with
The output end connection of the first adder adder0, the output end of the first output register preg1 is defeated with described first
Go out and hold P0 to connect, for exporting the first parallel data.
As shown in Fig. 2 the bit accumulator circuit wide also includes the 4th branch road, the 4th branch road and first addition
The output end connection of device adder0, for the first output cascade data that the first adder adder0 is exported to be transported
Calculate, export the second parallel data.
Specifically, the 4th branch road includes third selector mux2, second adder adder1, the second output register
Preg2 and the second output end P1 being connected with the second output register preg2, wherein, it is preferred that the 3rd selection
Device mux2 uses one-out-three selector, the input of the third selector mux2 to connect with the output end of first adder adder0
Connect, output end is connected with the input of the second adder adder1, the output end of the second adder adder1 and institute
The second output register preg2 connections are stated, the output end of the second output end P1 and the second output register preg2 connects
Connect.
In the present embodiment, when the 3rd selection signal sel2 is the cascade data after selection is moved to right, the 3rd choosing
Select device mux2 and move to right the M level for obtaining for being passed through by the first output cascade data according to the 3rd selection signal sel2 selections
To the second adder adder1, the second adder adder1 exports the third selector mux2 to connection data output
The data that the M cascade data for obtaining export with the second output register preg2 that move to right carry out add operation, and export
To the second output register preg2, the second output register preg2 exports the second parallel data.
In the present embodiment, if at least three data of the 4th input PI inputs include：Cascaded by the first input
Data shift right M the cascade data for obtaining, the data of the first output register preg1 outputs and first output are posted
During three data of low M-bit data of the data of storage preg1 outputs, the second selector mux1 is one-out-three selector, institute
State one-out-three selector and select one from three data according to the second selection signal sel1 and export to the first adder
Adder0, it is preferred that the M is more than or equal to 18 and less than the positive integer of 48 (18≤M ＜ 48).
Further, the 3rd input C and the 4th input PI can be to merge, specifically, it is defeated to work as the described 3rd
When the data for entering to hold C to be input into are all the data of the first output register preg1 outputs, the 3rd input C and the 4th
Input PI can be shared.
As shown in figure 3, be the bit accumulator circuit diagram wide of the maximum bit of bit wide 48 of output, if the first input end
The data of A and the second input B inputs are the data A [17 of 18 bits:0] and B [17:, and the first selector 0]
Mux0, the corresponding selection signals of second selector mux1 are respectively：When the first choice signal sel0 is first computing
The selection signal of data, the second selection signal sel1 is the selection of the data of the first output register preg1 outputs
During signal, the first adder adder0 exports first operational data and the first output register preg1
Data Pr [47:0] add operation is carried out, output operation result obtains first and line number to the first output register preg1
According to P0 [47:0], its corresponding computing formula is：P0[47:0]=Pr [47:0]+A[17:0]*B[17:0].
As shown in figure 4, the schematic diagram of the bit accumulator circuit wide for the maximum bit of bit wide 66 of output, concrete implementation 66 compares
Special output is specific to be realized by 2 outputs of cascade, wherein first data P1 of cascaded-output is 18 bits, the 2nd
The data P2 of individual cascaded-output is 48 bits, and it be just the maximum bit of parallel output 66 that 2 cascaded-outputs are stacked and add up.
When the selection signal that the first choice signal sel0 is first operational data, second selection signal
When sel1 is the selection signal of the low M-bit data of the data of the first output register preg1 outputs, the first adder
The data that adder0 exports first operational data with the first output register preg1 low M-bit data 30'h0,
Pr0[17:0] add operation } is carried out, output operation result obtains the 3rd parallel data to the first output register preg1
P1[17:0], its corresponding computing formula is：P1[17:0]={ 30'h0, Pr0 [17:0]}+A[17:0]*B[17:0].
Further, in the selection signal that the first choice signal sel0 is first operational data, described second
On the basis of selection signal sel1 is the selection signal of the low M-bit data of the data of the first output register preg1 output,
The 3rd selection signal sel2 is to be believed by moving to right the M selection of the cascade data for obtaining by the first output cascade data
Number when, the first adder adder0 according to operation result export the first output cascade data PO[47:0] to the described 3rd choosing
Select device mux2, the third selector mux2 according to the 3rd selection signal first by the first output cascade data shift right 18 after,
Obtain moving to right cascade data PO[47:0]>>>18, and select this to move to right cascade data output PO[47:0]>>>18 to described second
Adder adder1, the second adder adder1 by it is described move to right 18 cascade datas for obtaining with described second output post
The data Pr1 [47 of storage preg2 outputs:0] add operation, output operation result to second output register are carried out
Preg2, obtains the 4th parallel data P2 [65:18]=Pr1 [47:0]+PO[47:0]>>>18。
Corresponding, present invention also offers a kind of PLD, it includes the accumulator wide that the present embodiment is provided
Circuit, tie point, the second branch road, the 3rd branch road, the 4th branch road, multiplier multipler in the accumulator circuit wide,
Selector configures to realize by the stone of the PLD.
The bit accumulator circuit wide that the present embodiment is provided, the bit accumulator wide that can be directly realized by is configured by stone, is not required to
Will be by outside register and coiling, solving existing accumulator needs to be realized by DSP external circuit arrangements resource
Problem, while also reducing register output to the time delay between ALU, make its timing performance better than by soft IP
The accumulator of realization.
Second embodiment：
The flow chart of the bit accumulator circuit design method wide that Fig. 5 is provided for the hungry embodiment of the present invention, refer to Fig. 5,
The bit accumulator circuit wide includes：Tie point, the second branch road, the first output register preg1 and the first output deposit
The first output end P0 and first adder adder0 of device preg1 connections, when the circuit is designed, configure particular by stone
To realize, its configuration design cycle is as follows：
S501, sets multiplier multipler and first selector mux0 in the tie point.
In this step, tie point is configured to by stone and is configured with multiplier multipler and alternative selector,
Two inputs of the multiplier multipler are connected with first input end A, the second input B respectively, for receiving two
The data A [17 of individual input input:0] and B [17:0], and by A [17:0] and B [17:0] multiplying is carried out, is obtained
One operational data is exported to alternative selector, and the alternative selector is according to first choice signal sel0 from the described first fortune
The evidence that counts and the data Pr [47 of the 3rd input C inputs:0] data output to first addition is selected in two data
Device adder0.
S502, sets second selector mux1 on second branch road.
In this step, the second branch road is configured to by stone and configures one-out-three selector, in the one-out-three selector
Input in be input into three data, including data shift right M cascade data for obtaining, described first defeated is cascaded by the first input
Go out the number of low M-bit data three of the data of register preg1 outputs and the data of the first output register preg1 outputs
Selected from three data according to the second selection signal sel1 according to, the one-out-three selector one export to described first plus
Musical instruments used in a Buddhist or Taoist mass adder0.
S503, judges whether the first choice signal sel0 and the second selection signal sel1 meet first condition, if full
Foot, then export the first parallel data.
In this step, the specific first choice signal sel0 and the second selection signal sel1 meets first condition
For：When the selection signal that the first choice signal sel0 is first operational data, the second selection signal sel1 is
During the selection signal of the data of the first output register preg1 output, the first adder adder0 is by described first
The data that operational data is exported with the first output register preg1 carry out add operation, output operation result to described the
One output register preg1, obtains the first parallel data.
In the present embodiment, when it is 48 bit that bit accumulator circuit wide only needs to output maximum data, it is only necessary to pass through
It is to be capable of achieving to perform step S501-S503, and the computing of output multiplier multipler is selected by controlling first selector mux0
As a result, the data of second selector mux1 selection output the first output register preg1 outputs are controlled and, you can realize
One maximum output is the bit accumulator wide of 48 bits, and physical circuit connection is as shown in Figure 3.
But, if the data of output are more than 48 bit, also need in the position wide designed by step S501-S503
On the basis of accumulator circuit, one-level output is further added by, it is specific such as step S504-S507.
S504, sets the 4th branch road in the output end of the first adder adder0.
In this step, the 3rd is set in the output end of the first adder adder0 particular by stone configuration
Selector mux2, second adder adder1, the second output register preg2 and with the second output register preg2
Second output end P1, the third selector mux2 of connection is selected by first output stage according to the 3rd selection signal sel2
Connection data are exported to the second adder adder1, the second adder by moving to right the M cascade data for obtaining
Adder1 moves to right the M cascade data for obtaining with second output register by what the third selector mux2 was exported
The data of preg2 outputs carry out add operation, and export to the second output register preg2.
S505, judges whether the first choice signal sel0 and the second selection signal sel1 meet second condition, if full
Foot, then export the 3rd parallel data.
When the selection signal that the first choice signal sel0 is first operational data, second selection signal
When sel1 is the selection signal of the low M-bit data of the data of the first output register preg1 outputs, the first adder
The low M-bit data of the data that adder0 exports first operational data with the first output register preg1 is added
Method computing, output operation result obtains the 3rd parallel data to the first output register preg1.
S506, on the basis of step S505, the 3rd selection signal sel2 of selection is by the first output cascade data
By moving to right the M selection signal of the cascade data for obtaining.
S507, according to the 3rd selection signal sel2, the 4th branch road first adder adder0 is exported
One output cascade data carry out computing, export the 4th parallel data.
Specifically, second parallel data is realized by 2 outputs of cascade, wherein the 1st number of cascaded-output
It is 18 bits according to P1, the 2nd data P2 of cascaded-output is 48 bits, 2 cascaded-outputs are stacked and add up just as maximum
The bit of parallel output 66.
First, the 1st cascaded-output is by first operational data and described by the first adder adder0
The low M-bit data of the data of one output register preg1 outputs carries out add operation, output operation result to the described first output
Register preg1, obtains the 3rd parallel data.
After the completion of first cascaded-output, continued to output by the 2nd cascaded-output, specifically by the first adder
Adder0 exports the first output cascade data to the third selector mux2 according to operation result, will be obtained by moving to right M
The first output cascade data output to the second adder adder1, the second adder adder1 moves to right M by described
The data that the first output cascade data that position obtains are exported with the second output register preg2 carry out add operation, export
Operation result obtains the 4th parallel data to the second output register preg2.
Exported by the 1st cascade and the 2nd alternating of cascade, it is achieved thereby that highest output digit reaches 66 bits
Parallel data.
In sum, by implementation of the invention, at least there is following beneficial effect：
The invention provides a kind of bit accumulator circuit wide and its method for designing, PLD, directly by hard
FPGA coilings resource and the register money that be capable of achieving width bit accumulator, can not only save outside Digital Logic processing module are put in caryogamy
Source, can also save soft IP resources；Further, the bit accumulator wide that can be directly realized by is configured by stone, it is not necessary to pass through
Outside register and coiling, reduce register output to the time delay between ALU, make its timing performance better than logical
Cross the accumulator that soft IP is realized.
Above content is to combine the further description that specific embodiment is made to the embodiment of the present invention, it is impossible to recognized
Fixed specific implementation of the invention is confined to these explanations.For general technical staff of the technical field of the invention,
Without departing from the inventive concept of the premise, some simple deduction or replace can also be made, the present invention should be all considered as belonging to
Protection domain.
Claims (10)
1. a kind of bit accumulator circuit wide, it is characterised in that including：First input end A, the second input B, the 3rd input C,
4th input PI, the first output end P0, first adder and defeated with the first input end A, the second input B and the 3rd
Enter to hold what the tie point that C is connected and the second branch road that the 4th input PI is connected and the first output end P0 were connected
3rd branch road, the first adder is transported the output result of the tie point with the output result of second branch road
Calculate, the first parallel data is exported by the 3rd branch road；
The tie point includes multiplier and first selector, and the multiplier is used for the first input end A and second
The data of input B inputs carry out multiplying, obtain the first operational data, and export to the first selector, and described the
The data two that one selector is input into according to first choice signal sel0 from first operational data and the 3rd input C
A data output to the first adder is selected in data；
Second branch road includes second selector, and the second selector is used for according to the second selection signal sel1 from described the
A data output to the first adder is selected at least three data of four input PI inputs；
3rd branch road include the first output register preg1, the input of the first output register preg1 with it is described
The output end connection of first adder, the output end of the first output register preg1 is connected with the first output end P0,
For exporting the first parallel data.
2. bit accumulator circuit wide according to claim 1, it is characterised in that also including the 4th branch road, described 4th
Road is connected with the output end of the first adder, and the first output cascade data for the first adder to be exported are carried out
Computing, exports the second parallel data.
3. bit accumulator circuit wide according to claim 2, it is characterised in that the 4th branch road includes the 3rd selection
Device, second adder, the second output register preg2 and the second output being connected with the second output register preg2
End P1, the third selector is selected by the first output cascade data by moving to right M according to the 3rd selection signal sel2
The cascade data for obtaining is exported to the second adder, and the second adder moves to right M by what the third selector was exported
The data that the cascade data that obtains of position export with the second output register preg2 carry out add operation, and output is to described
Second output register preg2.
4. bit accumulator circuit wide according to claim 3, it is characterised in that if the 4th input PI inputs are extremely
Few three data include：M cascade data for obtaining of data shift right, first output register are cascaded by the first input
During three data of low M-bit data of the data of preg1 outputs and the data of the first output register preg1 outputs, institute
Second selector is stated for one-out-three selector, the one-out-three selector is according to the second selection signal sel1 from three data
Selection one is exported to the first adder.
5. bit accumulator circuit wide according to claim 4, it is characterised in that when the first choice signal sel0 is institute
The selection signal of the first operational data is stated, the second selection signal sel1 is the first output register preg1 outputs
During the selection signal of data, the first adder is defeated with the first output register preg1 by first operational data
The data for going out carry out add operation, and output operation result obtains the first parallel data to the first output register preg1.
6. bit accumulator circuit wide according to claim 4, it is characterised in that when the first choice signal sel0 is institute
The selection signal of the first operational data is stated, the second selection signal sel1 is the first output register preg1 outputs
During the selection signal of the low M-bit data of data, the first adder posts first operational data with the described first output
The low M-bit data of the data of storage preg1 outputs carries out add operation, output operation result to first output register
Preg1, obtains the 3rd parallel data.
7. bit accumulator circuit wide according to claim 4, it is characterised in that when the first choice signal sel0 is institute
The selection signal of the first operational data is stated, the second selection signal sel1 is the first output register preg1 outputs
The selection signal of the low M-bit data of data, the 3rd selection signal sel2 is by right by the first output cascade data
During the selection signal of M cascade data for obtaining of shifting, the first adder is defeated with described first by first operational data
Going out the low M-bit data of the data of register preg1 outputs carries out add operation, and the first adder is exported according to operation result
First output cascade data to the third selector, the third selector is connected with the second adder, will be by right
M the first output cascade data output for obtaining is moved to the second adder, the second adder by it is described move to right M must
To the data that are exported with the second output register preg2 of the first output cascade data carry out add operation, export computing
Result obtains the 4th parallel data to the second output register preg2.
8. a kind of PLD, it is characterised in that including：Bit accumulator wide as described in any one of claim 1 to 9
Circuit.
9. a kind of bit accumulator circuit design method wide, the bit accumulator circuit wide includes tie point, the second branch road, first
The first output end P0 and first adder of output register preg1 and the first output register preg1 connections, it is special
Levy and be, methods described includes：
Multiplier and first selector are set in the tie point, and be input into for first input end A and second by the multiplier
The data of end B inputs carry out the first operational data that multiplying obtains and export to the first selector, the first choice
Device is selected according to first choice signal sel0 from first operational data and two data of data of the 3rd input C inputs
One data output is to the first adder；
Second selector is set on second branch road, wherein the second selector is one-out-three selector, described second
Selector is used to select a data at least three data being input into from the 4th input PI according to the second selection signal sel1
Output to the first adder, the data that the first adder will be exported according to the first selector and described second are selected
The data for selecting device output carry out computing, and the first parallel data is exported by the first output register preg1；
4th branch road, the output of the 4th branch road and the first adder are set in the output end of the first adder
End connection, the first output cascade data for the first adder to be exported carry out computing, export the second parallel data.
10. bit accumulator circuit design method wide according to claim 9, it is characterised in that it is described described first plus
The 4th branch road is set between musical instruments used in a Buddhist or Taoist mass and the first output register preg1 to be included：In the output end of the first adder
Third selector, second adder, the second output register preg2 are set and are connected with the second output register preg2
The the second output end P1 for connecing, the third selector is selected by the first output cascade data according to the 3rd selection signal sel2
Exported to the second adder by moving to right the M cascade data for obtaining, the second adder is by the third selector
The data that the M cascade data for obtaining export with the second output register preg2 that move to right of output carry out add operation, and
Export to the second output register preg2, the second output register preg2 exports the second parallel data.
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