CN112667292A - Asynchronous miniflow line controller - Google Patents
Asynchronous miniflow line controller Download PDFInfo
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Abstract
The invention discloses an asynchronous micro-assembly line controller, comprising: an inverter, an exclusive-or gate, a flip-flop FF and a data latch; the input end of the reverser is connected with the output end of the trigger; the input end of the exclusive-OR gate inputs a Fill signal and a Drain signal, the input end of the exclusive-OR gate comprises a first input end and a second input end, the Drain signal is input into the first input end, and the Fill signal is input into the second input end; the output end of the exclusive-OR gate is connected with the clock input end of the trigger; the data input end of the trigger is connected with the data reverse output end of the trigger, and the data output end of the trigger is connected with the input end of the inverter and the next stage of assembly line; the input end of the data latch is used for inputting the output data of the previous stage of assembly line, and the output end of the data latch is connected with the input end of the combinational logic module in the next stage of assembly line; the pulse input end of the data latch is connected with the input end of the exclusive-OR gate for inputting the Fill signal. The invention simplifies the whole structure of the pipeline control circuit and reduces the inversion of the control signal of the data latch.
Description
Technical Field
The invention relates to the field of asynchronous micro-assembly lines, in particular to an asynchronous micro-assembly line controller.
Background
The asynchronous micro-pipeline comprises a plurality of stages of controllers, each stage of controller is a Click unit, the control of a data path is generally realized through handshake signals among the controllers of each stage, and the Click units are used for controlling the data path of the pipeline. However, the circuit structure of the existing Click unit is slightly complex, and the data path register in the existing Click unit is controlled by four signals, so that the number of times of turning over the control signal of the data path register is increased, the data transmission speed is slow, and the data transmission efficiency is low.
Disclosure of Invention
The invention aims to provide an asynchronous micro-pipeline controller to solve the problems that the existing Click unit is low in data transmission speed and low in data transmission efficiency.
In order to achieve the purpose, the invention provides the following scheme:
the invention relates to an asynchronous micro-pipeline controller, which comprises: an inverter INV, an XOR gate XOR, a flip-flop FF and a data latch;
the input end of the inverter INV is connected with the output end of the flip-flop FF;
the input ends of the exclusive-OR gate XOR input a Fill signal and a Drain signal, the input ends of the exclusive-OR gate XOR comprise a first input end and a second input end, the first input end inputs the Drain signal, and the second input end inputs the Fill signal; the output end of the exclusive OR gate XOR is connected with the clock input end of the trigger FF;
the data input end of the flip-flop FF is connected with the data inversion output end of the flip-flop FF
The data output end Q of the flip-flop FF is connected with the input end of the inverter INV and a next-stage production line;
the input end of the data latch is used for inputting the output data of the previous stage of the assembly line, and the output end of the data latch is connected with the input end of the combinational logic module in the next stage of the assembly line; the pulse input end of the data latch is connected with the input end of the exclusive-OR gate XOR input Fill signal; the Fill signal and the Drain signal generate a clock signal through the XOR gate, the clock signal is input to the flip-flop FF, the flip-flop FF is triggered to output a FULL signal, and the FULL signal of the flip-flop FF is input to the inverter INV and the next stage pipeline; the Fill signal is also input to the data latch; and the asynchronous micro-pipeline controller controls the turnover times of the data latch by using the Fill signal and the output data of the previous stage of pipeline.
Optionally, the data output end Q of the flip-flop FF outputs a Full signal.
Optionally, after the Full signal is inverted by the inverter INV, an Empty signal is output.
Optionally, the Empty signal is input to the previous stage pipeline as a response signal of the previous stage pipeline.
Optionally, the Full signal is used as a request signal of the next stage pipeline.
Optionally, when a reset port of the flip-flop FF is 0, the flip-flop FF resets, and a data output Q of the flip-flop FF outputs 0.
Optionally, the test port of the flip-flop FF is used for testing the current working state of the flip-flop FF; the current working state comprises a normal working state and an abnormal working state.
Optionally, the time when the Fill signal is input into the exclusive or gate XOR is earlier than the time when the Drain signal is input into the exclusive or gate XOR.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention discloses an asynchronous micro-pipeline controller, wherein a data latch in the asynchronous micro-pipeline controller is controlled by two signals, and the turnover frequency of a control signal of the data latch is reduced, so that the data transmission speed is improved, and the data transmission efficiency in a data path is improved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic diagram of an asynchronous pipeline controller according to the present invention.
Description of the symbols: an inverter-INV; exclusive or gate-XOR; a flip-flop-FF; data latch-latch; a data output terminal-Q; data reverse output terminal
(ii) a A data input-D; reset port-CLR; test port-SET; the output data-Date out of the upper stage pipeline; the output data-Date in of the data latch.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide an asynchronous micro-pipeline controller to solve the problems that the existing Click unit is low in data transmission speed and low in data transmission efficiency.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a schematic diagram of an asynchronous pipeline controller according to the present invention, and as shown in fig. 1, the asynchronous pipeline controller includes: an inverter INV, an XOR gate XOR, a flip-flop FF and a data latch.
The input end of the inverter INV is connected with the output end of the flip-flop FF.
The input ends of the exclusive-OR gate XOR input a Fill signal and a Drain signal, the input ends of the exclusive-OR gate XOR comprise a first input end and a second input end, the first input end inputs the Drain signal, and the second input end inputs the Fill signal; and the output end of the exclusive OR gate XOR is connected with the clock input end of the flip-flop FF.
The data input end of the flip-flop FF is connected with the data inversion output end of the flip-flop FF
And the data output end Q of the flip-flop FF is connected with the input end of the inverter INV and a next-stage production line.
The input end of the data latch is used for inputting the output data Date out of the previous stage of the assembly line, and the output data Date in of the data latch is input to the input end of the combinational logic module in the next stage of the assembly line; the pulse input end of the data latch is connected with the second input end of the exclusive-OR gate XOR; the Fill signal and the Drain signal generate a clock signal through an exclusive-OR gate (XOR) and are input into the flip-flop FF, the flip-flop FF is triggered to output a FULL signal, and the FULL signal of the flip-flop FF is input into the inverter INV and the next stage pipeline; the Fill signal is also input to the data latch; and controlling the turnover times of the data latch by using the Fill signal and the output data of the previous stage of the pipeline.
As an alternative embodiment, the data output Q of the flip-flop FF outputs a Full signal.
As an alternative, the Empty signal is output after the Full signal is inverted by the inverter INV.
As an alternative, the Empty signal is input to the previous stage pipeline as a response signal of the previous stage pipeline.
In an alternative embodiment, the Full signal is used as the request signal of the next stage pipeline.
As an optional implementation manner, when the reset port of the flip-flop FF is 0, the flip-flop FF is reset, and the data output Q of the flip-flop FF outputs 0.
As an optional embodiment, the test port of the flip-flop FF is used for testing the current operating state of the flip-flop FF; the current working state comprises a normal working state and an abnormal working state.
As an alternative, the time when the Fill signal is input to the exclusive or gate XOR is earlier than the time when the Drain signal is input to the exclusive or gate XOR.
Compared with the existing micro-assembly line controller, the asynchronous micro-assembly line controller has the advantages of simple structure, higher speed and adjustable delay of each stage of the controlled assembly line.
The invention specifically functions as follows, the improved click unit is used as a controller of each stage of the pipeline, and the control of the data path of the pipeline is achieved by two input signals, namely, a Fill signal, a Drain signal, two output signals, namely, a Full signal and an Empty signal. The improved click cell consists of an inverter, an exclusive-or gate and a flip-flop with the output inverted Q tied back to the input. The request signal from the previous stage pipeline and the response signal from the next stage pipeline generate four local clock signals through an exclusive-or gate, the flip-flop output Q is controlled to be turned over through a trigger signal and a reset signal which are realized through a group of rising and falling edges, the output Q of the flip-flop is used as the request signal Full of the next stage, and the inverted Empty is used as the response signal of the previous stage pipeline. For each stage of pipeline control signal, the time of the Fill signal is required to be earlier than the arrival time of the Drain signal so as to satisfy the timing constraint condition.
The asynchronous micro-pipeline controller disclosed by the invention is actually an improved click unit, and compared with the existing click unit, the asynchronous micro-pipeline controller simplifies the overall structure of a pipeline control circuit and reduces the inversion of data path latch control signals.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (8)
1. An asynchronous micro-pipeline controller, comprising: an inverter INV, an XOR gate XOR, a flip-flop FF and a data latch;
the input end of the inverter INV is connected with the output end of the flip-flop FF;
the input ends of the exclusive-OR gate XOR input a Fill signal and a Drain signal, the input ends of the exclusive-OR gate XOR comprise a first input end and a second input end, the first input end inputs the Drain signal, and the second input end inputs the Fill signal; the output end of the exclusive OR gate XOR is connected with the clock input end of the trigger FF;
the data input end of the flip-flop FF is connected with the data inversion output end of the flip-flop FF
The data output end Q of the flip-flop FF is connected with the input end of the inverter INV and a next-stage production line;
the input end of the data latch is used for inputting the output data of the previous stage of the assembly line, and the output end of the data latch is connected with the input end of the combinational logic module in the next stage of the assembly line; the pulse input end of the data latch is connected with the input end of the exclusive-OR gate XOR input Fill signal; the Fill signal and the Drain signal generate a clock signal through the XOR gate, the clock signal is input to the flip-flop FF, the flip-flop FF is triggered to output a FULL signal, and the FULL signal of the flip-flop FF is input to the inverter INV and the next stage pipeline; the Fill signal is also input to the data latch; and the asynchronous micro-pipeline controller controls the turnover times of the data latch by using the Fill signal and the output data of the previous stage of pipeline.
2. The asynchronous pipeline controller of claim 1 wherein the data output Q of the flip-flop FF outputs a Full signal.
3. The asynchronous microflow pipeline controller of claim 2, wherein the Full signal is inverted by the inverter INV and then an Empty signal is output.
4. The asynchronous microflow pipeline controller as claimed in claim 3, wherein said Empty signal is input to said previous stage pipeline as a reply signal to said previous stage pipeline.
5. The asynchronous microflow pipeline controller of claim 4, wherein the Full signal is used as a request signal for the next stage pipeline.
6. The asynchronous pipeline controller of claim 1, wherein when the reset port of the flip-flop FF is 0, the flip-flop FF is reset, and the data output Q of the flip-flop FF outputs 0.
7. The asynchronous micro-pipeline controller of claim 1, wherein a test port of the flip-flop FF is used to test a current operating state of the flip-flop FF; the current working state comprises a normal working state and an abnormal working state.
8. The asynchronous micro-pipeline controller of claim 1, wherein the Fill signal is input to the exclusive or gate XOR at a time earlier than the Drain signal is input to the exclusive or gate XOR.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113407239A (en) * | 2021-06-09 | 2021-09-17 | 中山大学 | Assembly line processor based on asynchronous single track |
| CN113485671A (en) * | 2021-07-06 | 2021-10-08 | 北京中科芯蕊科技有限公司 | Click controller and asynchronous micro-pipeline data flow controller |
| CN113489482A (en) * | 2021-07-06 | 2021-10-08 | 北京中科芯蕊科技有限公司 | Asynchronous micro-pipeline data flow controller based on Mousetrap |
| CN113590200A (en) * | 2021-08-03 | 2021-11-02 | 北京中科芯蕊科技有限公司 | Asynchronous miniflow line controller based on SR latch |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113407239A (en) * | 2021-06-09 | 2021-09-17 | 中山大学 | Assembly line processor based on asynchronous single track |
| CN113407239B (en) * | 2021-06-09 | 2023-06-13 | 中山大学 | Pipeline processor based on asynchronous monorail |
| CN113485671A (en) * | 2021-07-06 | 2021-10-08 | 北京中科芯蕊科技有限公司 | Click controller and asynchronous micro-pipeline data flow controller |
| CN113489482A (en) * | 2021-07-06 | 2021-10-08 | 北京中科芯蕊科技有限公司 | Asynchronous micro-pipeline data flow controller based on Mousetrap |
| CN113489482B (en) * | 2021-07-06 | 2023-10-20 | 北京中科芯蕊科技有限公司 | Asynchronous micro-pipeline data flow controller based on Mouserap |
| CN113485671B (en) * | 2021-07-06 | 2024-01-30 | 北京中科芯蕊科技有限公司 | Click controller and asynchronous micro-pipeline data flow controller |
| CN113590200A (en) * | 2021-08-03 | 2021-11-02 | 北京中科芯蕊科技有限公司 | Asynchronous miniflow line controller based on SR latch |
| CN113590200B (en) * | 2021-08-03 | 2024-01-30 | 北京中科芯蕊科技有限公司 | Asynchronous micro-pipeline controller based on SR latch |
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