CN110673689B - Clock control circuit and method - Google Patents
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- CN110673689B CN110673689B CN201910899411.1A CN201910899411A CN110673689B CN 110673689 B CN110673689 B CN 110673689B CN 201910899411 A CN201910899411 A CN 201910899411A CN 110673689 B CN110673689 B CN 110673689B
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Abstract
The invention disclosesA clock control circuit and method, the clock control circuit comprising: the clock source, a first buffer unit, a first register group, a combinational logic unit, a second buffer unit, K gating clock units, a third buffer unit and T second register groups; the third buffer unit includes a plurality of third buffers for constituting K M-level N-branch structures; the clock source is connected with the K gated clock units sequentially through the first buffer unit, the first register group and the combinational logic unit, and is also connected with the K gated clock units through the second buffer unit; n formed by M-level N-branch structure for each gated clock unitM‑1A branch and NM‑1A second register set; wherein K, M, N, T are positive integers, and T is not more than K multiplied by NM‑1≤T+NM‑1-1, when T is constant, the larger K, the smaller M, the smaller the delay per branch.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a clock control circuit and a clock control method.
Background
With the continuous evolution of integrated circuit technology, high-speed and low-power consumption circuit design becomes more and more mainstream, and particularly in high-speed circuits such as a high-speed IP unit CPU, an artificial intelligence processing unit NPU and the like, high-speed operation frequency is needed during operation, and ultra-low power consumption and energy conservation are needed during standby. The conventional high-speed circuit design needs to insert a gated clock to achieve the purpose of reducing power consumption, in the existing sequential control circuit, the number of registers loaded by the gated clock is large, the delay value is large, imbalance of a sequential path is easily caused, the sequential path is not easy to meet the requirement, the circuit is difficult to converge in the sequential manner, and the high-frequency design cannot be met.
Disclosure of Invention
The invention provides a time sequence control circuit, which aims to solve the problem of time sequence convergence of the conventional time sequence control circuit.
A first aspect of the present invention provides a clock control circuit, including: the clock source, a first buffer unit, a first register group, a combinational logic unit, a second buffer unit, K gating clock units, a third buffer unit and T second register groups; the third buffer unit includes a plurality of third buffers for constituting K M-level N-branch structures; the clock source sequentially passes through the first buffer unit, the first register set and the combinational logic unit and the K gating timeThe clock units are connected with each other and are also connected with the K gating clock units through the second buffer units; n formed by M-level N-branch structure for each gated clock unitM-1A branch and NM-1A second register set; wherein K, M, N, T are positive integers, and T is not more than K multiplied by NM-1≤T+NM-1-1, when T is constant, the larger K, the smaller M, the smaller the delay per branch.
In a preferred embodiment, the clock source is connected to the K gated clock units through the first buffer unit, the first register group, and the combinational logic unit to form a first clock path, and is connected to the K gated clock units through the second buffer unit to form a first sub-path, and is connected to the second register group through the third buffer unit to form a second sub-path, where the second sub-path includes K × N sub-paths formed by the M-level N branch structureM-1A branch, a sum of the first sub-path delay and the second sub-path delay being equal to the delay of the first clock path.
In a preferred embodiment, the first buffer unit includes a plurality of first buffers connected in series in sequence, the first buffer at the start end is connected to the clock source, the first buffer at the end is connected to the clock end of the first register set, and the output end of the first register set is connected to the K gated clock units through the combinational logic unit.
In a preferred embodiment, the second buffer unit includes a plurality of second buffers connected in series in sequence, the second buffer at the start end is connected to the clock source, and the second buffer at the end is connected to the K gated clock units.
In a preferred embodiment, the enable terminal of each gated clock unit is connected to the combinational logic unit, the clock terminal of each gated clock unit is connected to the second buffer at the end, and the output terminal of each gated clock unit is connected to N through an N-level N-branch structureM-1A branch and the NM-1A second register set is connected.
In a preferred embodiment, in the K M-level N-branch structures, one end of each third buffer of the first level is connected to an output end of a corresponding clock gating unit, and the other end of each third buffer of the first level is divided into N paths and connected to one end of N third buffers of the second level; the other end of each third buffer of the second stage is divided into N paths and connected with one end of N third buffers of the third stage; and so on until K × N of the Mth stageM-1Third buffers are connected to the T second register groups.
A first aspect of the present invention provides a clock control method, including:
amplifying and logically operating an original clock signal, and outputting a control signal to K gate control clock units;
amplifying the original clock signal and outputting a first clock control signal to the K gate control clock units; and
the K gated clock units are connected with T second register groups, and each gated clock unit is formed by an N-level N branch structureM-1Each branch outputting a second clock control signal to NM-1A second register set, wherein K, M, N, T are positive integers, and T is not more than K × NM-1≤T+NM-1-1, when T is constant, the larger K, the smaller M, the smaller the delay per branch.
In a preferred embodiment, the original clock signal outputs the control signal via a first clock path; and the original clock signal outputs the first clock control signal through a first sub-path and outputs the second clock control signal through a second sub-path, and the K multiplied by N formed by the K M-level N branch structuresM-1The branches form the second sub-path, and the sum of the delays of the first sub-path and the second sub-path is equal to the delay of the first clock path.
In a preferred embodiment, a plurality of first buffers connected in series in sequence are connected to the K gated clock units through a first register set and a combinational logic unit to form the first clock path; connecting a plurality of second buffers connected in series in sequence with the K gated clock units to form the first sub-path; and connecting the K gated clock units to the T second register groups through K M-level N-branch structures formed by a plurality of third buffers to form the second sub-paths.
In a preferred embodiment, the connecting the K clock gating units to the T second register groups through K M-level N-branch structures formed by a plurality of third buffers to form the second sub-paths includes:
one end of each third buffer of the first stage is connected with a corresponding gated clock unit, and the other end of each third buffer of the first stage is divided into N paths to be connected with one end of N third buffers of the second stage; the other end of each third buffer of the second level is divided into N paths to be connected with one end of N third buffers of the third level; and so on until the third buffer of the Mth stage forms the KxNM -1And one branch is connected with the T second registers.
In the invention, the clock control circuit and the clock control method form a second sub-path with a plurality of branches by a plurality of gate control clock units to connect a certain number of second register groups, so that the delay of the second sub-path is reduced, and the time sequence convergence effect is achieved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a circuit diagram of a timing control circuit according to a first embodiment of the present invention.
Fig. 2 is a circuit diagram of a timing control circuit according to a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 shows a circuit diagram of a clock control circuit provided in a first embodiment of the present invention, and for convenience of explanation, only the parts related to the embodiment of the present invention are shown, and the details are as follows:
as shown in fig. 1, the clock control circuit 100 includes a clock source 10, a first buffer unit 20, a first register group 30, a combinational logic unit 40, a second buffer unit 50, a plurality of clock gating units 60, a second register group 70, and a third buffer unit 80. For ease of understanding, in the preferred embodiment, the number of the clock gating units 60 is 2 for example.
The clock source 10 outputs an original clock signal CLK, the original clock signal CLK is connected to the gate control unit 60 through the first buffer unit 20, the first register set 30 and the combinational logic unit 40 to form a first clock path a, the original clock signal CLK is connected to the gate control unit 60 through the second buffer unit 50 to form a first sub-path B1, and is connected to the second register set 70 through the third buffer unit 80 to form a second sub-path B2, and the first sub-path B1 and the second sub-path B2 form a second clock path B. In the preferred embodiment, the second sub-path B2 includes a plurality of branches B21, and each of the clock-gating cells 60 is connected to the second register file 70 through one of the branches B21, such that the delay of the second sub-path B2 is reduced.
Specifically, when the same number of the second register groups 70 are connected through the clock gating unit 60, the branch B21 is set such that the overall path length of the second sub-path B2 becomes shorter, and therefore, the delay of the second sub-path B2 decreases accordingly.
In the preferred embodiment, the first buffer unit 20 and the second buffer unit 50 are used for amplifying the original clock signal CLK, so as to ensure the signal strength of the original clock signal CLK during transmission. The first buffer unit 20, the first register set 30 and the combinational logic unit 40 cooperate to amplify and logically operate the original clock signal, and then provide a control signal to the gated clock unit 60. The second buffer 50 amplifies the original clock signal and provides the first clock signal to the gate control clock unit 60, and the gate control clock unit 60 is configured to output the second clock signal to the second register group 70 under the control of the control signal, so as to control the second register group 70 to work normally. The third buffer unit 80 is configured to amplify the second clock signal CLK, so as to ensure the signal strength of the second clock signal CLK during transmission.
In the preferred embodiment, the first buffer unit 20 includes a plurality of first buffers 21 connected in series in sequence, the first buffer 21 at the beginning is connected to the clock source 10, the first buffer 21 at the end is connected to the clock terminal CLK of the first register set 30, and the output terminal Q of the first register set 30 is connected to the clock gating unit 60 through the combinational logic unit 40.
In the preferred embodiment, the second buffer unit 50 includes a plurality of second buffers 50 connected in series in sequence, the second buffer 51 at the beginning is connected to the clock source 10, and the second buffer 50 at the end is connected to the clock gating unit 60.
In the preferred embodiment, the enable terminal E of each of the clock gating units 60 is connected to the combinational logic unit 40, and when the enable terminal E is 0, the second clock signal is off, and when the enable terminal E is 1, the second clock signal is on. The clock terminal CLK of each of the clock gating units 60 is connected to the second buffer 50 at the end, and the output terminal Z of each of the clock gating units 60 is connected to the second register group 70 via the branch B21, so as to form a tree-like branch structure.
In the preferred embodiment, the third buffer unit 80 includes a plurality of third buffers 81, and the number of the third buffers 81 in each branch B21 is the same, and the number of the third buffers 81 is the number of the levels of the connection between the third buffer 81 and the corresponding clock gating unit 60.
In one embodiment, the number of stages of the third buffer unit 80 is 3, one end of the third buffer 81 of the first stage is connected to the output terminal Z of the clock gating unit 60, and the other end is divided into two paths to be connected to the third buffer 81 of the second stage, the third buffer 81 of the second stage is divided into two paths to be connected to the third buffer 81 of the third stage, and the third buffer 81 of the third stage is connected to the second register group 70. Thus, the third buffer 81 forms 2 3-level 2 branches forming 8 branches, and each clock-gating cell 60 is connected to 4 second registers 70 through 4 branches formed by one of the 3-level 2 branches.
It is understood that the number of the third buffers 81 in each branch B21 may be different, when the number of the third buffers 81 is different, the number of the stages C and the delay Tc of the third buffer unit 80 are determined by the branch B21 with the longest path, and the number of the stages C of the third buffer unit 80 is the number of the stages of the branch B21 with the longest path, and the specific number may be changed according to actual requirements.
It is understood that the combinational logic unit 40 may be a simple combinational circuit, and may be any combinational circuit capable of performing various logic operation functions. The combination circuit outputs the result of the operation to the clock gating unit 60.
In the preferred embodiment, the number of stages of the first buffer unit 20 is a, the delay is Ta, the number of stages of the second buffer unit 50 is B, the delay is Tb, the number of stages of the third buffer unit 80 is C, and the delay is Tc, so that the first clock path a and the second clock path B reach a balanced state, that is, the clock signals reaching the second register group 70 through the first clock path a and the second clock path B need to be synchronized, the number of stages of the buffer units needs to satisfy the condition a ═ B + C, and the delay needs to satisfy the formula (i): ta + Tc. When the period of the original clock signal CLK is T and the delay of the combinational logic unit 40 is TL, the clock control circuit 100 needs to satisfy the formula two: and (3) combining the formula (I) and the formula (II) to obtain a formula (III): T-TL-Tc > is 0, generally, the delay TL of the combinational logic unit 40 is large, and when the period of the original clock signal CLK is T fixed, and when the delay of the second sub-path B2 is reduced, that is, Tc is reduced, the clock control circuit 100 can satisfy the formula (c), thereby achieving the effect of timing convergence.
It can be understood that, when the number of the clock gating units 60 is larger, the number of the branches B21 is also larger, and the same number of the second register sets 70 are connected through the clock gating units 60, the shorter the overall path length of the corresponding second sub-path B2 is, the smaller Tc of the third buffer unit 80 is, and meanwhile, the sum of the delay of the first sub-path B1 and the delay of the second sub-path B2 is equal to the delay of the first clock path a, and is a certain value, and accordingly, the larger the delay Tb of the second buffer unit 50 is, it can be understood that the number of the clock gating units 60 can be adjusted according to actual requirements, as long as the clock control circuit 100 satisfies the formula (c): T-TL-Tc > may be 0.
Fig. 2 shows a circuit diagram of a clock control circuit provided in a second embodiment of the present invention, and for convenience of explanation, only the parts related to the embodiment of the present invention are shown, and the details are as follows:
as shown in fig. 2, the clock control circuit 200 has a structure substantially the same as that of the clock control circuit 100, except that the clock gating units 60 and the third buffer units 80 are different in number, specifically, the clock control circuit 200 includes a clock source 10, a first buffer unit 20, a first register set 30, a combinational logic unit 40, a second buffer unit 50, K clock gating units 60, a second register set 70, and T third buffer units 80. Wherein K, T is a positive integer.
In the preferred embodiment, the clock source 10 is connected to the K clock gating units 60 sequentially through the first buffer unit 20, the first register set 30 and the combinational logic unit 40 to form a first clock path a.
In the preferred embodiment, the first buffer unit 20 includes a plurality of first buffers 21 connected in series in sequence, the first buffer 21 at the beginning is connected to the clock source 10, the first buffer 21 at the end is connected to the clock end of the first register set 30, and the output end of the first register set 30 is connected to the K clock gating units through the combinational logic unit 40.
The clock source 10 is further connected to the K clock gating units 60 through the second buffer unit 50 to form a second sub-path B1.
In the preferred embodiment, the second buffer unit 50 includes a plurality of second buffers 50 connected in series in sequence, the second buffer 51 at the beginning is connected to the clock source 10, and the second buffer 50 at the end is connected to the K gated clock units 60.
N formed by one M-level N-branch structure per gated clock cell 60M-1A branch and NM-1The second register set 70 is connected to form a second sub-path B2. In the preferred embodiment, M, N are all positive integers, and T ≦ K × NM-1≤T+NM-11, when the number of second register sets 70 to which the clock gating cell 60 is connected is constant, the larger K, the smaller M, and the smaller the delay of each branch B21. The sum of the first sub-path delay B1 and the second sub-path delay B2 is equal to the delay of the first clock path A.
In the preferred embodiment, the enable terminal E of each clock gating cell 60 is connected to the combinational logic unit 40, the clock terminal CLK of each clock gating cell is connected to the second buffer 51 at the end, and the output terminal Z of each clock gating cell is connected to the N-th buffer 51 formed by the K M-level N-branch structuresM-1A branch and the NM-1A second register set 70 is connected.
In the preferred embodiment, in the K M-level N-branch structure, one end of each third buffer 81 of the first level is connected to the output terminal Z of a corresponding clock gating unit 60, the other end is divided into N paths and connected to one end of the N third buffers 81 of the second level, the other end of each third buffer 81 of the second level is further divided into N paths and connected to one end of the N third buffers 81 of the third level, and so on until the K × N branch structure of the M levelM-1A third buffer 81 and the T second registersThe groups 70 are connected.
The specific working principle of the clock control circuit 200 is substantially the same as that of the clock control circuit 100, and therefore, the detailed description thereof is omitted.
In the embodiment of the present invention, the clock control circuit 100 forms a tree structure with a plurality of branches B21 by a plurality of clock gating units 60 to connect the second register groups 70, and when the same number of second register groups 70 are connected by the clock gating units 60, the overall path length of the corresponding second sub-path B2 is shorter, so that the delay of the second sub-path B2 is reduced, thereby achieving the effect of timing convergence.
The embodiment of the invention also provides a clock control method, which comprises the following steps:
providing the clock control circuit 200, amplifying and logically operating the original clock signal, and outputting a control signal to the K gate control clock units 60; amplifying the original clock signal and outputting a first clock control signal to the K gate control clock units 60; and the K clock gating units 60 are connected to T second register groups 70, and each clock gating unit 60 forms N through an M-level N-branch structureM-1A branch B21 outputs a second clock control signal to NM-1A second register group 70, wherein K, M, N, T are positive integers, and T is less than or equal to K × NM-1≤T+NM-1-1, when T is constant, the larger K, the smaller M and the smaller the delay of each branch B21.
In the preferred embodiment, the original clock signal outputs the control signal through a first clock path a; and the original clock signal outputs the first clock control signal through a first sub-path B1 and outputs the second clock control signal through a second sub-path B21, and K times N are formed by K M-level N branch structuresM-1A branch B21 forms the second sub-path B2, the sum of the delays of the first sub-path B1 and the second sub-path B2 being equal to the delay of the first clock path a.
In the preferred embodiment, a plurality of first buffers connected in series in sequence are provided21 are connected to the K gated clock units 60 via a first register bank 30 and combinational logic unit 40 to form the first clock path A; connecting a plurality of second buffers 21 connected in series in sequence to the K clock-gating cells 60 to form the first sub-path B1; passing the K gated clock units 60 through K M-level N-branch structures formed by a plurality of third buffers 81 and the NM-1A second register set 70 is connected to form the second sub-path B2.
In the preferred embodiment, connecting the K clock gating units 60 to the T second register groups 70 through K M-level N-branch structures formed by a plurality of third buffers 81 to form the second sub-path B2 includes:
connecting one end of each third buffer 81 of the first stage with a corresponding gated clock unit 60, and dividing the other end into N paths to be connected with one end of N third buffers 81 of the second stage; the other end of each third buffer 81 of the second stage is further divided into N paths to be connected with one end of N third buffers 81 of the third stage; and so on until the third buffer 81 of the Mth stage forms the KxNM-1One branch is connected to the T second registers 70.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is only one logical functional division, and other divisions may be realized in practice.
The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
In addition, functional modules in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference signs in the claims shall not be construed as limiting the claim concerned. Furthermore, it is obvious that the word "comprising" does not exclude other elements or steps, and the singular does not exclude the plural. A plurality of modules or means recited in the system claims may also be implemented by one module or means in software or hardware. The terms first, second, etc. are used to denote names, but not any particular order.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.
Claims (7)
1. A clock control circuit, comprising: the clock source, a first buffer unit, a first register group, a combinational logic unit, a second buffer unit, K gating clock units, a third buffer unit and T second register groups; the third buffer unit includes a plurality of third buffers for constituting K M-level N-branch structures; the clock source is connected with the K gated clock units sequentially through the first buffer unit, the first register group and the combinational logic unit, and is also connected with the K gated clock units through the second buffer unit; n formed by M-level N-branch structure for each gated clock unitM-1A branch and NM-1A second register set; k, M, N, T are positive integers, the number of the gated clock units is multiple, and T is not more than K multiplied by NM-1≤T+NM-1-1, when T is a certain time, the larger K is, the smaller M is, and the smaller delay of each branch is, the clock source is connected to the K gated clock units through the first buffer unit, the first register group and the combinational logic unit on one hand to form a first clock path, and the clock source is connected to the K gated clock units through the second buffer unit on the other hand to form a first sub-path, and then connected to the second register group through the third buffer unit to form a second sub-path, where the second sub-path includes K × N branch structures formed by the M-level N branch structuresM-1A branch, a sum of the first sub-path delay and the second sub-path delay being equal to the delay of the first clock path.
2. The clock control circuit of claim 1, wherein the first buffer unit comprises a plurality of first buffers connected in series in sequence, the first buffer at the beginning is connected to the clock source, the first buffer at the end is connected to the clock terminal of the first register set, and the output terminal of the first register set is connected to the K clock gating units through the combinational logic unit.
3. The clock control circuit of claim 2, wherein the second buffer unit comprises a plurality of second buffers connected in series in sequence, the second buffer at the beginning end is connected to the clock source, and the second buffer at the end is connected to the K gated clock units.
4. The clock control circuit of claim 3, wherein the enable terminal of each clock gating cell is coupled to the combinational logic cell, the clock terminal of each clock gating cell is coupled to the second buffer at the end, and the output terminal of each clock gating cell is coupled to the N buffer via an N branch structure of M stagesM-1A branch and the NM-1A second register set is connected.
5. The clock control circuit of claim 4, wherein in the K M-stage N-branch structures, each of the third buffers of the first stage is connected to an output terminal of a corresponding one of the clock gating cells at one end, and the other end is divided into N paths to be connected to one ends of the N third buffers of the second stage; the other end of each third buffer of the second stage is divided into N paths and connected with one end of N third buffers of the third stage; and so on until K × N of the Mth stageM-1Third buffers are connected to the T second register groups.
6. A method of clock control, the method comprising:
amplifying and logically operating an original clock signal, and outputting a control signal to K gate control clock units;
amplifying the original clock signal and outputting a first clock control signal to the K gate control clock units; and
the K gated clock units are connected with T second register groups, and each gated clock unit is formed by an N-level N branch structureM-1Each branch outputting a second clock control signal to NM-1A second register set, wherein K, M, N, T are positive integers, the number of the gated clock units is multiple, and T is not more than K × NM-1≤T+NM-1-1, when T is constant, the larger K, the smaller M, the smaller the delay per branch;
on one hand, the original clock signal outputs the control signal through a first clock path, and a plurality of first buffers which are sequentially connected in series are connected with the K gating clock units through a first register group and a combinational logic unit to form the first clock path;
and on the other hand, the original clock signal outputs the first clock control signal through a first sub-path and outputs the second clock control signal through a second sub-path, a plurality of second buffers which are sequentially connected in series are connected with the K gating clock units to form the first sub-path, the K gating clock units are connected with the T second register groups through K M-level N branch structures formed by a plurality of third buffers to form the second sub-path, and the sum of the delay of the first sub-path and the delay of the second sub-path is equal to the delay of the first clock path.
7. The clock control method of claim 6, wherein said connecting the K clock-gating cells to the T second register groups through K M-level N-branch structures formed by a plurality of third buffers to form the second sub-path comprises:
one end of each third buffer of the first stage is connected with a corresponding gated clock unit, and the other end of each third buffer of the first stage is divided into N paths to be connected with one end of N third buffers of the second stage; the other end of each third buffer of the second level is divided into N paths to be connected with one end of N third buffers of the third level; and so on until the third buffer of the Mth stage forms the KxNM-1And one branch is connected with the T second registers.
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| CN101216721A (en) * | 2007-12-28 | 2008-07-09 | 北京航空航天大学 | Digital television modulator chip synchronization frequency division clock production devices and method |
| CN106992770A (en) * | 2016-01-21 | 2017-07-28 | 华为技术有限公司 | Clock circuit and its method for transmitting clock signal |
| CN109799870A (en) * | 2018-12-29 | 2019-05-24 | 深圳云天励飞技术有限公司 | A kind of clock control circuit and control method |
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