CN106409261A - GOA drive circuit - Google Patents
GOA drive circuit Download PDFInfo
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- CN106409261A CN106409261A CN201611069140.XA CN201611069140A CN106409261A CN 106409261 A CN106409261 A CN 106409261A CN 201611069140 A CN201611069140 A CN 201611069140A CN 106409261 A CN106409261 A CN 106409261A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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Abstract
The invention discloses a GOA drive circuit. The GOA drive circuit comprises an input control module which is used for inputting a level drive signal, a latching module which is used for latching the input level drive signal, a processing module which is used for processing the level drive signal output by the latching module into a first intermediate signal, and a buffer module which is used for buffering and processing the first intermediate signal into a gate drive signal and a second intermediate signal. The phases of the first intermediate signal and the second intermediate signal are opposite. The first intermediate signal and/or the second intermediate signal output by an upper level GOA drive circuit and a lower level GOA drive circuit control the input control module to input the level drive signal, and control the latching module to latch the level drive signal input by the input control module. According to the invention, the input control module is not controlled by a clock control signal, which effectively reduces the load for generating the clock control signal and the power consumption of the circuit.
Description
Technical field
The invention belongs to display control technology field, specifically, more particularly, to a kind of GOA drive circuit.
Background technology
GOA (Gate Driver On Array is integrated in the row scanning on array base palte) is using existing film crystal
Pipe LCD (Liquid Crystal Display) array processing procedure, by row scanning drive signal circuit production on array base palte, realizes what progressive scan drove
One technology.
Existing traditional CMOS GOA circuit design is straight and narrow, and it does not carry out too to the use of clock control signal
Many optimization, leads to the load for producing clock signal and power consumption is larger so that the power consumption of whole GOA circuit is difficult to reduce.
Content of the invention
The invention provides a kind of GOA drive circuit, do not adopt clock control signal control input control module, Ke Yiyou
Effect ground reduces the generation load of clock control signal and the power consumption of circuit.
According to one embodiment of present invention, there is provided a kind of GOA drive circuit, including：
Input control module, passes signal for input stage；
Latch module, the level for latching input passes signal；
Processing module, it is first M signal that the level for exporting described latch module passes signal processing；
Cache module, is gate drive signal and second M signal for caching and processing described first M signal,
Described first M signal and the opposite in phase of described second M signal,
Wherein, by upper level GOA drive circuit and next stage GOA drive circuit output described first M signal and/
Or described second M signal controls described input control module to carry out input stage to pass signal, and described latch module is controlled to latch
Signal is passed by the level that described input control module inputs.
According to one embodiment of present invention, described input control module includes：
The first transistor, it is P-type transistor, and grid is used for inputting in the middle of the first of next stage GOA drive circuit output
Signal, source electrode is used for input the first control signal, and drain electrode connects described latch module；
Transistor seconds, it is N-type transistor, and grid is used for inputting in the middle of the second of upper level GOA drive circuit output
Signal, source electrode is used for input the second control signal, and drain electrode connects described latch module.
According to one embodiment of present invention, described latch module includes：
First phase inverter, its input connects the drain electrode of described the first transistor and described transistor seconds, and outfan is even
Connect described processing module；
Third transistor, it is P-type transistor, and grid is used for inputting in the middle of the second of upper level GOA drive circuit output
Signal, drain electrode connects the input of described first phase inverter；
4th transistor, it is N-type transistor, and grid is used for inputting in the middle of the first of next stage GOA drive circuit output
Signal, drain electrode connects the source electrode of described third transistor；
Second phase inverter, its input connects the outfan of described first phase inverter, and outfan connects described 4th crystal
The source electrode of pipe.
According to one embodiment of present invention, described input control module includes：
The first transistor, it is P-type transistor, and grid is used for inputting in the middle of the first of upper level GOA drive circuit output
Signal, source electrode is used for input the first control signal, and drain electrode connects described latch module；
Transistor seconds, it is N-type transistor, and grid is used for inputting in the middle of the second of next stage GOA drive circuit output
Signal, source electrode is used for input the second control signal, and drain electrode connects described latch module.
According to one embodiment of present invention, described latch module includes：
First phase inverter, its input connects the drain electrode of described the first transistor and described transistor seconds；
Second phase inverter, its input connects the outfan of described first phase inverter, and outfan connects described processing module；
Third transistor, it is N-type transistor, and grid is used for inputting in the middle of the first of upper level GOA drive circuit output
Signal, drain electrode connects the input of described first phase inverter；
4th transistor, it is P-type transistor, and grid is used for inputting in the middle of the second of next stage GOA drive circuit output
Signal, drain electrode connects the source electrode of described third transistor, and source electrode connects the outfan of described second phase inverter.
According to one embodiment of present invention, described input control module includes：
The first transistor, it is N-type transistor, and grid is used for inputting in the middle of the second of upper level GOA drive circuit output
Signal, source electrode is used for input the second control signal, and drain electrode connects described latch module；
Transistor seconds, it is N-type transistor, and grid is used for inputting in the middle of the second of next stage GOA drive circuit output
Signal, source electrode is used for input the second control signal, and drain electrode connects described latch module.
According to one embodiment of present invention, described latch module includes：
First phase inverter, its input connects the drain electrode of described the first transistor, and outfan connects described processing module；
Third transistor, it is P-type transistor, and grid is used for inputting in the middle of the second of upper level GOA drive circuit output
Signal, drain electrode connects the input of described first phase inverter；
4th transistor, it is P-type transistor, and grid is used for inputting in the middle of the second of next stage GOA drive circuit output
Signal, source electrode connects the outfan of described first phase inverter；
Second phase inverter, its input connects the drain electrode of described third transistor, and outfan connects described 4th transistor
Source electrode.
According to one embodiment of present invention, described input control module includes：
The first transistor, it is P-type transistor, and grid is used for inputting in the middle of the first of next stage GOA drive circuit output
Signal, source electrode is used for input the first control signal, and drain electrode connects described latch module；
Transistor seconds, it is P-type transistor, and grid is used for inputting in the middle of the first of upper level GOA drive circuit output
Signal, source electrode is used for input the first control signal, and drain electrode connects described latch module.
According to one embodiment of present invention, described latch module includes：
First phase inverter, its input connects the drain electrode of described the first transistor, and outfan connects described processing module；
Third transistor, it is N-type transistor, and grid is used for inputting in the middle of the first of next stage GOA drive circuit output
Signal, drain electrode connects the input of described first phase inverter；
4th transistor, it is N-type transistor, and grid is used for inputting in the middle of the first of upper level GOA drive circuit output
Signal, source electrode connects the outfan of described first phase inverter；
Second phase inverter, its input connects the drain electrode of described 4th transistor, and outfan connects described third transistor
Source electrode.
According to one embodiment of present invention,
Described processing module includes a NAND gate, and its first input end connects the outfan of described latch module, and second is defeated
Enter end and connect the first Timing driver signal, outfan is connected with described cache module and exports described first M signal,
Described cache module includes the 3rd phase inverter, the 4th phase inverter and the 5th phase inverter connected, wherein,
The input of described 3rd phase inverter connects described processing module, and outfan connects the input of described 4th phase inverter
End；
The outfan of described 4th phase inverter connects the input of described 5th phase inverter, and exports letter in the middle of described second
Number；
The outfan output gate drive signal of described 5th phase inverter,
Described reseting module includes hex inverter and the 5th transistor being connected with described hex inverter, wherein,
The outfan of described hex inverter connects the outfan of described cache module, and input connects the described 5th respectively
The drain electrode of transistor and the input of described hex inverter；
The source electrode of described 5th transistor introduces the first control signal, and grid introduces reset signal.
Beneficial effects of the present invention：
The GOA drive circuit that the present invention provides, does not adopt clock control signal control input control module, is effectively reduced
Produce the load of clock control signal and the power consumption of circuit.
Other features and advantages of the present invention will illustrate in the following description, and, partly become from description
Obtain it is clear that or being understood by implementing the present invention.The purpose of the present invention and other advantages can be by description, rights
In claim and accompanying drawing, specifically noted structure is realizing and to obtain.
Brief description
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, required in embodiment being described below
Accompanying drawing does simple introduction：
Fig. 1 is a kind of GOA drive circuit schematic diagram in prior art；
Fig. 2 a-2c is the internal structure schematic diagram of partial circuit components and parts in Fig. 1；
Fig. 3 is working timing figure during Fig. 1 scanning；
Fig. 4 is driving circuit structure figure according to an embodiment of the invention；
Fig. 5 is driving circuit structure figure according to first embodiment of the invention；
Fig. 6 is the driving circuit structure figure of second embodiment according to the present invention；
Fig. 7 is the driving circuit structure figure of the 3rd embodiment according to the present invention；
Fig. 8 is the driving circuit structure figure of the 4th embodiment according to the present invention；
Fig. 9 is driving configuration diagram according to an embodiment of the invention；
Figure 10 is working timing figure during drive circuit scanning according to an embodiment of the invention；
Figure 11 is simulation waveform sequential chart during scanning according to an embodiment of the invention；
Figure 12 is simulation waveform sequential chart during scanning according to another embodiment of the invention.
Specific embodiment
To describe embodiments of the present invention in detail below with reference to drawings and Examples, whereby how the present invention to be applied
Technological means are solving technical problem, and reach realizing process and fully understanding and implement according to this of technique effect.Need explanation
As long as not constituting conflict, each embodiment in the present invention and each feature in each embodiment can be combined with each other,
The technical scheme being formed is all within protection scope of the present invention.
It is a kind of traditional CMOS GOA drive circuit in prior art as shown in Figure 1, this circuit is using staggered driving side
Formula, monolateral GOA drive circuit needs two clock control signal CK cablings (as clock control signal CK1 cabling, clock control letter
Number CK2 cabling), an enabling signal STV cabling (not shown), a reset signal RESET cabling, a high potential signal
VGH cabling and a low-potential signal VGL cabling.As shown in figure 1, this CMOS GOA drive circuit is mainly by several portions as follows
It is grouped into.
The signal input that input control module 100 is used for GOA drive circuit controls, by CK1 signal and XCK1 signal control
Make its internal clocked inverter, realize the transmission of upper level Q point signal；Latch module 200 is by its internal clocking
Control the control of phase inverter, realize the latch of this grade of Q point signal；RESET module 300 includes a transistor PTFT1 and phase inverter
IN2, for the reset processing of signal node in circuit；The processing module 400 (NAND gate NAND) of Q point signal passes through CK3 signal
With Q point signal and non-process, produce the gate drive signal of this grade；Gate drive signal buffer process module 500, including three
Phase inverter IN3, IN4, IN5 of individual series connection, for improving the driving force of gate drive signal.Wherein, the Q in Fig. 1 (N) represents
The Q point signal of N level GOA drive circuit, Q point is the point for the output of control gate drive signal；P (N) represents N level GOA
The P point signal of drive circuit, P point is the point for controlling holding circuit between circuit inaction period stably to export.CK1 signal warp
XCK1 signal is obtained after phase inverter IN1 is anti-phase.Q (N-1) is that the level of N level GOA drive circuit passes signal.
If Fig. 2 a-2c is the equivalent circuit diagram of part components and parts in CMOS GOA drive circuit in Fig. 1, wherein, Fig. 2 a is
The corresponding equivalent circuit of each phase inverter in Fig. 1, Fig. 2 b is the corresponding equivalent circuit of clocked inverter in Fig. 1, and Fig. 2 c is Fig. 1
The corresponding equivalent circuit of middle NAND gate.
Fig. 3 is the working timing figure of GOA drive circuit shown in Fig. 1, is analyzed from Fig. 3, and the work of circuit shown in Fig. 1 is former
Manage and be：Before level passes signal Q (N-1) input, all GOA drive circuits first carry out reset processing, and the Q node of all circuit is multiple
Position is low level, and gate drive signal is low level；High electricity when the CK1 signal of upper level Q point signal and this grade of control input
Flat pulse signal is simultaneously interim, and Q (N) point is charged to high level, when the CK1 signal of control input becomes low level, lock
Storing module 200 latches the high level signal that Q (N) puts；When the high level pulse signal of the control CK3 signal of NAND gate comes temporarily,
GATE (n) signal output high level signal, that is, produce the gate drive signal of this grade；High electricity when the CK1 signal of control input
Flat pulse signal comes temporarily again, and Q (N) point is charged to low level, and afterwards, Q (N) point latches and input low level letter always
Number, GATE (N) signal maintains stable low level output.
Analyzed from above, existing COMS GOA drive circuit input control module 100 needs CK1 signal to be controlled
System, it is used for producing the circuit of CK1 signal and load consumption is larger so that the power consumption of whole GOA circuit is difficult to reduce.
Therefore, the invention provides a kind of GOA drive circuit, its input control module 100 does not need CK1 signal to be controlled
System, is effectively reduced for producing the load of CK1 signal and the power consumption of circuit.It is a reality according to the present invention as shown in Figure 4
Apply the GOA driving circuit structure figure of example, the present invention is described in detail below with reference to Fig. 4.
This GOA drive circuit includes input control module 21, latch module 22, processing module 23 and cache module 24.Defeated
Enter control module 21 and pass signal for input stage；The level that latch module 22 is used for latching input passes signal；Processing module 23 is used for
It is first M signal that the level that latch module is exported passes signal processing；Cache module 24 is used for caching and process letter in the middle of first
Number be gate drive signal and second M signal, the opposite in phase of first M signal and second M signal, wherein, by upper
The first M signal of one-level GOA drive circuit and the output of next stage GOA drive circuit and/or second M signal control input
Control module 21 is carried out input stage and is passed signal, and controls latch module 22 to latch the level biography letter being inputted by input control module 21
Number.
The GOA drive circuit that the present invention provides, latch module 22 and input control module 21 do not adopt clock control signal
Control, significantly reduce the generation load of clock control signal and the power consumption of circuit.
According to one embodiment of present invention, this input control module 21 includes the first transistor T11 and transistor seconds
T12, as shown in Figure 5.The first transistor T11 is P-type transistor, and its grid is used for inputting the output of next stage GOA drive circuit
((N+1), source electrode is used for input the first control signal VGH to first M signal XP, and drain electrode connects latch module 22；Second crystal
Pipe T12 is N-type transistor, and grid is used for inputting second M signal P ((N-1), the source electrode of upper level GOA drive circuit output
For inputting the second control signal VGL, drain electrode connects latch module 22.GOA drive circuit shown in Fig. 5 eliminates traditional cmos
Clocked inverter module in GOA circuit, input control module is not controlled using CK1 signal, directly adopts upper one
The second M signal of the first M signal of level and next stage carries out to the Q point of this grade pulling up and drop-down process respectively.
As shown in figure 5, pull-up process, T12 transistor are carried out to this grade of Q point signal using T12, T13 and P (N-1) signal
For the transmission of Q point signal, T13 transistor is used for the on-off control of latch loop, and P (N-1) is the second of upper level GOA circuit
M signal, for the on-off control of T12 and T13 transistor.Using T11, T14 and XP (N+1) signal, this grade of Q point signal is entered
The drop-down process of row, T11 transistor is used for the transmission of Q point signal low level signal, and T14 transistor is used for the switch control of latch loop
System, XP (N+1) is the first M signal of next stage GOA circuit.Circuit shown in Fig. 5 carries out the transmission of VGH signal using PTFT,
Carry out the transmission of VGL signal using NTFT, the threshold voltage Vth loss of transmission signal can be reduced.
According to one embodiment of present invention, this latch module include the first phase inverter IN11, the second phase inverter IN12,
Three transistor T13 and the 4th transistor T14, as shown in Figure 5.The input of the first phase inverter IN11 connects the first transistor T11
With the drain electrode of transistor seconds T12, outfan connection processing module 23；Third transistor T13 is P-type transistor, and grid is used for
Second M signal P (N-1) of input upper level GOA drive circuit output, drain electrode connects the input of the first phase inverter IN11；
4th transistor T14 is N-type transistor, and grid is used for inputting the first M signal XP (N+ of next stage GOA drive circuit output
1), drain electrode connects the source electrode of third transistor T13；The input of the second phase inverter IN12 connects the output of the first phase inverter IN11
End, outfan connects the source electrode of the 4th transistor T14.
According to one embodiment of present invention, this input control module includes the first transistor T21 and transistor seconds
T22, as shown in Figure 6.The first transistor T21 is P-type transistor, and grid is used for inputting the of the output of upper level GOA drive circuit
One M signal XP (N-1), source electrode is used for input the first control signal VGH, and drain electrode connects latch module 23. transistor seconds
T22 is N-type transistor, and grid is used for inputting second M signal P (N+1) of next stage GOA drive circuit output, and source electrode is used for
Input the second control signal VGL, drain electrode connects latch module 23.
According to one embodiment of present invention, this latch module include the first phase inverter IN21, the second phase inverter IN22,
Three transistor T23 and the 4th transistor T24, as shown in Figure 6.The input of the first phase inverter IN21 connects the first transistor T11
Drain electrode with transistor seconds T12；The input of the second phase inverter IN22 connects the outfan of the first phase inverter IN21, outfan
Connect processing module 23；Third transistor T23 is P-type transistor, and grid is used for inputting the of the output of next stage GOA drive circuit
Two M signal P (N+1), drain electrode connects the outfan of the second phase inverter IN22；4th transistor T24 is N-type transistor, grid
For inputting first M signal XP (N-1) of upper level GOA drive circuit output, drain electrode connects the source of third transistor T23
Pole, source electrode connects the input of the first phase inverter IN21.
From Fig. 5 and Fig. 6, third transistor and the 4th transistor are used for latching the switch control in loop in latch module
System.As shown in figure 5, this latch loop is brilliant by the first phase inverter IN11, the second phase inverter IN12, third transistor T13 and the 4th
Body pipe T14 is constituted.When level passes signal after the first transistor T11 or transistor seconds T12 arrival latch module, upper level
Second M signal P (N-1) of GOA drive circuit output is low level, the first middle letter of next stage GOA drive circuit output
Number XP (N+1) is low and high level, and now third transistor T13 and the 4th transistor T14 open, and level passes signal and is saved in and latches back
Lu Zhong.As shown in fig. 6, this latch loop is by the first phase inverter IN21, the second phase inverter IN22, third transistor T23 and the 4th
Transistor T24 is constituted.When level passes signal after the first transistor T21 or transistor seconds T22 arrival latch module, upper level
GOA drive circuit output first M signal XP (N-1) be high level, next stage GOA drive circuit output second in the middle of
Signal P (N+1) is low level, and now third transistor T23 and the 4th transistor T24 open, and level biography signal is saved in and latches back
Lu Zhong.In the present invention, latch module does not adopt clock control signal control, can effectively reduce and produce clock control signal
Load and the power consumption of circuit.
According to one embodiment of present invention, this input control module includes the first transistor T31 and transistor seconds
T32, as shown in Figure 7.The first transistor T31 is N-type transistor, and grid is used for inputting the of the output of upper level GOA drive circuit
Two M signal P (N-1), source electrode is used for input the second control signal VGL, and drain electrode connects latch module 22；Transistor seconds T32
For N-type transistor, for inputting second M signal P (N+1) of next stage GOA drive circuit output, source electrode is used for defeated grid
Enter the second control signal VGL, drain electrode connects latch module 22.
According to one embodiment of present invention, this latch module include the first phase inverter IN31, the second phase inverter IN32,
Three transistor T33 and the 4th transistor T34, as shown in Figure 7.First phase inverter IN31 input connects the first transistor T31's
Drain electrode, outfan connects processing module；Third transistor T33 is P-type transistor, and grid is used for inputting upper level GOA driving electricity
(N-1, drain electrode connects the input of the first phase inverter IN31 to second M signal P of road output；4th transistor T34 is that p-type is brilliant
Body pipe, its grid is used for inputting second M signal P (N+1) of next stage GOA drive circuit output, and it is anti-phase that source electrode connects first
The outfan of device IN31；Second phase inverter IN32 outfan connects the source electrode of third transistor T33, and input connects the 4th crystal
The drain electrode of pipe T34.
As shown in fig. 7, drop-down process, T32 transistor are carried out to this grade of Q point signal using T32, T34 and P (N+1) signal
For the transmission of Q point signal, T34 transistor is used for the on-off control of latch loop, and P (N+1) is the second of next stage GOA circuit
M signal, for the on-off control of T32 and T34 transistor.Using T31, T33 and P (N-1) signal, this grade of Q point signal is entered
The drop-down process of row, T31 transistor is used for the transmission of Q point signal low level signal, and T33 transistor is used for the switch control of latch loop
System.Circuit shown in Fig. 7 carries out the transmission of VGL signal using NTFT, can reduce the threshold voltage Vth loss of transmission signal.
According to one embodiment of present invention, this input control module includes the first transistor T41 and transistor seconds
T42, as shown in Figure 8.The first transistor T41 is P-type transistor, and grid is used for inputting the of the output of next stage GOA drive circuit
One M signal XP (N+1), source electrode is used for input the first control signal VGH, and drain electrode connects latch module 22.Transistor seconds
T42 is P-type transistor, and grid is used for inputting first M signal P (N-1) of upper level GOA drive circuit output, and source electrode is used for
Input the first control signal VGH, drain electrode connects latch module 22.
According to one embodiment of present invention, this latch module include the first phase inverter IN41, the second phase inverter IN42,
Three transistor T43 and the 4th transistor T44, as shown in Figure 8.The input of the first phase inverter IN41 connects the first transistor T41
Drain electrode, outfan connect processing module 23；Third transistor T43 is N-type transistor, and grid is used for inputting next stage GOA drive
First M signal XP (N+1) of dynamic circuit output, drain electrode connects the input of the first phase inverter IN41；4th transistor T44
For N-type transistor, grid is used for inputting first M signal XP (N-1) of upper level GOA drive circuit output, drain electrode connection the
The outfan of one phase inverter IN41；The input of the second phase inverter IN42 connects the drain electrode of the 4th transistor T44, and outfan connects
The source electrode of third transistor T43.
From Fig. 7 and Fig. 8, third transistor and the 4th transistor are used for latching the switch control in loop in latch module
System.As shown in fig. 7, this latch loop is brilliant by the first phase inverter IN31, the second phase inverter IN32, third transistor T33 and the 4th
Body pipe T34 is constituted.When level passes signal after the first transistor T31 or transistor seconds T32 arrival latch module, upper level
Second M signal P (N-1) of GOA drive circuit output is low level, the second middle letter of next stage GOA drive circuit output
Number P (N+1) is low level, and now third transistor T33 and the 4th transistor T34 open, and level passes signal and is saved in latch loop
In.As shown in figure 8, this latch loop is brilliant by the first phase inverter IN41, the second phase inverter IN42, third transistor T43 and the 4th
Body pipe T44 is constituted.When level passes signal after the first transistor T41 or transistor seconds T42 arrival latch module, upper level
GOA drive circuit output first M signal XP (N-1) be high level, next stage GOA drive circuit output first in the middle of
Signal XP (N+1) is low level, and now third transistor T43 and the 4th transistor T44 open, and level biography signal is saved in and latches back
Lu Zhong.In the present invention, latch module does not adopt clock control signal control, can effectively reduce and produce clock control signal
Load and the power consumption of circuit.
According to one embodiment of present invention, this processing module 23 includes NAND gate NAND, and its first input end connects
The outfan of latch module, the second input connects the first Timing driver signal CK3, and outfan Connection Cache module simultaneously exports this
First M signal P (N) of level, as shown in Figure 5-Figure 8.
According to one embodiment of present invention, this cache module 24 includes connecting the 3rd phase inverter IN23, the 4th anti-phase
Device IN24 and the 5th phase inverter IN25, wherein, the input of the 3rd phase inverter IN23 connects processing module, and outfan connects the 4th
The input of phase inverter IN24；The outfan of the 4th phase inverter IN24 connects the input of the 5th phase inverter IN25, and exports the
Two M signals；The outfan output gate drive signal of the 5th phase inverter IN25, as shown in Figure 5-Figure 8.
According to one embodiment of present invention, reseting module is included hex inverter IN26 and is connected with hex inverter IN26
The 5th transistor T25 connecing, wherein, the outfan of the outfan Connection Cache module of hex inverter IN26, input is respectively
Connect the drain electrode of the 5th transistor T25 and the input of hex inverter IN26；The source electrode of the 5th transistor T25 introduces the first control
Signal processed, grid introduces reset signal.
Be illustrated in figure 9 Fig. 5-to circuit shown in Fig. 8 driver framework figure, this driver framework figure is monolateral driver framework
Figure, the scan line of corresponding odd-numbered line, wherein, monolateral GOA circuit needs two STV signal lead, is respectively used to first order GOA electricity
The pull-up of road Q point and afterbody GOA circuit Q point drop-down；Monolateral two CK signal lead of needs, shift for grid and drive
The generation of signal；Monolateral piece RESET cabling of needs, for the reset processing of every one-level GOA circuit；Monolateral one VGH of needs
Cabling and a VGL cabling, for the driving of CMOS GOA circuit.
As the turntable driving sequential chart of Figure 10 driver framework shown in Fig. 9, from time chart analysis, this patent provides
The operation principle of GOA circuit is：When RESETt signal low level pulse signal comes temporarily, all of GOA circuit is carried out at reset
Reason, Q point latches low level signal after resetting；When XP0 low level pulse or P0 high level pulse signal come temporarily, Q point is filled
Electricity latches high level signal to high level, afterwards Q point；When temporarily the high level pulse of CK3 signal, to produce in the middle of this level first
Signal XP1；The buffered resume module of this grade of first M signal XP1 is this grade of gate drive signal GATE1；Low electricity as XP2
The live high level pulse signal of P2 of flat pulse comes interim, and Q point is charged to low level, and Q point latches low level letter always afterwards
Number, GOA circuit stability exports low level gate drive signal.
If Figure 11 is the first turntable driving emulation schematic diagram according to one embodiment of the present of invention, according to such as Figure 12
The second turntable driving emulation schematic diagram of one embodiment of the present of invention, from Figure 11 and Figure 12, the circuit of the present invention can
To realize exporting forward or backwards scanning signal.
While it is disclosed that embodiment as above, but described content is only to facilitate understanding the present invention and adopting
Embodiment, is not limited to the present invention.Technical staff in any the technical field of the invention, without departing from this
On the premise of the disclosed spirit and scope of invention, any modification and change can be made in the formal and details implemented,
But the scope of patent protection of the present invention, still must be defined by the scope of which is defined in the appended claims.
Claims (10)
1. a kind of GOA drive circuit, including：
Input control module, passes signal for input stage；
Latch module, the level for latching input passes signal；
Processing module, it is first M signal that the level for exporting described latch module passes signal processing；
Cache module, is gate drive signal and second M signal for caching and processing described first M signal, described
First M signal and the opposite in phase of described second M signal,
Wherein, by described first M signal and/or the institute of upper level GOA drive circuit and the output of next stage GOA drive circuit
Stating second M signal controls described input control module to carry out input stage biography signal, and controls described latch module to latch by institute
The level stating input control module input passes signal.
2. circuit according to claim 1 is it is characterised in that described input control module includes：
The first transistor, it is P-type transistor, and grid is used for inputting the first M signal of next stage GOA drive circuit output,
Source electrode is used for input the first control signal, and drain electrode connects described latch module；
Transistor seconds, it is N-type transistor, and grid is used for inputting the second M signal of upper level GOA drive circuit output,
Source electrode is used for input the second control signal, and drain electrode connects described latch module.
3. circuit according to claim 2 is it is characterised in that described latch module includes：
First phase inverter, its input connects the drain electrode of described the first transistor and described transistor seconds, and outfan connects institute
State processing module；
Third transistor, it is P-type transistor, and grid is used for inputting the second M signal of upper level GOA drive circuit output,
Drain electrode connects the input of described first phase inverter；
4th transistor, it is N-type transistor, and grid is used for inputting the first M signal of next stage GOA drive circuit output,
Drain electrode connects the source electrode of described third transistor；
Second phase inverter, its input connects the outfan of described first phase inverter, and outfan connects described 4th transistor
Source electrode.
4. circuit according to claim 1 is it is characterised in that described input control module includes：
The first transistor, it is P-type transistor, and grid is used for inputting the first M signal of upper level GOA drive circuit output,
Source electrode is used for input the first control signal, and drain electrode connects described latch module；
Transistor seconds, it is N-type transistor, and grid is used for inputting the second M signal of next stage GOA drive circuit output,
Source electrode is used for input the second control signal, and drain electrode connects described latch module.
5. circuit according to claim 4 is it is characterised in that described latch module includes：
First phase inverter, its input connects the drain electrode of described the first transistor and described transistor seconds；
Second phase inverter, its input connects the outfan of described first phase inverter, and outfan connects described processing module；
Third transistor, it is N-type transistor, and grid is used for inputting the first M signal of upper level GOA drive circuit output,
Drain electrode connects the input of described first phase inverter；
4th transistor, it is P-type transistor, and grid is used for inputting the second M signal of next stage GOA drive circuit output,
Drain electrode connects the source electrode of described third transistor, and source electrode connects the outfan of described second phase inverter.
6. circuit according to claim 1 is it is characterised in that described input control module includes：
The first transistor, it is N-type transistor, and grid is used for inputting the second M signal of upper level GOA drive circuit output,
Source electrode is used for input the second control signal, and drain electrode connects described latch module；
Transistor seconds, it is N-type transistor, and grid is used for inputting the second M signal of next stage GOA drive circuit output,
Source electrode is used for input the second control signal, and drain electrode connects described latch module.
7. circuit according to claim 6 is it is characterised in that described latch module includes：
First phase inverter, its input connects the drain electrode of described the first transistor, and outfan connects described processing module；
Third transistor, it is P-type transistor, and grid is used for inputting the second M signal of upper level GOA drive circuit output,
Drain electrode connects the input of described first phase inverter；
4th transistor, it is P-type transistor, and grid is used for inputting the second M signal of next stage GOA drive circuit output,
Source electrode connects the outfan of described first phase inverter；
Second phase inverter, its input connects the drain electrode of described third transistor, and outfan connects the source of described 4th transistor
Pole.
8. circuit according to claim 1 is it is characterised in that described input control module includes：
The first transistor, it is P-type transistor, and grid is used for inputting the first M signal of next stage GOA drive circuit output,
Source electrode is used for input the first control signal, and drain electrode connects described latch module；
Transistor seconds, it is P-type transistor, and grid is used for inputting the first M signal of upper level GOA drive circuit output,
Source electrode is used for input the first control signal, and drain electrode connects described latch module.
9. circuit according to claim 8 is it is characterised in that described latch module includes：
First phase inverter, its input connects the drain electrode of described the first transistor, and outfan connects described processing module；
Third transistor, it is N-type transistor, and grid is used for inputting the first M signal of next stage GOA drive circuit output,
Drain electrode connects the input of described first phase inverter；
4th transistor, it is N-type transistor, and grid is used for inputting the first M signal of upper level GOA drive circuit output,
Source electrode connects the outfan of described first phase inverter；
Second phase inverter, its input connects the drain electrode of described 4th transistor, and outfan connects the source of described third transistor
Pole.
10. circuit according to claim 1 it is characterised in that
Described processing module includes a NAND gate, and its first input end connects the outfan of described latch module, the second input
Connect the first Timing driver signal, outfan is connected with described cache module and exports described first M signal,
Described cache module includes the 3rd phase inverter, the 4th phase inverter and the 5th phase inverter connected, wherein,
The input of described 3rd phase inverter connects described processing module, and outfan connects the input of described 4th phase inverter；
The outfan of described 4th phase inverter connects the input of described 5th phase inverter, and exports described second M signal；
The outfan output gate drive signal of described 5th phase inverter,
Described reseting module includes hex inverter and the 5th transistor being connected with described hex inverter, wherein,
The outfan of described hex inverter connects the outfan of described cache module, and input connects described 5th crystal respectively
The drain electrode of pipe and the input of described hex inverter；
The source electrode of described 5th transistor introduces the first control signal, and grid introduces reset signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611069140.XA CN106409261B (en) | 2016-11-29 | 2016-11-29 | GOA drive circuit |
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|---|---|---|---|
| CN201611069140.XA CN106409261B (en) | 2016-11-29 | 2016-11-29 | GOA drive circuit |
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| CN106409261B CN106409261B (en) | 2020-09-04 |
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| CN106782358A (en) * | 2016-11-29 | 2017-05-31 | 武汉华星光电技术有限公司 | A kind of GOA drive circuits |
| WO2018094817A1 (en) * | 2016-11-28 | 2018-05-31 | 武汉华星光电技术有限公司 | Goa drive circuit |
| CN110545091A (en) * | 2018-05-28 | 2019-12-06 | 深圳指芯智能科技有限公司 | Latch circuit |
| CN114170987A (en) * | 2021-12-09 | 2022-03-11 | 武汉华星光电技术有限公司 | Grid driving circuit and display panel |
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| CN114170987A (en) * | 2021-12-09 | 2022-03-11 | 武汉华星光电技术有限公司 | Grid driving circuit and display panel |
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| Publication number | Publication date |
|---|---|
| CN106409261B (en) | 2020-09-04 |
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