CN106098016B - Scan drive circuit and flat display apparatus with the circuit - Google Patents
Scan drive circuit and flat display apparatus with the circuit Download PDFInfo
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- CN106098016B CN106098016B CN201610717822.0A CN201610717822A CN106098016B CN 106098016 B CN106098016 B CN 106098016B CN 201610717822 A CN201610717822 A CN 201610717822A CN 106098016 B CN106098016 B CN 106098016B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- Computer Hardware Design (AREA)
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- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of scan drive circuit and flat display apparatus, scan drive circuit includes cascade multiple scan drive cells, and each scan drive cell includes that first and second input circuit receives the first clock signal and drive signal and exports first and second input signal；Pull-down circuit receives second clock signal and exports pulldown signal and drop-down control signaling point is pulled down or charged；First and second control circuit receives first and second input signal to first and second pull-up control signaling point charging, or receives pulldown signal to first and second pull-up control signaling point drop-down；First output circuit receives the first scanning drive signal of third clock signal generation and drives pixel unit to the first scan line；Second output circuit receives the second scanning drive signal of the 4th clock signal generation and drives pixel unit to the second scan line, and the circuit of simplified flat display apparatus is realized with this, saves space, and then conducive to the narrow frame design of flat display apparatus.
Description
Technical field
The present invention relates to display technology fields, aobvious more particularly to a kind of scan drive circuit and plane with the circuit
Showing device.
Background technology
Scan drive circuit is used in current flat display apparatus, that is, is shown using existing thin film transistor (TFT) plane
Scan drive circuit is produced in array substrate by device array process, realizes the type of drive to progressive scan.Existing plane
Each scan drive circuit only drives a scan line in display device, and all multi-strip scannings are arranged in general plane display device
Line, this will need to design many scan drive circuits, certainly will make complex circuit designs, and occupied space, and it is aobvious to be unfavorable for plane
The narrow frame design of showing device.
Invention content
The invention mainly solves the technical problem of providing a kind of scan drive circuits and plane with the circuit to show
Device saves space, and then conducive to the narrow frame design of flat display apparatus to simplify the circuit of flat display apparatus.
In order to solve the above technical problems, one aspect of the present invention is：A kind of scan drive circuit, institute are provided
It includes cascade multiple scan drive cells to state scan drive circuit, and each scan drive cell includes：
First input circuit, for receiving the first clock signal and drive signal and exporting the first input signal；
Second input circuit, for receiving the first clock signal and drive signal and exporting the second input signal；
Pull-down circuit, for receiving second clock signal and exporting pulldown signal and according to the second clock signal under
Control signaling point is drawn to be pulled down or charged；
First control circuit, for receiving first input signal from first input circuit and according to described first
The pull-up control signaling point of input signal pair first charges, or receives the pulldown signal and basis from the pull-down circuit
The pulldown signal pulls down the first pull-up control signaling point；
Second control circuit, for receiving second input signal from second input circuit and according to described second
The pull-up control signaling point of input signal pair second charges, or receives the pulldown signal and basis from the pull-down circuit
The pulldown signal pulls down the second pull-up control signaling point；
First output circuit drives for receiving third clock signal and generating the first scanning according to the third clock signal
Dynamic signal is exported drives pixel unit to the first scan line；And
Second output circuit drives for receiving the 4th clock signal and generating the second scanning according to the 4th clock signal
Dynamic signal is exported drives pixel unit to the second scan line.
Wherein, first input circuit includes the first controllable switch, and the control terminal of first controllable switch receives institute
State the first clock signal, the first end of first controllable switch receives the drive signal, and the of first controllable switch
Two ends connect the pull-down circuit and the first control circuit.
Wherein, the pull-down circuit includes the second to the 8th controllable switch and the first capacitance, second controllable switch
Control terminal connects the second end of first controllable switch, the first end of the third controllable switch and the first control electricity
Road, the first end of second controllable switch, which receives, closes voltage end signal, and the second end of second controllable switch connects institute
State the control terminal of the third controllable switch, control terminal of the 4th controllable switch, the control terminal of the 7th controllable switch, described
The second end of the control terminal of 8th controllable switch, the first end of the 5th controllable switch and the 6th controllable switch, it is described
The second end of third controllable switch connects the first end of the 4th controllable switch, the second end of the 7th controllable switch and institute
State the first end of the 8th controllable switch, the second end of the 4th controllable switch connect the control terminal of the 5th controllable switch,
The second end of second input circuit and the second control circuit, the 5th controllable switch receives the closing voltage end
The control terminal of signal, the 6th controllable switch receives the second clock signal, the first termination of the 6th controllable switch
Cut-in voltage end signal is received, the first end of the 7th controllable switch connects first output circuit, and the described 8th controllably opens
The second end of pass connects second output circuit, first end and the of first capacitance connection in the 6th controllable switch
Between two ends.
Wherein, the first control circuit includes the 9th controllable switch, and the control terminal of the 9th controllable switch receives institute
Cut-in voltage end signal is stated, the first end of the 9th controllable switch connects the control terminal and described of second controllable switch
The second end of the first end of three controllable switches, the 9th controllable switch connects first output circuit.
Wherein, first output circuit includes the tenth controllable switch and the second capacitance, the control of the tenth controllable switch
End processed connects the second end of the 9th controllable switch, and the first end of the tenth controllable switch receives the third clock letter
Number, the second end of the tenth controllable switch connects first scan line and the first end of the 7th controllable switch, described
Second capacitance connection is between the control terminal and second end of the tenth controllable switch.
Wherein, second input circuit includes the 11st controllable switch, and the control of the 11st controllable switch terminates
First clock signal is received, the first end of the 11st controllable switch receives the drive signal, and the described 11st is controllable
The second end of switch connects the control terminal of the 5th controllable switch.
Wherein, the second control circuit includes the 12nd controllable switch, and the control of the 12nd controllable switch terminates
Receive the cut-in voltage end signal, the first end of the 12nd controllable switch connect the 4th controllable switch second end and
The second end of the control terminal of 5th controllable switch, the 12nd controllable switch connects second output circuit.
Wherein, second output circuit includes the 13rd controllable switch and third capacitance, the 13rd controllable switch
Control terminal connect the second end of the 12nd controllable switch, the first end connection described second of the 13rd controllable switch
The second end of the second end of scan line and the 8th controllable switch, the 13rd controllable switch receives the 4th clock letter
Number, the third capacitance connection is between the control terminal and first end of the 13rd controllable switch.
Wherein, the described first to the 13rd controllable switch is N-type TFT, the described first to the 13rd controllable switch
Control terminal, first end and second end correspond to grid, drain electrode and the source electrode of the N-type TFT respectively；Or described
One to the 13rd controllable switch is P-type TFT, the control terminal of the described first to the 13rd controllable switch, first end and the
Two ends correspond to grid, drain electrode and the source electrode of the P-type TFT respectively.
In order to solve the above technical problems, another technical solution used in the present invention is：A kind of flat display apparatus is provided,
The flat display apparatus includes such as any of the above-described scan drive circuit.
The beneficial effects of the invention are as follows：The case where being different from the prior art, the scan drive circuit of the present invention of the invention
First and second pull-up control signaling point is filled by first and second input circuit and first and second control circuit
Electricity, and realized to the drop-down control of drop-down control signaling point by the way that a pull-down circuit is arranged, pass through first and second output
First and second scanning drive signal of circuit output is respectively supplied to first and second scan line to drive corresponding pixel unit,
The circuit of simplified flat display apparatus is realized with this, saves space, and then conducive to the narrow frame design of flat display apparatus.
Description of the drawings
Fig. 1 is the circuit diagram of a scan drive cell of scan drive circuit in the prior art；
Fig. 2 is the working timing figure of scan drive cell in the prior art；
Fig. 3 is the circuit diagram of the first embodiment of a scan drive cell of the scan drive circuit of the present invention；
Fig. 4 is the working timing figure of double drives of the scan drive cell of Fig. 3；
Fig. 5 is the interleaved working timing figure of the scan drive cell of Fig. 3；
Fig. 6 is the software emulation result figure of double drives of the scan drive cell of Fig. 3；
Fig. 7 is the interleaved software emulation result figure of the scan drive cell of Fig. 3；
Fig. 8 is the second embodiment of a scan drive cell of the scan drive circuit of the present invention
Circuit diagram；
Fig. 9 is the schematic diagram of the flat display apparatus of the present invention.
Specific implementation mode
Referring to Fig. 1, being provided with several scan lines in flat display apparatus in the prior art, also just need to correspond to these
Corresponding scan drive cell is arranged in scan line, and existing each scan drive cell only drives a scan line, often sweeps
It includes input circuit 10, pull-down circuit 20, control circuit 30 and output circuit 40 to retouch driving unit, this will be so that plane display dress
Complex circuit designs in setting.It is the working timing figure of scan drive cell in the prior art please continue to refer to Fig. 2, Fig. 2.Its
In, when the high level of clock signal CK1 comes temporarily, drive signal STV controls signal by thin film transistor (TFT) T1 and T5 to pull-up
Point Q1 charges, and pull-up control signaling point Q1 is charged to high level, and capacitance C1 maintains high level；Meanwhile pulling up control signal
Point Q1 realizes that the drop-down to drop-down control signaling point P1 controls, capacitance C2 maintains low electricity by the control to thin film transistor (TFT) T3
It is flat；At this point, thin film transistor (TFT) T2 and T7 are closed；When the high level of clock signal CK3 carrys out interim, scan line Gate1
High level signal is exported, that is, produces the gate drive signal of this grade, after clock signal CK3 becomes low level, clock signal
The high level signal of CK4 arrives, at this point, thin film transistor (TFT) T4 conductings, drop-down control signaling point P1 is charged to high level, capacitance C2
Maintain high level；Later, thin film transistor (TFT) T2 and T7 conductings, pull-up control signaling point Q1 are pulled down to low level, scan line
The output signal of Gate1 is pulled down to low level, and entire circuit is in stable state, the operation principle of remaining scan drive circuit
Same as described above, details are not described herein.
Referring to Fig. 3, being the circuit of the first embodiment of a scan drive cell of the scan drive circuit of the present invention
Figure.In the present embodiment, it is only illustrated by taking a scan drive cell as an example.As shown in figure 3, the turntable driving of the present invention
Circuit includes cascade multiple scan drive cells, and each scan drive cell includes：
First input circuit 100, for receiving the first clock signal and drive signal and exporting the first input signal；
Second input circuit 500, for receiving the first clock signal and drive signal and exporting the second input signal；
Pull-down circuit 200, for receiving second clock signal and exporting pulldown signal and according to the second clock signal
Drop-down control signaling point is pulled down or charged；
First control circuit 300, for receiving first input signal from first input circuit 100 and according to institute
It states the first input signal pair first pull-up control signaling point to charge, or the drop-down is received from the pull-down circuit 200
Signal simultaneously pulls down the first pull-up control signaling point according to the pulldown signal；
Second control circuit 600, for receiving second input signal from second input circuit 500 and according to institute
It states the second input signal pair second pull-up control signaling point to charge, or the drop-down is received from the pull-down circuit 200
Signal simultaneously pulls down the second pull-up control signaling point according to the pulldown signal；
First output circuit 400 is swept for receiving third clock signal and generating first according to the third clock signal
It retouches drive signal and exports and drive pixel unit to the first scan line；And
Second output circuit 700 is swept for receiving the 4th clock signal and generating second according to the 4th clock signal
It retouches drive signal and exports and drive pixel unit to the second scan line.
Specifically, first input circuit 100 includes the first controllable switch T1, the control of the first controllable switch T1
End receives first clock signal, and the first end of the first controllable switch T1 receives the drive signal, and described first can
The second end for controlling switch T1 connects the pull-down circuit 200 and the first control circuit 300.
The pull-down circuit 200 includes the second to the 8th controllable switch T2-T8 and the first capacitance C1, and described second controllably opens
The control terminal for closing T2 connects the second end of the first controllable switch T1, the first end of the third controllable switch T3 and described the
One control circuit 300, the first end of the second controllable switch T2, which receives, closes voltage end signal VGL, and described second controllably opens
The second end for closing T2 connects the control terminal of the third controllable switch T3, the control terminal of the 4th controllable switch T4, described the
The control terminal of seven controllable switch T7, the control terminal of the 8th controllable switch T8, the first end of the 5th controllable switch T5 and
The second end of the second end of the 6th controllable switch T6, the third controllable switch T3 connects the 4th controllable switch T4's
The first end of first end, the second end of the 7th controllable switch T7 and the 8th controllable switch T8, the described 4th controllably opens
The second end for closing T4 connects the control terminal of the 5th controllable switch T5, second input circuit 500 and second control
The second end of circuit 600, the 5th controllable switch T5 receives the closing voltage end signal VGL, the 6th controllable switch
The control terminal of T6 receives the second clock signal, and the first end of the 6th controllable switch T6 receives cut-in voltage end signal
The first end of VGH, the 7th controllable switch T7 connects first output circuit 400, and the of the 8th controllable switch T8
Two ends connect second output circuit 700, the first capacitance C1 be connected to the first end of the 6th controllable switch T6 with
Between second end.
The first control circuit 300 includes the 9th controllable switch T9, and the control terminal of the 9th controllable switch T9 receives
The cut-in voltage end signal VGH, the first end of the 9th controllable switch T9 connect the control of the second controllable switch T2
The second end of the first end of end and the third controllable switch T3, the 9th controllable switch T9 connects first output circuit
400。
First output circuit 400 includes the tenth controllable switch T10 and the second capacitance C2, the tenth controllable switch
The control terminal of T10 connects the second end of the 9th controllable switch T9, described in the first end of the tenth controllable switch T10 receives
The second end of third clock signal, the tenth controllable switch T10 connects first scan line and the 7th controllable switch
The first end of T7, the second capacitance C2 are connected between the control terminal and second end of the tenth controllable switch T10.
Second input circuit 500 includes the 11st controllable switch T11, the control of the 11st controllable switch T11
End reception first clock signal, the first end reception drive signal of the 11st controllable switch T11, the described tenth
The second end of one controllable switch T11 connects the control terminal of the 5th controllable switch T5.
The second control circuit 600 includes the 12nd controllable switch T12, the control of the 12nd controllable switch T12
End receives the cut-in voltage end signal VGH, and the first end of the 12nd controllable switch T12 connects the 4th controllable switch
The control terminal of the second end of T4 and the 5th controllable switch T5, the 12nd controllable switch T12 second end connection described in
Second output circuit 700.
Second output circuit 700 includes the 13rd controllable switch T13 and third capacitance C3, and the described 13rd controllably opens
The control terminal for closing T13 connects the second end of the 12nd controllable switch T12, the first end of the 13rd controllable switch T13
Connect second scan line and the second end of the 8th controllable switch T8, the second end of the 13rd controllable switch T13
The 4th clock signal is received, the third capacitance C3 is connected to the control terminal and first of the 13rd controllable switch T13
Between end.
In the present embodiment, the described first to the 13rd controllable switch T1-T13 be N-type TFT, described first to
Control terminal, first end and the second end of 13rd controllable switch T1-T13 corresponds to the grid of the N-type TFT, leakage respectively
Pole and source electrode.
Specifically, first clock signal is the first clock signal CK1, and the second clock signal is believed for second clock
Number CK4, the third clock signal are third clock signal CK2, and the 4th clock signal is the 4th clock signal CK3, institute
It is pull-up control signaling point Q1 to state the first pull-up control signaling point, and the second pull-up control signaling point is pull-up control signaling point
Q2, drop-down control signaling point are drop-down control signaling point P12, and drive signal is drive signal STV, and the first scan line is scan line
Gate1, the second scan line are scan line Gate2.
Fig. 4 to Fig. 7 is please referred to, is the working timing figure and software emulation figure of scan drive circuit of the present invention.Extremely according to Fig. 4
The operation principle that Fig. 7 can obtain the scan drive circuit is as follows：It is illustrated by taking a scan drive cell as an example below.
When the high level of the first clock signal CK1 comes temporarily, the first controllable switch T1 and the second controllable switch T2 conductings, the 9th controllably opens
The control terminal for closing T9 receives always the high level of cut-in voltage end signal VGH and in the conduction state, and drive signal STV is logical at this time
It crosses T9 couples first pull-up control signaling point Q1 of the first controllable switch T1 and the 9th controllable switch to charge, the first pull-up control letter
Number point Q1 is charged to high level, and the second capacitance C2 maintains high level；When the high level of the first clock signal CK1 come it is interim,
11st controllable switch T11 and the 5th controllable switch T5 conductings, the control terminal of the 12nd controllable switch T12 receive always unlatching electricity
The high level of pressure side signal VGH and it is in the conduction state, drive signal STV can by the 11st controllable switch T11 and the 12nd
T12 couples second pull-up control signaling point Q2 of control switch charges, and the second pull-up control signaling point Q2 is charged to high level, third
Capacitance C3 maintains high level.When the low level of second clock signal CK4 is come temporarily, the 6th controllable switch T6 ends, because second
Controllable switch T2 and the 5th controllable switch T5 is in conducting state, the first pull-up control signaling point Q1, the second pull-up control letter
Number point Q2 and drop-down control signaling point P12 are pulled down to low level, and the first capacitance C1 maintains low level, at this point, third is controllable
Switch T3, the 7th controllable switch T7, the 4th controllable switch T4 and the 8th controllable switch T8 control terminal receive low level signal
And end.
When the high level of third clock signal CK2 comes temporarily, because the tenth controllable switch T10 is in the conduction state, therefore
First scan line Gate1 exports high level signal, that is, produces the gate drive signal of the first order and be supplied to corresponding pixel
Unit；When the high level of the 4th clock signal CK3 come it is interim because the 13rd controllable switch T13 is in the conduction state, therefore the
Two scan line Gate2 export high level signal, that is, produce the corresponding pixel unit of gate drive signal of the second level.
When the high level of second clock signal CK4 comes interim, the 6th controllable switch T6 conductings, drop-down control signaling point P12
It is charged to high level, the first capacitance C1 maintains high level；Later, third controllable switch T3, the 7th controllable switch T7, the 4th controllable
The control terminal of switch T4 and the 8th controllable switch T8 receive high level signal and are connected, the first pull-up control signaling point Q1 and the
Two pull-up control signaling point Q2 are pulled down to low level and stablize in low level, the first scan line Gate1 and the second scan line
The scanning drive signal of Gate2 outputs is pulled down to low level and is supplied to corresponding pixel unit, at this point, the turntable driving
Cell operation terminates, and entire circuit is in stable state.The operation principle of remaining scan drive cell is same as described above, herein not
It repeats again.
Referring to Fig. 8, being the circuit of the second embodiment of a scan drive cell of the scan drive circuit of the present invention
Figure.It is in place of the second embodiment of the scan drive cell and the difference of the first embodiment of above-mentioned scan drive cell：
Described first to the 13rd controllable switch T1-T13 is P-type TFT, the described first to the 13rd controllable switch T1-T13
Control terminal, first end and second end correspond to grid, drain electrode and the source electrode of the P-type TFT respectively.In other implementations
In example, the described first to the 13rd controllable switch is alternatively other kinds of switch, as long as can achieve the object of the present invention.
Referring to Fig. 9, for a kind of schematic diagram of flat display apparatus of the present invention.The flat display apparatus includes above-mentioned
Scan drive circuit, the scan drive circuit are arranged in the both ends of the flat display apparatus, the flat display apparatus
Other devices and function in existing flat display apparatus device and function it is identical, details are not described herein.Wherein, described flat
Flat-panel display device is LCD or OLED.
The scan drive circuit of the present invention is by first and second input circuit and first and second control circuit come to the
One and second pull-up control signaling point charge, and realized to drop-down control signaling point by the way that pull-down circuit is arranged
Drop-down control, exports first and second scanning drive signal by first and second output circuit and is respectively supplied to first and second
Scan line drives corresponding pixel unit, and the circuit of simplified flat display apparatus is realized with this, saves space, and then conducive to flat
The narrow frame design of flat-panel display device.
Mode the above is only the implementation of the present invention is not intended to limit the scope of the invention, every to utilize this
Equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field is included within the scope of the present invention.
Claims (8)
1. a kind of scan drive circuit, which is characterized in that the scan drive circuit includes cascade multiple scan drive cells,
Each scan drive cell includes：
First input circuit, for receiving the first clock signal and drive signal and exporting the first input signal；
Second input circuit, for receiving the first clock signal and drive signal and exporting the second input signal；
Pull-down circuit, for receiving second clock signal and exporting pulldown signal and according to the second clock signal to drop-down control
Signaling point processed is pulled down or is charged；
First control circuit, for receiving first input signal from first input circuit and being inputted according to described first
The pull-up control signaling point of signal pair first charges, or from the pull-down circuit reception pulldown signal and according to described
Pulldown signal pulls down the first pull-up control signaling point；
Second control circuit, for receiving second input signal from second input circuit and being inputted according to described second
The pull-up control signaling point of signal pair second charges, or from the pull-down circuit reception pulldown signal and according to described
Pulldown signal pulls down the second pull-up control signaling point；
First output circuit, for receiving third clock signal and generating the first turntable driving letter according to the third clock signal
Number output drives pixel unit to the first scan line；And
Second output circuit, for receiving the 4th clock signal and generating the second turntable driving letter according to the 4th clock signal
Number output drives pixel unit to the second scan line；
First input circuit includes the first controllable switch, and the control terminal of first controllable switch receives first clock
The first end of signal, first controllable switch receives the drive signal, and the second end of first controllable switch connects institute
State pull-down circuit and the first control circuit；
The pull-down circuit includes the second to the 8th controllable switch and the first capacitance, and the control terminal of second controllable switch connects
The second end of first controllable switch, the first end of the third controllable switch and the first control circuit, described second
The first end of controllable switch, which receives, closes voltage end signal, and the second end of second controllable switch connects the third and controllably opens
The control terminal of pass, the control terminal of the 4th controllable switch, the control terminal of the 7th controllable switch, the 8th controllable switch
Control terminal, the first end of the 5th controllable switch and the second end of the 6th controllable switch, the third controllable switch
Second end connect the first end of the 4th controllable switch, the second end of the 7th controllable switch and the described 8th controllably open
The first end of pass simultaneously receives the closing voltage end signal, and the second end connection the described 5th of the 4th controllable switch is controllably opened
The second end of the control terminal of pass, second input circuit and the second control circuit, the 5th controllable switch receives institute
It states and closes voltage end signal, the control terminal of the 6th controllable switch receives the second clock signal, and the described 6th controllably opens
The first end of pass receives cut-in voltage end signal, and the first end of the 7th controllable switch connects first output circuit, institute
The second end for stating the 8th controllable switch connects second output circuit, and first capacitance connection is in the 6th controllable switch
First end and second end between.
2. scan drive circuit according to claim 1, which is characterized in that the first control circuit includes the 9th controllable
The control terminal of switch, the 9th controllable switch receives the cut-in voltage end signal, the first end of the 9th controllable switch
Connect the control terminal of second controllable switch and the first end of the third controllable switch, the second of the 9th controllable switch
End connects first output circuit.
3. scan drive circuit according to claim 2, which is characterized in that first output circuit includes the tenth controllable
Switch and the second capacitance, the control terminal of the tenth controllable switch connect the second end of the 9th controllable switch, and the described tenth
The first end of controllable switch receives the third clock signal, second end connection first scanning of the tenth controllable switch
The first end of line and the 7th controllable switch, control terminal and second of second capacitance connection in the tenth controllable switch
Between end.
4. scan drive circuit according to claim 3, which is characterized in that second input circuit can including the 11st
Control switch, the control terminal of the 11st controllable switch receive first clock signal, and the of the 11st controllable switch
One end receives the drive signal, and the second end of the 11st controllable switch connects the control terminal of the 5th controllable switch.
5. scan drive circuit according to claim 4, which is characterized in that the second control circuit can including the 12nd
The control terminal of control switch, the 12nd controllable switch receives the cut-in voltage end signal, the 12nd controllable switch
First end connects the second end of the 4th controllable switch and the control terminal of the 5th controllable switch, and the described 12nd controllably opens
The second end of pass connects second output circuit.
6. scan drive circuit according to claim 5, which is characterized in that second output circuit can including the 13rd
Control switch and third capacitance, the control terminal of the 13rd controllable switch connect the second end of the 12nd controllable switch, institute
The first end for stating the 13rd controllable switch connects second scan line and the second end of the 8th controllable switch, and the described tenth
The second end of three controllable switches receives the 4th clock signal, and the third capacitance connection is in the 13rd controllable switch
Between control terminal and first end.
7. scan drive circuit according to claim 6, which is characterized in that the described first to the 13rd controllable switch is N
Type thin film transistor (TFT), it is thin that control terminal, first end and the second end of the described first to the 13rd controllable switch correspond to the N-type respectively
Grid, drain electrode and the source electrode of film transistor；Or the described first to the 13rd controllable switch be P-type TFT, described the
Control terminal, first end and the second end of one to the 13rd controllable switch correspond to the grid of the P-type TFT, drain electrode respectively
And source electrode.
8. a kind of flat display apparatus, which is characterized in that the flat display apparatus includes as described in claim 1-7 is any
Scan drive circuit.
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| CN201610717822.0A CN106098016B (en) | 2016-08-24 | 2016-08-24 | Scan drive circuit and flat display apparatus with the circuit |
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| CN201610717822.0A CN106098016B (en) | 2016-08-24 | 2016-08-24 | Scan drive circuit and flat display apparatus with the circuit |
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| CN106098016B true CN106098016B (en) | 2018-10-23 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106486078B (en) * | 2016-12-30 | 2019-05-03 | 深圳市华星光电技术有限公司 | A kind of scan drive circuit, driving circuit and display device |
| CN108665837B (en) * | 2017-03-27 | 2021-07-30 | 昆山工研院新型平板显示技术中心有限公司 | Scanning driving circuit, driving method thereof and flat panel display device |
| CN106782423B (en) | 2017-03-29 | 2019-04-16 | 武汉华星光电技术有限公司 | A kind of scan drive circuit and liquid crystal display |
| CN106991973B (en) * | 2017-05-19 | 2019-01-25 | 京东方科技集团股份有限公司 | Control light emission drive circuit and display device, driving method |
| CN111477157B (en) * | 2020-05-15 | 2021-10-08 | 武汉华星光电技术有限公司 | Display driving circuit |
| CN114038412B (en) * | 2021-11-30 | 2022-12-30 | 重庆康佳光电技术研究院有限公司 | Light-emitting control signal generation circuit, light-emitting diode driving module and display panel |
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