CN106409261B

CN106409261B - GOA drive circuit

Info

Publication number: CN106409261B
Application number: CN201611069140.XA
Authority: CN
Inventors: 赵莽
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2016-11-29
Filing date: 2016-11-29
Publication date: 2020-09-04
Anticipated expiration: 2036-11-29
Also published as: CN106409261A

Abstract

The invention discloses a GOA drive circuit, comprising: the input control module is used for inputting an input transmission signal; the latch module is used for latching the input stage transmission signal; the processing module is used for processing the stage transmission signal output by the latch module into a first intermediate signal; and the buffer module is used for buffering and processing the first intermediate signal into a gate driving signal and a second intermediate signal, wherein the phases of the first intermediate signal and the second intermediate signal are opposite, the first intermediate signal and/or the second intermediate signal output by the previous-stage GOA driving circuit and the next-stage GOA driving circuit control the input control module to input the stage transmission signal, and the latch module is controlled to latch the stage transmission signal input by the input control module. The invention does not adopt the clock control signal to control the input control module, thereby effectively reducing the load generating the clock control signal and the power consumption of the circuit.

Description

GOA drive circuit

Technical Field

The invention belongs to the technical field of display control, and particularly relates to a GOA driving circuit.

Background

The GOA (Gate Driver On Array, line scan integrated On an Array substrate) is a technology for realizing line-by-line scan driving by fabricating a line scan driving signal circuit On an Array substrate by using the existing thin film transistor liquid crystal display Array process.

In the conventional design of the CMOS GOA circuit, the use of a clock control signal is not optimized too much, so that the load and power consumption for generating the clock signal are large, and the power consumption of the whole GOA circuit is difficult to reduce.

Disclosure of Invention

The invention provides a GOA driving circuit, which does not adopt a clock control signal to control an input control module, and can effectively reduce the load of generating the clock control signal and the power consumption of a circuit.

According to an embodiment of the present invention, there is provided a GOA driving circuit including:

the input control module is used for inputting an input transmission signal;

the latch module is used for latching the input stage transmission signal;

the processing module is used for processing the stage transmission signal output by the latch module into a first intermediate signal;

a buffer module for buffering and processing the first intermediate signal into a gate driving signal and a second intermediate signal, the phases of the first intermediate signal and the second intermediate signal being opposite,

the first intermediate signal and/or the second intermediate signal output by the previous-stage GOA driving circuit and the next-stage GOA driving circuit control the input control module to input the stage transmission signal, and control the latch module to latch the stage transmission signal input by the input control module.

According to one embodiment of the invention, the input control module comprises:

the first transistor is a P-type transistor, the grid electrode of the first transistor is used for inputting a first intermediate signal output by a next-stage GOA driving circuit, the source electrode of the first transistor is used for inputting a first control signal, and the drain electrode of the first transistor is connected with the latch module;

and the second transistor is an N-type transistor, the grid electrode of the second transistor is used for inputting a second intermediate signal output by the previous-stage GOA driving circuit, the source electrode of the second transistor is used for inputting a second control signal, and the drain electrode of the second transistor is connected with the latch module.

According to one embodiment of the present invention, the latch module includes:

the input end of the first inverter is connected with the drains of the first transistor and the second transistor, and the output end of the first inverter is connected with the processing module;

the third transistor is a P-type transistor, the grid electrode of the third transistor is used for inputting a second intermediate signal output by the previous-stage GOA driving circuit, and the drain electrode of the third transistor is connected with the input end of the first inverter;

the fourth transistor is an N-type transistor, the grid electrode of the fourth transistor is used for inputting the first intermediate signal output by the next-stage GOA driving circuit, and the drain electrode of the fourth transistor is connected with the source electrode of the third transistor;

and the input end of the second phase inverter is connected with the output end of the first phase inverter, and the output end of the second phase inverter is connected with the source electrode of the fourth transistor.

the first transistor is a P-type transistor, the grid electrode of the first transistor is used for inputting a first intermediate signal output by the previous-stage GOA driving circuit, the source electrode of the first transistor is used for inputting a first control signal, and the drain electrode of the first transistor is connected with the latch module;

and the second transistor is an N-type transistor, the grid electrode of the second transistor is used for inputting a second intermediate signal output by the next-stage GOA driving circuit, the source electrode of the second transistor is used for inputting a second control signal, and the drain electrode of the second transistor is connected with the latch module.

a first inverter having an input terminal connected to the drains of the first transistor and the second transistor;

the input end of the second phase inverter is connected with the output end of the first phase inverter, and the output end of the second phase inverter is connected with the processing module;

the third transistor is an N-type transistor, the grid electrode of the third transistor is used for inputting the first intermediate signal output by the previous-stage GOA driving circuit, and the drain electrode of the third transistor is connected with the input end of the first inverter;

and the fourth transistor is a P-type transistor, the grid electrode of the fourth transistor is used for inputting a second intermediate signal output by the next-stage GOA driving circuit, the drain electrode of the fourth transistor is connected with the source electrode of the third transistor, and the source electrode of the fourth transistor is connected with the output end of the second inverter.

the first transistor is an N-type transistor, the grid electrode of the first transistor is used for inputting a second intermediate signal output by the previous-stage GOA driving circuit, the source electrode of the first transistor is used for inputting a second control signal, and the drain electrode of the first transistor is connected with the latch module;

the input end of the first inverter is connected with the drain electrode of the first transistor, and the output end of the first inverter is connected with the processing module;

the fourth transistor is a P-type transistor, the grid electrode of the fourth transistor is used for inputting a second intermediate signal output by the next-stage GOA driving circuit, and the source electrode of the fourth transistor is connected with the output end of the first inverter;

and the input end of the second inverter is connected with the drain electrode of the third transistor, and the output end of the second inverter is connected with the source electrode of the fourth transistor.

and the second transistor is a P-type transistor, the grid electrode of the second transistor is used for inputting a first intermediate signal output by the previous-stage GOA driving circuit, the source electrode of the second transistor is used for inputting a first control signal, and the drain electrode of the second transistor is connected with the latch module.

the third transistor is an N-type transistor, the grid electrode of the third transistor is used for inputting a first intermediate signal output by the next-stage GOA driving circuit, and the drain electrode of the third transistor is connected with the input end of the first inverter;

the fourth transistor is an N-type transistor, the grid electrode of the fourth transistor is used for inputting the first intermediate signal output by the previous-stage GOA driving circuit, and the source electrode of the fourth transistor is connected with the output end of the first phase inverter;

and the input end of the second inverter is connected with the drain electrode of the fourth transistor, and the output end of the second inverter is connected with the source electrode of the third transistor.

In accordance with one embodiment of the present invention,

the processing module comprises a NAND gate, the first input end of the NAND gate is connected with the output end of the latch module, the second input end of the NAND gate is connected with the first time sequence driving signal, the output end of the NAND gate is connected with the cache module and outputs the first intermediate signal,

the buffer module comprises a third inverter, a fourth inverter and a fifth inverter which are connected in series, wherein,

the input end of the third phase inverter is connected with the processing module, and the output end of the third phase inverter is connected with the input end of the fourth phase inverter;

the output end of the fourth inverter is connected with the input end of the fifth inverter and outputs the second intermediate signal;

an output terminal of the fifth inverter outputs a gate driving signal,

the reset module comprises a sixth inverter and a fifth transistor connected with the sixth inverter, wherein,

the output end of the sixth inverter is connected with the output end of the cache module, and the input end of the sixth inverter is respectively connected with the drain electrode of the fifth transistor and the input end of the sixth inverter;

the source electrode of the fifth transistor introduces a first control signal, and the grid electrode introduces a reset signal.

The invention has the beneficial effects that:

the GOA driving circuit provided by the invention does not adopt a clock control signal to control the input control module, thereby effectively reducing the load for generating the clock control signal and the power consumption of the circuit.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the technical solution in the embodiments of the present invention, the drawings required in the description of the embodiments will be briefly introduced as follows:

FIG. 1 is a schematic diagram of a GOA driving circuit in the prior art;

FIGS. 2a-2c are schematic diagrams of internal structures of some of the circuit components of FIG. 1;

FIG. 3 is a timing diagram illustrating operation of the scan of FIG. 1;

FIG. 4 is a diagram of a driver circuit configuration according to one embodiment of the present invention;

fig. 5 is a configuration diagram of a driving circuit according to a first embodiment of the present invention;

fig. 6 is a structural view of a driving circuit according to a second embodiment of the present invention;

fig. 7 is a configuration diagram of a driving circuit according to a third embodiment of the present invention;

fig. 8 is a configuration diagram of a driving circuit according to a fourth embodiment of the present invention;

FIG. 9 is a schematic diagram of a driving architecture according to one embodiment of the invention;

FIG. 10 is a timing diagram of the operation of the driving circuit during scanning according to one embodiment of the present invention;

FIG. 11 is a timing diagram of simulated waveforms during scanning, according to one embodiment of the invention;

fig. 12 is a timing diagram of simulated waveforms during scanning according to another embodiment of the present invention.

Detailed Description

The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.

Fig. 1 shows a conventional CMOS GOA driver circuit in the prior art, which employs an interleaved driving manner, and the single-sided GOA driver circuit requires two clock control signal CK traces (e.g., clock control signal CK1 trace, clock control signal CK2 trace), a start signal STV trace (not shown), a RESET signal RESET trace, a high potential signal VGH trace, and a low potential signal VGL trace. As shown in fig. 1, the CMOS GOA driver circuit is mainly composed of the following parts.

The input control module 100 is used for signal input control of the GOA driving circuit, and controls a clock control inverter therein through a CK1 signal and an XCK1 signal to realize transmission of a Q-point signal of an upper stage; the latch module 200 controls the internal clock control inverter to latch the current-stage Q point signal; the RESET block 300 includes a transistor PTFT1 and an inverter IN2 for resetting a signal node IN the circuit; the processing module 400 (NAND gate NAND) for Q-point signal generates the gate driving signal of the present stage by NAND processing of CK3 signal and Q-point signal; the gate driving signal buffer processing module 500 includes three inverters IN3, IN4, IN5 connected IN series for increasing the driving capability of the gate driving signal. Wherein, Q (N) in fig. 1 represents a Q point signal of the nth stage GOA driving circuit, and the Q point is a point for controlling the output of the gate driving signal; p (N) denotes a P point signal of the nth stage GOA driver circuit, which is a point for controlling the hold circuit to stably output during the period in which the circuit is inactive. The CK1 signal is inverted by an inverter IN1 to obtain the XCK1 signal. Q (N-1) is a stage transmission signal of the Nth-stage GOA driving circuit.

Fig. 2a-2c are equivalent circuit diagrams of some components in the CMOS GOA driver circuit in fig. 1, where fig. 2a is an equivalent circuit corresponding to each inverter in fig. 1, fig. 2b is an equivalent circuit corresponding to the clocked inverter in fig. 1, and fig. 2c is an equivalent circuit corresponding to the nand gate in fig. 1.

Fig. 3 is an operation timing diagram of the GOA driving circuit shown in fig. 1, and as can be seen from the analysis of fig. 3, the operation principle of the circuit shown in fig. 1 is as follows: before a stage transmission signal Q (N-1) is input, all GOA driving circuits are reset, Q nodes of all the circuits are reset to be low level, and a grid driving signal is low level; when the Q point signal of the previous stage and the high level pulse signal of the CK1 signal inputted to the control input of the present stage come at the same time, the point Q (n) is charged to the high level, and when the CK1 signal inputted to the control input becomes the low level, the latch module 200 latches the high level signal of the point Q (n); when the high-level pulse signal of the control CK3 signal of the NAND gate comes, the GATE (n) signal outputs a high-level signal, namely, a grid driving signal of the stage is generated; when the high pulse signal of the CK1 signal is input again, the point q (n) is charged to low level, and then the point q (n) latches and inputs the low signal, and the gate (n) signal maintains a stable low output.

As can be seen from the above analysis, the conventional cmos GOA driving circuit input control module 100 requires the CK1 signal for control, and the circuit and load thereof for generating the CK1 signal are consumed more, so that the power consumption of the entire GOA circuit is difficult to reduce.

Therefore, the present invention provides a GOA driving circuit, which input control module 100 does not need CK1 signal for control, effectively reducing the load and power consumption of the circuit for generating CK1 signal. Referring to fig. 4, a structure of a GOA driving circuit according to an embodiment of the present invention is shown, and the present invention will be described in detail with reference to fig. 4.

The GOA driving circuit includes an input control module 21, a latch module 22, a processing module 23, and a buffer module 24. The input control module 21 is used for inputting an input transmission signal; the latch module 22 is used for latching the input stage transmission signal; the processing module 23 is configured to process the stage signal output by the latch module into a first intermediate signal; the buffer module 24 is configured to buffer and process the first intermediate signal into a gate driving signal and a second intermediate signal, where the phases of the first intermediate signal and the second intermediate signal are opposite, where the first intermediate signal and/or the second intermediate signal output by the previous-stage GOA driving circuit and the next-stage GOA driving circuit control the input control module 21 to input the stage transmission signal, and control the latch module 22 to latch the stage transmission signal input by the input control module 21.

According to the GOA driving circuit provided by the invention, the latch module 22 and the input control module 21 are not controlled by clock control signals, so that the load for generating the clock control signals and the power consumption of the circuit are effectively reduced.

According to an embodiment of the present invention, the input control module 21 includes a first transistor T11 and a second transistor T12, as shown in fig. 5. The first transistor T11 is a P-type transistor having a gate for inputting the first intermediate signal XP ((N +1) outputted by the next-stage GOA driver, a source for inputting the first control signal VGH, and a drain connected to the latch module 22. the second transistor T12 is an N-type transistor having a gate for inputting the second intermediate signal P ((N-1) outputted by the previous-stage GOA driver, a source for inputting the second control signal VGL, and a drain connected to the latch module 22. the GOA driver shown in fig. 5 has no clock-controlled inverter module in the conventional cmos GOA circuit, and the input control module does not use the CK1 signal for control, and directly uses the first intermediate signal of the previous stage and the second intermediate signal of the next stage to respectively pull up and pull down the Q point of the current stage.

As shown in fig. 5, the Q-point signal of the present stage is subjected to a pull-up process by using T12, T13 and P (N-1) signals, a T12 transistor is used for transmission of the Q-point signal, a T13 transistor is used for switching control of a latch loop, and P (N-1) is a second intermediate signal of a GOA circuit of the previous stage and is used for switching control of T12 and T13 transistors. The Q point signal of the current stage is subjected to pull-down processing by utilizing T11, T14 and XP (N +1) signals, a T11 transistor is used for transmission of a low-level signal of the Q point signal, a T14 transistor is used for switching control of a latch loop, and XP (N +1) is a first intermediate signal of a GOA circuit of the next stage. The circuit shown in fig. 5 can reduce the loss of the threshold voltage Vth of the transmission signal by transferring the VGH signal by using PTFT and transferring the VGL signal by using NTFT.

According to one embodiment of the present invention, the latch module includes a first inverter IN11, a second inverter IN12, a third transistor T13, and a fourth transistor T14, as shown IN fig. 5. The input end of the first inverter IN11 is connected with the drains of the first transistor T11 and the second transistor T12, and the output end is connected with the processing module 23; the third transistor T13 is a P-type transistor, the gate thereof is used for inputting the second intermediate signal P (N-1) output by the previous-stage GOA driving circuit, and the drain thereof is connected to the input terminal of the first inverter IN 11; the fourth transistor T14 is an N-type transistor, and has a gate for inputting the first intermediate signal XP (N +1) output by the next-stage GOA driving circuit, and a drain connected to the source of the third transistor T13; the second inverter IN12 has an input terminal connected to the output terminal of the first inverter IN11 and an output terminal connected to the source of the fourth transistor T14.

According to an embodiment of the present invention, the input control module includes a first transistor T21 and a second transistor T22, as shown in fig. 6. The first transistor T21 is a P-type transistor having a gate for inputting the first intermediate signal XP (N-1) output by the previous GOA driver, a source for inputting the first control signal VGH, and a drain connected to the latch module 23. the second transistor T22 is an N-type transistor having a gate for inputting the second intermediate signal P (N +1) output by the next GOA driver, a source for inputting the second control signal VGL, and a drain connected to the latch module 23.

According to one embodiment of the present invention, the latch module includes a first inverter IN21, a second inverter IN22, a third transistor T23, and a fourth transistor T24, as shown IN fig. 6. An input terminal of the first inverter IN21 is connected to the drains of the first transistor T11 and the second transistor T12; the input end of the second inverter IN22 is connected with the output end of the first inverter IN21, and the output end is connected with the processing module 23; the third transistor T23 is a P-type transistor, the gate of which is used for inputting the second intermediate signal P (N +1) output by the next-stage GOA driving circuit, and the drain of which is connected to the output terminal of the second inverter IN 22; the fourth transistor T24 is an N-type transistor, and has a gate for inputting the first intermediate signal XP (N-1) output by the previous-stage GOA driving circuit, a drain connected to the source of the third transistor T23, and a source connected to the input terminal of the first inverter IN 21.

As can be seen from fig. 5 and 6, the third transistor and the fourth transistor are used for switching control of the latch loop in the latch module. As shown IN fig. 5, the latch circuit is composed of a first inverter IN11, a second inverter IN12, a third transistor T13, and a fourth transistor T14. When the stage signal reaches the latch module through the first transistor T11 or the second transistor T12, the second intermediate signal P (N-1) output by the previous stage of the GOA driving circuit is at a low level, the first intermediate signal XP (N +1) output by the next stage of the GOA driving circuit is at a high level and a low level, at this time, the third transistor T13 and the fourth transistor T14 are turned on, and the stage signal is stored in the latch loop. As shown IN fig. 6, the latch circuit is composed of a first inverter IN21, a second inverter IN22, a third transistor T23, and a fourth transistor T24. When the stage signal reaches the latch module through the first transistor T21 or the second transistor T22, the first intermediate signal XP (N-1) output by the previous stage of GOA driving circuit is at a high level, the second intermediate signal P (N +1) output by the next stage of GOA driving circuit is at a low level, at this time, the third transistor T23 and the fourth transistor T24 are turned on, and the stage signal is stored in the latch loop. In the invention, the latch module is not controlled by a clock control signal, so that the load for generating the clock control signal and the power consumption of a circuit can be effectively reduced.

According to an embodiment of the present invention, the input control module includes a first transistor T31 and a second transistor T32, as shown in fig. 7. The first transistor T31 is an N-type transistor, the gate of the first transistor is used for inputting the second intermediate signal P (N-1) output by the previous-stage GOA driving circuit, the source of the first transistor is used for inputting the second control signal VGL, and the drain of the first transistor is connected to the latch module 22; the second transistor T32 is an N-type transistor, and has a gate for inputting the second intermediate signal P (N +1) output by the next-stage GOA driving circuit, a source for inputting the second control signal VGL, and a drain connected to the latch module 22.

According to one embodiment of the present invention, the latch module includes a first inverter IN31, a second inverter IN32, a third transistor T33, and a fourth transistor T34, as shown IN fig. 7. The input end of the first inverter IN31 is connected with the drain electrode of the first transistor T31, and the output end is connected with the processing module; the third transistor T33 is a P-type transistor having a gate for inputting the second intermediate signal P (N-1) outputted from the previous-stage GOA driving circuit, a drain connected to the input terminal of the first inverter IN31, the fourth transistor T34 is a P-type transistor having a gate for inputting the second intermediate signal P (N +1) outputted from the next-stage GOA driving circuit, a source connected to the output terminal of the first inverter IN31, an output terminal of the second inverter IN32 connected to the source of the third transistor T33, and an input terminal connected to the drain of the fourth transistor T34.

As shown in fig. 7, the Q-point signal of the present stage is pulled down by T32, T34 and P (N +1) signals, the T32 transistor is used for transmission of the Q-point signal, the T34 transistor is used for switching control of the latch loop, and P (N +1) is a second intermediate signal of the next stage GOA circuit and used for switching control of the T32 and T34 transistors. The Q point signal of the stage is pulled down by T31, T33 and P (N-1) signals, a T31 transistor is used for transmitting a low level signal of the Q point signal, and a T33 transistor is used for switching control of a latch loop. The circuit shown in fig. 7 uses NTFT to transmit the VGL signal, so that the threshold voltage Vth loss of the transmission signal can be reduced.

According to an embodiment of the present invention, the input control module includes a first transistor T41 and a second transistor T42, as shown in fig. 8. The first transistor T41 is a P-type transistor, and has a gate for inputting the first intermediate signal XP (N +1) output by the next GOA driver, a source for inputting the first control signal VGH, and a drain connected to the latch module 22. The second transistor T42 is a P-type transistor, and has a gate for inputting the first intermediate signal P (N-1) output by the previous-stage GOA driving circuit, a source for inputting the first control signal VGH, and a drain connected to the latch module 22.

According to one embodiment of the present invention, the latch module includes a first inverter IN41, a second inverter IN42, a third transistor T43, and a fourth transistor T44, as shown IN fig. 8. The input end of the first inverter IN41 is connected with the drain of the first transistor T41, and the output end is connected with the processing module 23; the third transistor T43 is an N-type transistor, and has a gate for inputting the first intermediate signal XP (N +1) output by the next-stage GOA driving circuit, and a drain connected to the input terminal of the first inverter IN 41; the fourth transistor T44 is an N-type transistor, and has a gate for inputting the first intermediate signal XP (N-1) output by the previous-stage GOA driver circuit, and a drain connected to the output terminal of the first inverter IN 41; the second inverter IN42 has an input terminal connected to the drain of the fourth transistor T44 and an output terminal connected to the source of the third transistor T43.

As can be seen from fig. 7 and 8, the third transistor and the fourth transistor are used for switching control of the latch loop in the latch module. As shown IN fig. 7, the latch circuit is composed of a first inverter IN31, a second inverter IN32, a third transistor T33, and a fourth transistor T34. When the stage signal reaches the latch module through the first transistor T31 or the second transistor T32, the second intermediate signal P (N-1) output by the previous stage of the GOA driving circuit is at a low level, the second intermediate signal P (N +1) output by the next stage of the GOA driving circuit is at a low level, and at this time, the third transistor T33 and the fourth transistor T34 are turned on, and the stage signal is stored in the latch loop. As shown IN fig. 8, the latch circuit is composed of a first inverter IN41, a second inverter IN42, a third transistor T43, and a fourth transistor T44. When the stage signal reaches the latch module through the first transistor T41 or the second transistor T42, the first intermediate signal XP (N-1) output by the previous stage of GOA driving circuit is at a high level, the first intermediate signal XP (N +1) output by the next stage of GOA driving circuit is at a low level, at this time, the third transistor T43 and the fourth transistor T44 are turned on, and the stage signal is stored in the latch loop. In the invention, the latch module is not controlled by a clock control signal, so that the load for generating the clock control signal and the power consumption of a circuit can be effectively reduced.

According to an embodiment of the present invention, the processing module 23 includes a NAND gate NAND having a first input terminal connected to the output terminal of the latch module, a second input terminal connected to the first timing driving signal CK3, and an output terminal connected to the buffer module and outputting the first intermediate signal p (n) of the present stage, as shown in fig. 5-8.

According to one embodiment of the present invention, the buffer module 24 comprises a third inverter IN23, a fourth inverter IN24, and a fifth inverter IN25 connected IN series, wherein the input terminal of the third inverter IN23 is connected to the processing module, and the output terminal is connected to the input terminal of the fourth inverter IN 24; the output terminal of the fourth inverter IN24 is connected to the input terminal of the fifth inverter IN25 and outputs a second intermediate signal; the output terminal of the fifth inverter IN25 outputs the gate drive signal as shown IN fig. 5-8.

According to an embodiment of the present invention, the reset module includes a sixth inverter IN26 and a fifth transistor T25 connected to the sixth inverter IN26, wherein an output terminal of the sixth inverter IN26 is connected to an output terminal of the buffer module, and input terminals are respectively connected to a drain of the fifth transistor T25 and an input terminal of the sixth inverter IN 26; the source of the fifth transistor T25 introduces the first control signal and the gate introduces the reset signal.

Fig. 9 is a driving frame diagram of the circuits shown in fig. 5-8, which is a single-side driving frame diagram corresponding to odd-numbered scan lines, wherein the single-side GOA circuit requires two STV signal traces for pulling up the Q point of the first-stage GOA circuit and for pulling down the Q point of the last-stage GOA circuit; one side needs two CK signal routing lines for generating a grid shift driving signal; one side needs a RESET wire for RESET processing of each level of GOA circuit; one VGH routing line and one VGL routing line are needed on a single side, and the single side is used for driving the CMOS GOA circuit.

As shown in fig. 10, which is a timing diagram of the scanning driving of the driving frame shown in fig. 9, it can be known from the timing diagram analysis that the working principle of the GOA circuit provided in this patent is as follows: when a low-level pulse signal of the RESETt signal comes, all GOA circuits carry out reset processing, and a low-level signal is latched after a Q point is reset; when an XP0 low-level pulse or a P0 high-level pulse signal comes, a Q point is charged to a high level, and then the Q point latches the high-level signal; when a high-level pulse of the CK3 signal arrives, a first intermediate signal XP1 of the current stage is generated; the first intermediate signal XP1 at the current stage is processed into a GATE driving signal GATE1 at the current stage by a cache module; when a low-level pulse of XP2 activates a high-level pulse signal of P2, a point Q is charged to a low level, and then the point Q always latches a low-level signal, so that the GOA circuit stably outputs a low-level gate driving signal.

Fig. 11 is a simulation diagram of a first scan driving according to an embodiment of the present invention, and fig. 12 is a simulation diagram of a second scan driving according to an embodiment of the present invention, and it can be seen from fig. 11 and 12 that the circuit of the present invention can realize a forward or reverse output scan signal.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A GOA driver circuit, comprising:

the input control module is used for inputting an input transmission signal;

the latch module is used for latching the input stage transmission signal;

the first intermediate signal and/or the second intermediate signal output by the previous-stage GOA driving circuit and the next-stage GOA driving circuit control the input control module to input the stage transmission signal and control the latch module to latch the stage transmission signal input by the input control module, so that the latch module and the input control module are not controlled by a clock control signal, and the load for generating the clock control signal and the power consumption of the circuit are reduced;

the first or second intermediate signal of the previous-stage GOA driving circuit is used for controlling the input control module to pull up the stage signaling signal, and the first or second intermediate signal of the next-stage GOA driving circuit is used for controlling the input control module to pull down the stage signaling signal.

2. The circuit of claim 1, wherein the input control module comprises:

3. The circuit of claim 2, wherein the latch module comprises:

4. The circuit of claim 1, wherein the input control module comprises:

5. The circuit of claim 4, wherein the latch module comprises:

6. The circuit of claim 1, wherein the input control module comprises:

the first transistor is an N-type transistor, the grid electrode of the first transistor is used for inputting a second intermediate signal output by the previous-stage GOA driving circuit, the source electrode of the first transistor is used for inputting a second control signal, and the drain electrode of the first transistor is connected with the latch module:

7. The circuit of claim 6, wherein the latch module comprises:

8. The circuit of claim 1, wherein the input control module comprises:

9. The circuit of claim 8, wherein the latch module comprises:

10. The circuit of claim 1,

an output terminal of the fifth inverter outputs a gate driving signal,