CN106357260A - Multi-input-data-state parallel detecting circuit - Google Patents
Multi-input-data-state parallel detecting circuit Download PDFInfo
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- CN106357260A CN106357260A CN201610814292.1A CN201610814292A CN106357260A CN 106357260 A CN106357260 A CN 106357260A CN 201610814292 A CN201610814292 A CN 201610814292A CN 106357260 A CN106357260 A CN 106357260A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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Abstract
The invention discloses a multi-input-data-state parallel detecting circuit. The multi-input-data-state parallel detecting circuit comprises detecting branches which are in one-to-one correspondence to a plurality of data input interfaces; each detecting branch comprises a biasing circuit and two threshold value comparing units; each biasing circuit comprises two resistors which are in series connection; a node positioned between the two resistors of each biasing circuit is connected with the corresponding data input interface and is respectively connected with first input ends of the two corresponding threshold value comparing units; second input ends of the two threshold value comparing units of each biasing circuit are respectively connected with a threshold value input interface; output ends of the two threshold value comparing units of each biasing circuit are connected with two input ends of a gate circuit in a one-to-one correspondence manner; and an output end of each gate circuit is connected with an input end of an and gate. Input voltage signals of the data input interfaces are compared respectively, whether input data of the data input interfaces are simultaneously valid or not is judged according to output data of the and gate, and therefore, parallel detection to validness of the input data of the data input interfaces is realized.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly, to a kind of multi input data mode parallel detection circuit.
Background technology
Since mankind's nineteen forty-seven invention transistor, between more than 50 year, semiconductor technology experienced silicon transistor, integrated electricity
The several generations such as road, super large-scale integration, very large scale integration, development speed is that other industries are unexistent soon；In
Central processor refers to the part that computer-internal is processed to data and processing procedure is controlled, and collects along with extensive
Become the developing rapidly of circuit engineering, integrated chip density more and more higher, cpu can integrated on a semiconductor chip in a, this
There are the LSI devices of central processing unit function, be collectively referred to as " microprocessor "；Either videocorder, intelligence are washed
The household appliances such as clothing machine, mobile phone, or car engine controls, and Digit Control Machine Tool, guided missile precise guidance etc. will embed
All kinds of different microprocessors；Microprocessor is not only the core component of microcomputer, is also various digital intelligent equipment
Critical component.
And interface chip, it is for connecting a kind of electronic devices and components between microprocessor and memorizer, it includes number
According to the data buffer of temporary buffering or bus buffer, provide bus driver of larger driving force etc. for address signal
Deng in brief, interface chip is for ensuring that safety and the stability of data transmission procedure.
However, during data transfer, the input interface of interface chip can cannot determine interface because of loose contact
Effectively whether, now, the output interface of interface chip but still can export the determination signal of " 0 " or " 1 " to the input data of chip,
And by the middle of its signal transmission to microprocessor；However, due to the loose contact of input interface, making the input data of interface chip
Real data can not be reflected, thus leading to the output data of interface chip to be nonsensical.How to obtain interface chip
The effectiveness of upper input data, thus deciding whether to accept and believe the output data on interface chip, becomes for people's research
Individual problem.
In digital circuit, digital circuit typically has three kinds of output states, is high level, low level and high-impedance state, wherein
High level is logical one, and low level is logical zero, and high-impedance state is equivalent to cut-off state；Wherein by logical one and logical zero group
The binary signal becoming, is the major way of current electronic chip data transfer inside, and if the input interface of interface chip
Vacantly or in the case of loose contact, high-impedance state will be formed, be based on this, if can be carried out by the input of docking port chip
The test of high-impedance state, to obtain the effectiveness of input data on interface chip, thus avoiding judging whether output data has
The technical problem of effect.
Therefore, it is necessary to provide a kind of input energy to detect the circuit of input data effectiveness.
Content of the invention
The present invention provides a kind of multi input data mode parallel detection circuit for solving the above problems, by multiple data
The input voltage signal of input interface is respectively compared, and judges multiple Data Input Interfaces according to the output data with door
Whether whether input data all effective, it is achieved thereby that effectively examining parallel to the input data of multiple Data Input Interfaces
Survey.
For achieving the above object, reach the effect above, the present invention is achieved through the following technical solutions:
A kind of multi input data mode parallel detection circuit, this testing circuit includes one-to-one with multiple Data Input Interfaces
Detection branch；This detection branch includes biasing circuit, the first threshold values comparing unit, the second threshold values comparing unit；Wherein biased electrical
Road includes the resistance of two series connection, and the node between two resistance is connected with Data Input Interface, connects Data Input Interface
Node is connected with the first input end of the first threshold values comparing unit, the second threshold values comparing unit；First threshold values comparing unit, second
Second input of threshold values comparing unit is connected with a threshold values input interface respectively, the first threshold values comparing unit, the second threshold values
The outfan of comparing unit is connected one to one with the two of gate circuit inputs, the output of the gate circuit in each detection branch
End be connected to one with the input of door on, judge that the input data of Data Input Interface is according to the fan-out of door evidence
No effective.
As preferred, gate circuit is same OR gate or XOR gate.
As preferred, in order to detect that circuit output state is high level, low level or high-impedance state, threshold values input interface
Include high threshold values input interface, low valve valve input interface, the second input of the first threshold values comparing unit is connected high threshold values
Input interface, the second input of the second threshold values comparing unit connects low valve valve input interface, from high threshold values input interface, low valve
Value input interface uploads the benchmark being input into the high and low level voltage threshold values coming as comparator.
As preferred, the outfan of the first threshold values comparing unit or the second threshold values comparing unit is selected one and is connect with data output
Mouth connects, and will input data be transferred in next stage circuit.
As preferred, when input data is effective, the next stage circuit being connected with this circuit will continue to gather this data
Signal；When input data is invalid, the next stage circuit being connected with this circuit will stop gathering this data signal.
As preferred, because the span of high and low level is extreme for two, so the biasing circuit producing takes centre
During value scheme preferably, so make two resistance resistance equal, and so that one of resistance is connected with power supply, another resistance and
Ground connects, so that the bias voltage that intermediate node produces is the intermediate value of circuit voltage.
As preferred, the first threshold values comparing unit, the first input end of the second threshold values comparing unit are in-phase end, first
Threshold values comparing unit, the second input of the second threshold values comparing unit are end of oppisite phase, i.e. the first threshold values comparing unit, the second threshold values
Comparing unit is all using positive logic.
As preferred, high threshold values input interface putting high level voltage threshold values, low valve valve input interface input low level
Threshold voltage, the node voltage between two resistance is less than high level voltage threshold values, and is more than low level voltage threshold values, that is, high,
Low level voltage threshold values forms three voltage ranges, respectively three kinds of states of corresponding circuits output.
As preferred, in order to adapt to different working environments and demand, two resistance can equivalence replacement be two electric currents
Source, one of current source is connected with power supply, and another current source is connected to ground, and the current direction of current source is for power supply direction extremely
Ground, its objective is to produce bias voltage.
The invention has the beneficial effects as follows:
A kind of multi input data mode parallel detection circuit, is believed to the input voltage of multiple Data Input Interfaces by detecting branch
Number it is respectively compared, judged the input data of this Data Input Interface according to the output data of the gate circuit in detection branch
Whether effectively, and by the testing result of multiple detection branches enter row operation by one with door, and according to the fan-out with door
According to whether all effective to judge the input data of multiple Data Input Interfaces, thus ensureing the effectiveness of data transmission procedure,
And can one or more in multiple input interfaces occur find in time during hanging or loose contact, it is to avoid because collection is not intended to
The signal of justice wasted as the data fault being led to and the time caused.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of description, below with presently preferred embodiments of the present invention and coordinate accompanying drawing describe in detail as after,
The specific embodiment of the present invention is shown in detail in by following examples and its accompanying drawing.
Brief description
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, this
Bright schematic description and description is used for explaining the present invention, does not constitute inappropriate limitation of the present invention.In the accompanying drawings:
The physical circuit schematic diagram of the detection branch that Fig. 1 is related to for first embodiment of the invention；
The circuit diagram that multiple detection branches that Fig. 2 is related to for first embodiment of the invention are connected between door；
Fig. 3 is the schematic diagram of the chip containing multi input data mode parallel detection circuit of the present invention and part peripheral circuit；
The schematic diagram of each position voltage in the detection branch that Fig. 4 is related to for first embodiment of the invention；
Fig. 5 applies the physical circuit schematic diagram of the detection branch that example is related to for the present invention second；
The physical circuit schematic diagram of many detections branch that Fig. 6 is related to for third embodiment of the invention；
The physical circuit schematic diagram of the detection branch that Fig. 7 is related to for fourth embodiment of the invention.
Wherein, in, in1-in4For Data Input Interface, dout、dout1- dout4For data output interface, dinsDefeated for data
Enter State- output interface, vhFor high threshold values input interface, vlFor low valve valve input interface, vccFor the power supply of circuit, gnd is
Earth terminal, r1-r6For resistance, is1、is2For current source, a1For the first threshold values comparing unit, a2For the second threshold values comparing unit,
dins1For the first data input State- output interface, dinsxFor xth data input State- output interface, dinsnFor the n-th data input
State- output interface, st is the total output interface of many data input state.
Wherein, in Fig. 4, the voltage of each position is described as follows: vinFor input voltage, vbiasFor bias voltage, va1+For first
Threshold values comparing unit a1The input voltage of in-phase end, va1-For the first threshold values comparing unit a1The input voltage of end of oppisite phase, va2+For
Two threshold values comparing unit a2The input voltage of in-phase end, va2-For the second threshold values comparing unit a2The input voltage of end of oppisite phase, vouta
For the first threshold values comparing unit a1Output voltage, voutbFor the second threshold values comparing unit a2Output voltage, vrefhFor high threshold values
Input voltage, vreflFor low valve valve input voltage, voutFor output voltage, vinsFor data input state-detection voltage.
Specific embodiment
Below with reference to the accompanying drawings and in conjunction with the embodiments, to describe the present invention in detail:
As shown in Figures 1 to 4 for the first embodiment of the present invention, wherein Fig. 1 is the concrete of detection branch in first embodiment
Circuit diagram；This detection branch includes detecting branch correspondingly with multiple Data Input Interface in, this detection branch bag
Include biasing circuit, the first threshold values comparing unit a1, the second threshold values comparing unit a2；Wherein biasing circuit includes the electricity of two series connection
Resistance r1、r2, resistance r1Power supply v with circuitccConnect, resistance r2It is connected with earth terminal gnd, in resistance r1、r2Between section
Point is connected with Data Input Interface in.
As shown in figure 1, the first threshold values comparing unit a1, the second threshold values comparing unit a2All using positive logic so that and data
The node of input interface in and the first threshold values comparing unit a1, the second threshold values comparing unit a2First input end connect, and two
The first input end of comparing unit is in-phase end；Second input of two comparing units is end of oppisite phase, the wherein first threshold values
Comparing unit a1Second input connect high threshold values input interface vh, the second threshold values comparing unit a2Second input connect
Low valve valve input interface vl；First threshold values comparing unit a1, the second threshold values comparing unit a2Outfan defeated with two of same OR gate
Enter end to connect one to one, with outfan and the data input State- output interface d of OR gateinsConnect, the first threshold values comparing unit
a1Outfan simultaneously with data output interface doutConnect.
As shown in Fig. 2 the outfan of the same OR gate in each detection branch be connected to one with the input of door on, and tie
Close Fig. 3, the detection object of the first embodiment of the present invention is 4 Data Input Interfaces, respectively Data Input Interface in1-in4,
I.e. n=4 in Fig. 2, after corresponding detection branch, exports corresponding data output interface dout1-dout4, input state output
Interface dins1- dins4；Input state output interface dins1- dins4Be both connected to one with the input of door on, should be defeated with door
Go out end and be connected with the total output interface st of data input state more than.
Shown in Fig. 3 is the schematic diagram of the chip containing the present invention and part peripheral circuit, resistance r3、r4Between formed
Node and high threshold values input interface vhConnect, resistance r5、r6Between the node and the low valve valve input interface v that are formedlConnect, pass through
Resistance r3、r4Between, resistance r5、r6Between formed proportionate relationship, thus generate with this detection shunting voltage be adapted height,
Low level voltage threshold values, and using high and low level voltage threshold values as benchmark.
And among these, high level voltage threshold values vrefhIt is disposed proximate to but the lower limit less than high level voltage, low level
Threshold voltage vreflIt is disposed proximate to but the lower limit more than low level voltage, resistance r1、r2Between node voltage be less than high electricity
Flat threshold voltage vrefh, and it is more than low level voltage threshold values vrefl, that is, form three voltage ranges, be respectively more than high level electricity
Pressure valve value vrefhInterval, be in high level voltage threshold values vrefhWith low level voltage threshold values vreflBetween interval and be less than
Low level voltage threshold values vreflInterval, and three kinds of states of respectively corresponding circuits output.
Meanwhile, in order to ensure more preferably Detection results, make resistance r1、r2Resistance equal, and resistance r1、r2Resistance is very
Greatly, thus in the ideal case, the bias voltage v of generationbiasPower supply v for circuitcc1/2nd, and this biased electrical
Electric current very little on road is so as to ignore to the impact caused by the high and low level of input data.
In order to better illustrate the work process of detection branch, each position voltage schematic diagram such as in cooperation Fig. 4, data is defeated
Circuit analysis under the upper three kinds of forms of incoming interface in is as follows:
(1), when Data Input Interface in state in which is high level, va1+=va2+=vin=vih(input high level), va1-
=vrefh, va2-=vrefl, due to vih> vrefhAnd vih> vrefl, so that the first threshold values comparing unit a1Output voltage vouta、
Second threshold values comparing unit a2Output voltage voutbIt is high level, after same OR gate computing, the data input state that obtains
Detection voltage vinsFor high level, that is, the logical value exporting is 1.
(2), when Data Input Interface in state in which is low level, va1+=va2+=vin=vil(input low level),
va1-=vrefh, va2-=vrefl, due to vil<vrefhAnd vil<vrefl, so that the first threshold values comparing unit a1Output voltage
vouta, the second threshold values comparing unit a2Output voltage voutbIt is low level, after same OR gate computing, the data obtaining is defeated
Enter state-detection voltage vinsFor high level, that is, the logical value exporting is 1.
(3), when Data Input Interface in state in which is high-impedance state, it is equal on Data Input Interface in not outer
Connect, now, va1+=va2+=vbias, due to vrefl< vbias< vrefh, so that the first threshold values comparing unit a1Output voltage
voutaFor low level, the second threshold values comparing unit a2Output voltage voutbFor high level, i.e. the first threshold values comparing unit a1Output
Logical value be 0, the second threshold values comparing unit a2The logical value of output is 1, after same OR gate computing, the data input that obtains
State-detection voltage vinsFor low level, that is, the logical value exporting is 0.
In sum, as multiple data input state-detection voltage vinsOutput logical value when being 1, through and door
The output logical value obtaining after computing is 1, and multiple Data Input Interface in state in which are high level or low level, that is, many
The input data logic of individual Data Input Interface in is effectively, and logically, output voltage voutWith input voltage vinPhase
Deng the output interface d therefore the next stage circuit being connected with this testing circuit is fetched dataoutOutput data as this next stage circuit
Input data；As multiple data input state-detection voltage vinsOutput logical value in have one be 0 when, Jing Guoyu
The output logical value obtaining after the computing of door is 0, has residing for a Data Input Interface in multiple Data Input Interface in
State is high-impedance state, and that is, the input data logic of multiple Data Input Interface in is invalid, therefore next being connected with this testing circuit
Level circuit stops accepting and believing this output data.
Fig. 5 applies the physical circuit schematic diagram detecting branch in example, the difference compared with first embodiment for the present invention second
It is: the first threshold values comparing unit a1, the second threshold values comparing unit a2First input end be end of oppisite phase；First threshold values compares
Unit a1, the second threshold values comparing unit a2The second input be in-phase end, when Data Input Interface in state in which is high electricity
At ordinary times, the first threshold values comparing unit a1, the second threshold values comparing unit a2The logical value of output is 0, when Data Input Interface in institute
When the state at place is low level, the first threshold values comparing unit a1, the second threshold values comparing unit a2The logical value of output is 1, that is, defeated
Go out that logical value is contrary with input logic value, the next stage circuit being now connected with this testing circuit is fetched data output interface dout's
, as the input data of this next stage circuit, remaining is with reference to above-mentioned with regard to first for result after output data NAND gate computing
The description of embodiment.
Fig. 6 is the physical circuit schematic diagram detecting branch in third embodiment of the invention, and this detection branch includes biased electrical
Road, the first threshold values comparing unit a1, the second threshold values comparing unit a2；Wherein biasing circuit includes the current source is of two series connection1、
is2, current source is1Power supply v with circuitccConnect, current source is2It is connected with earth terminal gnd, in current source is1、is2It
Between node be connected with Data Input Interface in, that is, third embodiment of the invention is on the basis of first embodiment, will bias
Resistance r on circuit1、r2Replace with current source is1、is2, remaining is with reference to the above-mentioned description with regard to first embodiment.
Fig. 7 is the physical circuit schematic diagram detecting branch in fourth embodiment of the invention, the first threshold values comparing unit a1,
Two threshold values comparing unit a2Outfan connect one to one with two inputs of XOR gate, the outfan of XOR gate and data
Input state output interface dinsConnect, now, as data input state-detection voltage vinsOutput logical value be 0 when, data
The input data logical validity of input interface in；As data input state-detection voltage vinsOutput logical value be 1 when, data
The input data logic of input interface in is invalid, and that is, the fourth embodiment of the present invention is on the basis of first embodiment, will be with
OR gate replaces with XOR gate so that the correspondence of output logical value and effectiveness is contrary with first embodiment, and remaining is with reference to above-mentioned pass
Description in first embodiment.
Meanwhile, by the exchange of in-phase end and end of oppisite phase in second embodiment, by resistance r in 3rd embodiment1、r2Replace with
Current source is1、is2, in fourth embodiment, same OR gate is replaced with the form of XOR gate, is all on the basis of first embodiment
The single replacement carrying out, this three kinds of substitute modes can freely form new embodiment, the such as the 5th embodiment: in the first enforcement
On the basis of example, by resistance r1、r2Replace with current source is1、is2, XOR gate, the 5th so being formed will be replaced with OR gate
Embodiment be implement to the 3rd, the simple combination of fourth embodiment, such combine new embodiment be the present invention etc.
Effect embodiment；In addition, detection object is 4 Data Input Interfaces in first embodiment of the invention, can not constitute to the present invention
Restriction, by 4 be revised as 2 any of the above numeral, be the Equivalent embodiments of the present invention.
The above, only presently preferred embodiments of the present invention, not the present invention is made with any pro forma restriction；All
The those of ordinary skill of the industry all can shown in by specification accompanying drawing and the above and swimmingly implement the present invention；But, all
Those skilled in the art, in the range of without departing from technical solution of the present invention, are done using disclosed above technology contents
The a little change going out, the equivalent variations modified and develop, are the Equivalent embodiments of the present invention；Meanwhile, all according to the present invention
The change of any equivalent variations, modification and differentiation that substantial technological is made to above example etc., all still fall within the skill of the present invention
Within the protection domain of art scheme.
Claims (9)
1. a kind of multi input data mode parallel detection circuit it is characterised in that: this testing circuit includes and multiple data inputs
Interface detects branch correspondingly；Described detection branch includes biasing circuit, the first threshold values comparing unit, the second threshold values compare
Unit；Described biasing circuit includes the resistance of two series connection, and the node between two described resistance is connected with Data Input Interface,
Connect node and described first threshold values comparing unit, the first input end of the second threshold values comparing unit of described Data Input Interface
Connect；Described first threshold values comparing unit, the second threshold values comparing unit the second input respectively with a threshold values input interface
Connect, a pair of two inputs one of described first threshold values comparing unit, the outfan of the second threshold values comparing unit and gate circuit
Should connect, each detection branch in described gate circuit outfan be connected to one with the input of door on, according to door
Whether fan-out is according to effective to judge the input data of Data Input Interface.
2. multi input data mode parallel detection circuit according to claim 1 it is characterised in that: described gate circuit be with
OR gate or XOR gate, the outfan of described gate circuit is connected with data input State- output interface.
3. multi input data mode parallel detection circuit according to claim 1 it is characterised in that: the input of described threshold values connects
Mouth includes high threshold values input interface, low valve valve input interface, and the second input of described first threshold values comparing unit connects height
Threshold values input interface, the second input of described second threshold values comparing unit connects low valve valve input interface.
4. multi input data mode parallel detection circuit according to claim 1 it is characterised in that: described first threshold values ratio
Select one compared with the outfan of unit or described second threshold values comparing unit to be connected with data output interface.
5. multi input data mode parallel detection circuit according to claim 1 it is characterised in that: when input data is effective
When, the next stage circuit being connected with this circuit will continue to gather this data signal；When input data is invalid, it is connected with this circuit
Next stage circuit by stop gather this data signal.
6. multi input data mode parallel detection circuit according to claim 1 it is characterised in that: two described resistance
Resistance is equal, and so that one of described resistance is connected with power supply, and another described resistance is connected to ground.
7. multi input data mode parallel detection circuit according to claim 1 it is characterised in that: described first threshold values ratio
It is in-phase end compared with the first input end of unit, the second threshold values comparing unit, described first threshold values comparing unit, the second threshold values compare
Second input of unit is end of oppisite phase.
8. multi input data mode parallel detection circuit according to claim 3 it is characterised in that: described high threshold values input
Interface putting high level voltage threshold values, described low valve valve input interface input low level threshold voltage, between two described resistance
Node voltage be less than high level voltage threshold values, and be more than low level voltage threshold values.
9. according to multi input data mode parallel detection circuit described in one of them for the claim 1 to 8 it is characterised in that: two
Individual described resistance can equivalence replacement be two current sources, and one of described current source is connected with power supply, another described electric current
Source is connected to ground, and the current direction of described current source is power supply direction to ground.
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| CN104000582A (en) * | 2014-05-04 | 2014-08-27 | 山东中医药大学 | Lead falling detection device for electrocardiogram monitoring device |
| CN104502683A (en) * | 2014-12-31 | 2015-04-08 | 武汉华中数控股份有限公司 | Switch quantity signal detection method and detection circuit |
| JP2015076768A (en) * | 2013-10-10 | 2015-04-20 | 日立オートモティブシステムズ株式会社 | Electronic control device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1714496A (en) * | 2002-11-25 | 2005-12-28 | 英特赛尔美国股份有限公司 | Method of setting bi-directional offset in a PWM controller using a single programming pin |
| JP2015076768A (en) * | 2013-10-10 | 2015-04-20 | 日立オートモティブシステムズ株式会社 | Electronic control device |
| CN104000582A (en) * | 2014-05-04 | 2014-08-27 | 山东中医药大学 | Lead falling detection device for electrocardiogram monitoring device |
| CN104502683A (en) * | 2014-12-31 | 2015-04-08 | 武汉华中数控股份有限公司 | Switch quantity signal detection method and detection circuit |
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Application publication date: 20170125 |
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