CN106301335A - Input data validity testing circuit with on-off control - Google Patents
Input data validity testing circuit with on-off control Download PDFInfo
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- CN106301335A CN106301335A CN201610814148.8A CN201610814148A CN106301335A CN 106301335 A CN106301335 A CN 106301335A CN 201610814148 A CN201610814148 A CN 201610814148A CN 106301335 A CN106301335 A CN 106301335A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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Abstract
The invention discloses a kind of input data validity testing circuit with on-off control, testing circuit includes biasing circuit, the first threshold values comparing unit, the second threshold values comparing unit；Biasing circuit includes that two resistance connected, the node between two resistance are connected with Data Input Interface, and in the both sides of node, two described resistance are connected to a switch；The first input end of the node and the first threshold values comparing unit, the second threshold values comparing unit that connect Data Input Interface connects；First threshold values comparing unit, the second input of the second threshold values comparing unit are connected with a threshold values input interface respectively, and the first threshold values comparing unit, the outfan of the second threshold values comparing unit are connected to a data output interface；The present invention is by comparing the input voltage signal of Data Input Interface, and the output data of two data output interfaces are judged whether equal by next stage circuit, thus detects that the input data of Data Input Interface are the most effective.
Description
Technical field
The present invention relates to integrated circuit fields, particularly relate to a kind of input data validity with on-off control and detect electricity
Road.
Background technology
Since mankind's nineteen forty-seven invention transistor, between more than 50 year, semiconductor technology experienced by silicon transistor, integrated electricity
The several generations such as road, super large-scale integration, very large scale integration, development speed is that other industries are unexistent soon；In
Central processor refers to the parts that data are processed and are controlled processing procedure by computer-internal, along with extensive collection
Becoming the developing rapidly of circuit engineering, integrated chip density is more and more higher, CPU can integrated on a semiconductor chip in a, this
There is the LSI devices of central processing unit function, be collectively referred to as " microprocessor "；Either videocorder, intelligence are washed
The household appliances such as clothing machine, mobile phone, or car engine controls, and Digit Control Machine Tool, guided missile precise guidance etc. will embed
All kinds of different microprocessors；The core component of microcomputer is not only by microprocessor, is also various digital intelligent equipment
Critical component.
And interface chip, it is a kind of electronic devices and components for connecting between microprocessor and memorizer, it includes number
According to the data buffer of temporary buffering or bus buffer, the bus driver etc. providing bigger driving force for address signal
Deng, in brief, interface chip is for ensuring that safety and the stability of data transmission procedure.
But, during data are transmitted, the input interface of interface chip can cannot determine interface because of loose contact
The input data of chip are the most effective, and now, the output interface of interface chip the most still can export the determination signal of " 0 " or " 1 ",
And its signal is transferred in the middle of microprocessor；But, due to the loose contact of input interface, make the input data of interface chip
Real data can not be reflected, thus it is nonsensical for causing the output data of interface chip.How to obtain interface chip
The effectiveness of upper input data, thus decide whether the output data accepting and believing on interface chip, become for people's research
Individual problem.
In digital circuit, digital circuit typically has three kinds of output states, for high level, low level and high-impedance state, wherein
High level is logical one, and low level is logical zero, and high-impedance state is equivalent to partition state；Wherein by logical one and logical zero group
The binary signal become, is the major way of current electronic chip data transfer inside, and if the input interface of interface chip
In the case of unsettled or loose contact, high-impedance state will be formed, be based on this, if can be carried out by the input of docking port chip
The test of high-impedance state, obtains the effectiveness inputting data on interface chip, thus avoids cannot judging to export whether data have
The technical problem of effect.
Therefore, it is necessary to provide a kind of circuit inputting and detecting input data validity.
Summary of the invention
The present invention solves that the problems referred to above provide a kind of input data validity testing circuit with on-off control, pass through
Comparing the input voltage signal of Data Input Interface, the output data of two data output interfaces are entered by next stage circuit
Row judges whether equal, thus detects that the input data of Data Input Interface are the most effective.
For achieving the above object, reaching the effect above, the present invention is achieved through the following technical solutions:
A kind of input data validity testing circuit with on-off control, this testing circuit includes biasing circuit, the first threshold values
Comparing unit, the second threshold values comparing unit；Wherein biasing circuit includes two resistance connected, node between the resistances
Being connected with Data Input Interface, and in the both sides of node, two described resistance are connected to a switch, described switch connects to be had
Switch control interface；The first input end of this node and the first threshold values comparing unit, the second threshold values comparing unit connects；First valve
Value comparing unit, the second input of the second threshold values comparing unit are connected with a threshold values input interface respectively, the first threshold values ratio
Relatively unit, the outfan of the second threshold values comparing unit are connected to a data output interface, are connected with this testing circuit
Next stage circuit is by judging whether equal to the output data of two data output interfaces, thus detects that data input
The input data of interface are the most effective.
As preferably, in order to detect that circuit output state is high level, low level or high-impedance state, threshold values input interface
Include high threshold values input interface, low valve valve input interface, upload be input into from high threshold values input interface, low valve valve input interface
High and low level voltage threshold values as benchmark.
As preferably, the second input of the first threshold values comparing unit is connected high threshold values input interface, the second threshold values
Second input of comparing unit connects low valve valve input interface.
As preferably, data output interface includes the first data output interface, the second data output interface, the first number
According to the outfan connection of output interface and the first threshold values comparing unit, the second data output interface and the second threshold values comparing unit
Outfan connects.
As preferably, when the output data of the first data output interface and the second data output interface are equal, data
Input interface state in which is that the input data of high level or low level, i.e. Data Input Interface are effective；When the first data are defeated
When the output data of outgoing interface and the second data output interface are unequal, Data Input Interface state in which is in high-impedance state,
The i.e. input data invalid of Data Input Interface.
As preferably, when inputting data and being effective, continuation is gathered these data by the next stage circuit being connected with this circuit
Signal；When inputting data invalid, stopping is gathered this data signal by the next stage circuit being connected with this circuit.
As preferably, due to the span of high and low level be two extreme, so the biasing circuit produced takes centre
During value, scheme is preferable, so making the resistance of two resistance equal, and makes one of them resistance be connected with power supply, another resistance and
Ground connects, so that the intermediate value that bias voltage is circuit voltage that intermediate node produces.
As preferably, the first threshold values comparing unit, the first input end of the second threshold values comparing unit are in-phase end, first
Threshold values comparing unit, the second input of the second threshold values comparing unit are end of oppisite phase, the i.e. first threshold values comparing unit, the second threshold values
Comparing unit all uses positive logic.
As preferably, high threshold values input interface putting high level voltage threshold values, low valve valve input interface input low level
Threshold voltage, the node voltage between two resistance is less than high level voltage threshold values, and is more than low level voltage threshold values, the highest,
Low level voltage threshold values forms three voltage ranges, respectively three kinds of states of corresponding circuits output.
As preferably, in order to adapt to different working environments and demand, two resistance equivalence can replace with two electric currents
Source, one of them current source is connected with power supply, and another current source is connected to ground, the current direction of current source be power supply direction extremely
Ground, its objective is to produce bias voltage.
The invention has the beneficial effects as follows:
A kind of input data validity testing circuit with on-off control, is carried out by the input voltage signal of docking port chip
Relatively, the next stage circuit being connected with this testing circuit is by judging whether the output data of two data output interfaces
Equal, thus detect that the input data of Data Input Interface are the most effective, thus ensure the effectiveness of data transmission procedure, and
Can find in time when input interface occurs unsettled or loose contact, it is to avoid because gathering insignificant signal as data institute
The fault caused.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of description, below with presently preferred embodiments of the present invention and coordinate accompanying drawing describe in detail as after,
The detailed description of the invention of the present invention is shown in detail in by following example and accompanying drawing thereof.
Accompanying drawing explanation
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, this
Bright schematic description and description is used for explaining the present invention, is not intended that inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the physical circuit of the input data validity testing circuit with on-off control that first embodiment of the invention relates to
Schematic diagram；
Fig. 2 is with chip and the part peripheral circuit of the input data validity testing circuit of on-off control containing the present invention
Schematic diagram；
Fig. 3 is that the input data validity testing circuit with on-off control that first embodiment of the invention relates to all is located at switch
Each position V diagram in the case of Guan Bi；
Fig. 4 is that the present invention second executes the physical circuit with the input data validity testing circuit of on-off control that example relates to and shows
It is intended to；
Fig. 5 is the physical circuit of the input data validity testing circuit with on-off control that third embodiment of the invention relates to
Schematic diagram；
Fig. 6 is the physical circuit of the input data validity testing circuit with on-off control that fourth embodiment of the invention relates to
Schematic diagram.
Wherein, IN is Data Input Interface, IKSFor switch control interface, A is the first data output interface, and B is the second number
According to output interface, VHFor high threshold values input interface, VLFor low valve valve input interface, VCCFor the power supply of circuit, GND is ground connection
End, R1-R6For resistance, IS1、IS2For current source, K1、K2For switch, A1It is the first threshold values comparing unit, A2It is that the second threshold values compares
Unit.
Wherein, in Fig. 3, the voltage of each position is described as follows: VINFor input voltage, VbiasFor bias voltage, VA1+It is first
Threshold values comparing unit A1The input voltage of in-phase end, VA1-It is the first threshold values comparing unit A1The input voltage of end of oppisite phase, VA2+It is
Two threshold values comparing unit A2The input voltage of in-phase end, VA2-It is the second threshold values comparing unit A2The input voltage of end of oppisite phase, Vouta
It is the first threshold values comparing unit A1Output voltage, VoutbIt is the second threshold values comparing unit A2Output voltage, VrefhFor high threshold values
Input voltage, VreflFor low valve valve input voltage.
Detailed description of the invention
Below with reference to the accompanying drawings and in conjunction with the embodiments, the present invention is described in detail:
As shown in Figure 1 to Figure 3 for the first embodiment of the present invention, wherein Fig. 1 is the physical circuit schematic diagram of first embodiment；
This testing circuit includes biasing circuit, the first threshold values comparing unit A1, the second threshold values comparing unit A2；Wherein biasing circuit includes
The resistance R of two series connection1、R2, resistance R1The power supply V of one end and circuitCCConnect, the other end and switch K1Connect, resistance
R2One end be connected with earth terminal GND, the other end with switch K2Connect, at switch K1、K2Between node and Data Input Interface
IN is connected.
As it is shown in figure 1, the first threshold values comparing unit A1, the second threshold values comparing unit A2All use positive logic so that with data
The node of input interface IN and the first threshold values comparing unit A1, the second threshold values comparing unit A2First input end connect, and two
The first input end of comparing unit is in-phase end；Second input of two comparing units is end of oppisite phase, wherein the first threshold values
Comparing unit A1Second input connect high threshold values input interface VH, the second threshold values comparing unit A2Second input connect
Low valve valve input interface VL；First threshold values comparing unit A1, the second threshold values comparing unit A2Outfan be connected to first number
According to output interface A, the second data output interface B.
Shown in Fig. 2 is the schematic diagram of the chip containing the present invention and part peripheral circuit, resistance R3、R4Between formed
Node and high threshold values input interface VHConnect, resistance R5、R6Between the node and the low valve valve input interface V that are formedLConnect, pass through
Resistance R3、R4Between, resistance R5、R6Between formed proportionate relationship, thus generate and this testing circuit voltage adapt height,
Low level voltage threshold values, and using high and low level voltage threshold values as benchmark.
And among these, high level voltage threshold values VrefhIt is disposed proximate to but is less than the lower limit of high level voltage, low level
Threshold voltage VreflIt is disposed proximate to but is more than the lower limit of low level voltage, resistance R1、R2Between node voltage less than high electricity
Flat threshold voltage Vrefh, and more than low level voltage threshold values Vrefl, i.e. form three voltage ranges, be respectively more than high level electricity
Pressure valve value VrefhInterval, be in high level voltage threshold values VrefhWith low level voltage threshold values VreflBetween interval and be less than
Low level voltage threshold values VreflInterval, and three kinds of states of respectively corresponding circuits output.
Meanwhile, in order to ensure more preferably Detection results, resistance R is made1、R2Resistance equal, and resistance R1、R2Resistance is very
Greatly, thus in the ideal case, the bias voltage V of generationbiasPower supply V for circuitCC1/2nd, and this biased electrical
Electric current on road is the least so that it is the impact being caused the high and low level inputting data is ignored.
In order to better illustrate the work process of whole circuit, at switch K1、K2In the case of Guan Bi, coordinate in Fig. 3 every
Putting voltage schematic diagram such as, the circuit analysis under the upper three kinds of forms of Data Input Interface IN is as follows:
(1), when Data Input Interface IN state in which is high level, VA1+ =VA2+=VIN=VIH(input high level), VA1-
=Vrefh, VA2-=Vrefl, due to VIH> VrefhAnd VIH> Vrefl, so that the first threshold values comparing unit A1Output voltage Vouta、
Second threshold values comparing unit A2Output voltage VoutbBeing high level, the logical value i.e. exported is 1.
(2), when Data Input Interface IN state in which is low level, VA1+ =VA2+=VIN=VIL(input low level),
VA1- =Vrefh, VA2-=Vrefl, due to VIL<VrefhAnd VIL <Vrefl, so that the first threshold values comparing unit A1Output voltage
Vouta, the second threshold values comparing unit A2Output voltage VoutbBeing low level, the logical value i.e. exported is 0.
(3), when Data Input Interface IN state in which is high-impedance state, it is equal on Data Input Interface IN the most outward
Connect, now, VA1+ =VA2+=Vbias, due to Vrefl < Vbias < Vrefh, so that the first threshold values comparing unit A1Output voltage
VoutaFor low level, the second threshold values comparing unit A2Output voltage VoutbFor high level, the i.e. first threshold values comparing unit A1Output
Logical value be 0, the second threshold values comparing unit A2The logical value of output is 1, and the logical value of two comparing unit outputs is unequal.
In sum, as the first threshold values comparing unit A1, the second threshold values comparing unit A2When the logical value of output is equal, number
Be high level or low level according to input interface IN state in which, i.e. the input mathematical logic of Data Input Interface IN is effective, and
And logically export with input equal, therefore the next stage circuit being connected with this testing circuit take two output data in any
One input data as this next stage circuit；As the first threshold values comparing unit A1, the second threshold values comparing unit A2Output
Logical value unequal time, Data Input Interface IN state in which is high-impedance state, i.e. the input data of Data Input Interface IN
Logic is invalid, therefore the next stage circuit being connected with this testing circuit stops accepting and believing this output data.
As switch K1、K2In the case of Duan Kaiing, then close the detection function of input data validity.
Fig. 4 is the physical circuit schematic diagram that the present invention second executes example, and the difference compared with first embodiment is: the first valve
Value comparing unit A1, the second threshold values comparing unit A2First input end be end of oppisite phase；First threshold values comparing unit A1, second
Threshold values comparing unit A2The second input be in-phase end, when Data Input Interface IN state in which is high level, first
Threshold values comparing unit A1, the second threshold values comparing unit A2The logical value of output is 0, when Data Input Interface IN state in which
During for low level, the first threshold values comparing unit A1, the second threshold values comparing unit A2The logical value of output is 1, i.e. exports logical value
Contrary with input logic value, the next stage circuit that is now connected with this testing circuit take in two output data any one with
Result after not gate computing is as the input data of this next stage circuit, and remaining is with reference to above-mentioned retouching about first embodiment
State.
Fig. 5 is the physical circuit schematic diagram of third embodiment of the invention, and this testing circuit includes biasing circuit, the first threshold values
Comparing unit A1, the second threshold values comparing unit A2；Wherein biasing circuit includes two current source IS connected1、IS2, current source IS1
Power supply V with circuitCCConnect, current source IS2It is connected with earth terminal GND, at current source IS1、IS2Between node and number
Be connected according to input interface IN, i.e. third embodiment of the invention is on the basis of first embodiment, by the resistance on biasing circuit
R1、R2Replace with current source IS1、IS2, remaining is with reference to the above-mentioned description about first embodiment.
Fig. 6 is the physical circuit schematic diagram of fourth embodiment of the invention, is on the basis of the second embodiment, by biased electrical
Resistance R on road1、R2Replace with current source IS1、IS2, remaining with reference to above-mentioned about first embodiment, the second embodiment, the 3rd
The description of embodiment.
The above, only presently preferred embodiments of the present invention, not the present invention is made any pro forma restriction；All
The those of ordinary skill of the industry all can shown in by specification accompanying drawing and the above and implement the present invention swimmingly；But, all
Those skilled in the art, in the range of without departing from technical solution of the present invention, utilize disclosed above technology contents to do
The a little change gone out, the equivalent variations modified and develop, be the Equivalent embodiments of the present invention；Meanwhile, all according to the present invention's
The change of any equivalent variations that above example is made by substantial technological, modify and differentiation etc., all still fall within the skill of the present invention
Within the protection domain of art scheme.
Claims (10)
1. the input data validity testing circuit with on-off control, it is characterised in that: this testing circuit includes biasing
Circuit, the first threshold values comparing unit, the second threshold values comparing unit；Described biasing circuit includes two resistance connected, two institutes
The node stated between resistance is connected with Data Input Interface, and in the both sides of node, two described resistance are connected to one and open
Closing, described switch connection has switch control interface；The node connecting described Data Input Interface compares single with described first threshold values
Unit, the first input end of the second threshold values comparing unit connect；Described first threshold values comparing unit, the of the second threshold values comparing unit
Two inputs are connected with a threshold values input interface respectively, described first threshold values comparing unit, the second threshold values comparing unit defeated
Going out end and be connected to a data output interface, two described data are exported by the next stage circuit being connected with this testing circuit
The output data of interface carry out judging whether equal, thus detect that the input data of Data Input Interface are the most effective.
Input data validity testing circuit with on-off control the most according to claim 1, it is characterised in that: described
Threshold values input interface includes high threshold values input interface, low valve valve input interface.
Input data validity testing circuit with on-off control the most according to claim 2, it is characterised in that: described
Second input of the first threshold values comparing unit connects high threshold values input interface, the second input of described second threshold values comparing unit
End connects low valve valve input interface.
Input data validity testing circuit with on-off control the most according to claim 1, it is characterised in that: described
Data output interface includes the first data output interface, the second data output interface, described first data output interface and
The outfan of one threshold values comparing unit connects, and the outfan of described second data output interface and the second threshold values comparing unit is even
Connect.
Input data validity testing circuit with on-off control the most according to claim 4, it is characterised in that: when
When the output data of one data output interface and the second data output interface are equal, described Data Input Interface state in which is
High level or low level, the input data of the most described Data Input Interface are effective；When the first data output interface and the second data
When the output data of output interface are unequal, described Data Input Interface state in which is in high-impedance state, and the most described data are defeated
The input data invalid of incoming interface.
Input data validity testing circuit with on-off control the most according to claim 5, it is characterised in that: when defeated
Enter data effective time, the next stage circuit being connected with this circuit by continuation gather this data signal；When inputting data invalid, with
Stopping is gathered this data signal by the next stage circuit that this circuit connects.
Input data validity testing circuit with on-off control the most according to claim 1, it is characterised in that: two
The resistance of described resistance is equal, and makes one of them described resistance be connected with power supply, and another described resistance is connected to ground.
Input data validity testing circuit with on-off control the most according to claim 1, it is characterised in that: described
First threshold values comparing unit, the first input end of the second threshold values comparing unit are in-phase end, described first threshold values comparing unit,
Second input of two threshold values comparing units is end of oppisite phase.
Input data validity testing circuit with on-off control the most according to claim 2, it is characterised in that: described
High threshold values input interface putting high level voltage threshold values, described low valve valve input interface input low level threshold voltage, two institutes
State the node voltage between resistance and be less than high level voltage threshold values, and more than low level voltage threshold values.
10. according to one of them described input data validity testing circuit with on-off control of claim 1 to 9, its
It is characterised by: two described resistance equivalence can replace with two current sources, and one of them described current source is connected with power supply, another
Individual described current source is connected to ground, and the current direction of described current source is that power supply direction is to ground.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610814148.8A CN106301335A (en) | 2016-09-10 | 2016-09-10 | Input data validity testing circuit with on-off control |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610814148.8A CN106301335A (en) | 2016-09-10 | 2016-09-10 | Input data validity testing circuit with on-off control |
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| CN104000582A (en) * | 2014-05-04 | 2014-08-27 | 山东中医药大学 | Lead falling detection device for electrocardiogram monitoring device |
| CN104502683A (en) * | 2014-12-31 | 2015-04-08 | 武汉华中数控股份有限公司 | Switch quantity signal detection method and detection circuit |
| JP2015076768A (en) * | 2013-10-10 | 2015-04-20 | 日立オートモティブシステムズ株式会社 | Electronic control device |
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|---|---|---|---|---|
| CN1714496A (en) * | 2002-11-25 | 2005-12-28 | 英特赛尔美国股份有限公司 | Method of setting bi-directional offset in a PWM controller using a single programming pin |
| JP2015076768A (en) * | 2013-10-10 | 2015-04-20 | 日立オートモティブシステムズ株式会社 | Electronic control device |
| CN104000582A (en) * | 2014-05-04 | 2014-08-27 | 山东中医药大学 | Lead falling detection device for electrocardiogram monitoring device |
| CN104502683A (en) * | 2014-12-31 | 2015-04-08 | 武汉华中数控股份有限公司 | Switch quantity signal detection method and detection circuit |
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