CN106325159A - High-speed collection board based on electronic filtering technology, and collection processing method - Google Patents
High-speed collection board based on electronic filtering technology, and collection processing method Download PDFInfo
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- CN106325159A CN106325159A CN201610772953.9A CN201610772953A CN106325159A CN 106325159 A CN106325159 A CN 106325159A CN 201610772953 A CN201610772953 A CN 201610772953A CN 106325159 A CN106325159 A CN 106325159A
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- G—PHYSICS
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
Abstract
The invention discloses a high-speed collection board based on electronic filtering technology, and a collection processing method. The collection board comprises an ARM chip, a client, a server, a pre-amplifier, a follower, a differentiating circuit, a first stage amplifier, a second stage amplifier, a reverse amplifier, an analog-digital converter, an FPGA and a GPU, wherein the pre-amplifier, the follower, the differentiating circuit, the first stage amplifier, the second stage amplifier, the reverse amplifier, the analog-digital converter, the FPGA and the GPU are sequentially connected. The FPGA and the GPU are connected to the client through a serial port and the ARM chip, and the client transmits an instruction to the FPGA or the GPU, and controls the processing process of a pulse signal. The client and the server carry out the bidirectional communication through a network. The collection board makes the most of the GPU to support floating calculation, and is high in programmability. The collection board achieves the multi-thread calculation, and is high in calculation speed. The collection board is high in data transmission speed. In order to solve a problem of pulse accumulation, the method provides the reliable hardware basis. The collection board can overcome the technical difficulty of pulse accumulation, improves the utilization rate of the pulse signals, and finally improves the detection precision of a system.
Description
Technical field
The invention belongs to nuclear physics category, the field such as including core medical treatment, core geological prospecting, industrial detection, particularly relate to one
Plant high speed acquisition board based on electronic filtering techniques and acquiring and processing method.
Background technology
Currently, common X-ray and nuclear particle collection plate do not have spectrum unscrambling function, and are only pulse to be piled up
Judge, if being judged as pulse pile-up, the pulse of accumulation is abandoned, the pulse do not piled up is retained.Though this way ensures
Signal accurate, but reduce the utilization rate of signal, and then reduce the energy resolution of system.
Pulse pile-up (such as Fig. 2) refers to that same detection channels detects multiple core thing within a scintillation pulse persistent period
Part.Counting rate is the highest, and pulse pile-up is the most serious, and (actual count rate and the relation curve of effective counter rate, such as Fig. 3, it is seen that real
Border counting rate is the highest, and pulse pile-up is the most serious), pulse pile-up causes multiple impulse waveform overlapping, affects data collecting system pair
The reading of individual pulse information, all can give up to fall by the pulse of accumulation under normal circumstances.This is owing to spectrum unscrambling process relates to greatly
Amount data transmission and computing, be 80MHz/s according to arithmetic speed, and resolution is that the a/d converter of 12 is calculated, and needs at least
The data transmission of 960Mb/s and computing, this requirement high to hardware proposition undoubtedly, portable particularly with small volume sets
Standby.The intractability that visible impulse is piled up essentially consists in hardware, to performance requirements such as the data transmission bauds of system, arithmetic speeds
Higher, it is achieved more difficulty of getting up.
The signal that impulsing is piled up is discarded, though avoiding a large amount of computing, but the detection essence that the system that have impact on is overall
Degree.Along with the new detector energy resolution and the raising of detection efficient, pulse pile-up is increasingly becoming lifting system accuracy of detection
Major obstacle.
GPU full name is Graphics Processing Unit (graphic process unit), is that one is devoted to image procossing work
The microprocessor made, and along with the programmability of GPU constantly strengthens, its application power far beyond the category of image procossing,
Utilize GPU to carry out general-purpose computations and be increasingly becoming the developing direction in this field.GPU mainly has three aspect advantages for general-purpose computations:
1) supporting Floating-point Computation, programmability is strong；2) multithreading calculates, and calculates speed fast (per second up to TFlops)；3) PCIe is supported
Parallel interface, data transmission bauds is fast (reaching as high as 8Gb/s).
Summary of the invention
For above-mentioned prior art situation, the present invention provides a kind of high speed acquisition board based on electronic filtering techniques and collection
Processing method.The present invention can solve the problem that the technological difficulties that pulse pile-up processes, and improves pulse signal utilization rate, finally promotes system
Accuracy of detection.
In order to achieve the above object, the technical solution used in the present invention is as follows: a kind of high speed based on electronic filtering techniques
Collection plate, puts including ARM chip, client, server and the preamplifier being sequentially connected, follower, peaker, one-level
Big device, two-stage amplifier, sign-changing amplifier, analog-digital converter, FPGA, GPU；Described analog-digital converter is for by front end output
Analogue signal is converted to digital signal through over sampling, quantization, cataloged procedure；Described FPGA is for exporting described analog-digital converter
Digital signal be filtered shape and pile up identify, by impulsing pile up and can spectrum unscrambling data transmit to GPU, by GPU
Carry out spectrum unscrambling computing；Described FPGA and GPU is transmitted to client through ARM chip by serial ports, and client is to FPGA or GPU simultaneously
Send instruction, the processing procedure of control wave；Carrying out two-way communication by network between client and server, being used for will
The spectrogram information file transmission that spectrum unscrambling computing obtains is to server, by calculated for server analysis destination file transmission extremely visitor
Family end.
Further, described follower be connected with peaker constitute circuit include: signal acquiring board joint P1, resistance
R1-R3, resistance R5, electric capacity C1 and amplifier U1；One end of signal acquiring board joint P1 is connected with one end of resistance R1, resistance R1's
The other end is connected with the electrode input end of amplifier U1, and one end of resistance R2 is connected with the negative input of amplifier U1, resistance R2's
The other end is connected with one end of resistance R3 after being connected with the outfan of amplifier U1, one end phase of the other end of resistance R3 and electric capacity C1
Even, the other end of electric capacity C1 is connected with one end of resistance R5, the other end of signal acquiring board joint P1 and the other end of resistance R5
All ground connection；The positive and negative power input of amplifier U1 connects+5V and-5V power supply respectively.
Further, the circuit that described first stage amplifier and two-stage amplifier are constituted includes: amplifier U2, amplifier U3, electric capacity
C2, electric capacity C3, resistance R6-R13, channel to channel adapter U5 and channel to channel adapter U6；The common port of electric capacity C1 and resistance R5 and amplifier
The electrode input end of U2 is connected, and the channel output end of channel to channel adapter U5 is connected with one end of electric capacity C2 afterwards and the negative pole of amplifier U2
Input is connected, and the other end of electric capacity C2 is connected with the gain compensation port of amplifier U2；The first passage of channel to channel adapter U5 is defeated
One end of inbound port resistance R6 is connected, and one end of second channel input port D2 and the resistance R7 of channel to channel adapter U5 is connected, logical
One end of third channel input port D3 and the resistance R13 of track selector U5 is connected, the fourth lane input of channel to channel adapter U5
Port D1 is connected with one end of resistance R8, the other end of resistance R6, the other end of resistance R7, the other end of resistance R13, resistance R8
The other end and the outfan of amplifier U2 be all connected with the electrode input end mouth of amplifier U2；
The channel output end of channel to channel adapter U6 is connected with the negative input of amplifier U3 after being connected with one end of electric capacity C3,
The other end of electric capacity C3 is connected with the gain compensation port of amplifier U3；The first passage input port D1 of channel to channel adapter U6 and electricity
One end of resistance R9 is connected, and one end of second channel input port D2 and the resistance R10 of channel to channel adapter U6 is connected, channel to channel adapter
One end of third channel input port D3 and the resistance R11 of U6 is connected, the fourth lane input port D1 of channel to channel adapter U6 with
One end of resistance R12 be connected, the other end of resistance R9, the other end of resistance R10, the other end of resistance R111, resistance R12 another
The outfan of one end and amplifier U3 is all connected with the electrode input end mouth of amplifier U2.
Further, described sign-changing amplifier includes: amplifier U4, resistance R4, resistance R14-R16, electric capacity C4 and electric capacity C5；
The common port of resistance R9, resistance R10, resistance R111, resistance R12 and amplifier U3 is connected with one end of resistance R4, resistance R4's
One end of the other end, one end of resistance R15 and electric capacity C5 is all connected with the negative input of amplifier U4, another of resistance R15
End be all connected with the outfan of amplifier U4 with the other end of electric capacity C5, the electrode input end of amplifier U4, one end of resistance R16 and
One end of electric capacity C4 is all connected with+5V power supply, the other end of resistance R16 and the equal ground connection of the other end of electric capacity C4.
A kind of acquiring and processing method of high speed acquisition board based on electronic filtering techniques, the method includes:
(1) signal pre-treatment
The sawtooth signal that collection plate receiving transducer is collected, after preamplifier amplifies, is transferred to follower,
The driving force making its sawtooth waveforms is improved, and is then passed through peaker, and sawtooth waveforms, after peaker, forms negative finger
Number ripple；Negative exponent ripple is amplified by negative exponent ripple through first stage amplifier and two-stage amplifier；Negative exponent ripple is put through two grades
After great, then through sign-changing amplifier so that it is negative exponent waveform becomes positive exponent ripple；
(2) analog digital conversion and filtering molding
The positive exponent ripple that front end is exported by analog-digital converter is converted to digital signal through over sampling, quantization, cataloged procedure；
The digital signal that analog-digital converter exports is filtered shaping and piling up identifying by FPGA；
Pile up identify in, if judge signal there occurs pulse pile-up and can spectrum unscrambling, enter step (3)；If judging, signal is not
Impulsing is piled up and is then directly entered step (4)；If judge signal there occurs pulse pile-up and can not spectrum unscrambling, abandoned；
(3) spectrum unscrambling computing
By impulsing pile up and can spectrum unscrambling data transmit to GPU, GPU carry out spectrum unscrambling computing, described spectrum unscrambling computing
Comprise the steps:
(3.1) spectrum unscrambling calculates
There is the exponential damping part of several pulses piled up in matching respectively, obtains fitted trend line；
(3.2) baseline restorer, amplitude extraction, amplitude adjust
The recovery of baseline mainly has two kinds of methods: 1. counting rate is less than 105During cps, determine that a number of baseline clicks on
Row weighted average, obtains baseline position；2. when counting rate is more than 105During cps, owing to determining that the difficulty of baseline point becomes big, by arteries and veins
Rushing signal deduction, remaining is baseline point, is weighted average, obtains baseline position.
Amplitude is extracted: extracting the amplitude of several pulses that accumulation occurs, the amplitude of described pulse is the pole of pulse signal
Big value；
Amplitude adjusts: the first pulse fit line is the first impulse waveform after spectrum unscrambling, and the second impulse wave after spectrum unscrambling
Shape is the second pulse fit line and the difference of the first pulse fit line；The 3rd impulse waveform after spectrum unscrambling is the 3rd pulse fit line
With the difference of first and second pulse fit line, the like can be represented by the formula:
In formula: U (t)iFor the amplitude of i-th pulse after spectrum unscrambling；u(t)iAmplitude for i-th pulse；ubT () is baseline electricity
Pressure.
(4) when the non-impulsing of FPGA is piled up or when GPU impulsing piles up, by the pulse information file that processed by
Depositor is transmitted to client through ARM chip by serial ports, and client sends instruction to FPGA or GPU simultaneously, controls pulse letter
Number processing procedure；Two-way communication is carried out by network, for being transmitted extremely by spectrogram information file between client and server
Server, by destination file transmit to client.
Further, described filtering is configured to gaussian filtering shaping, matched filtering shaping or trapezoidal filtering shaping.
Further, described filtering shaping includes a fast passage and a slow channel.
Further, described fast passage is used for obtaining pulse interval, and this time interval is used for piling up type and judges；With
Time obtain fast channel counts rate, for correction of the count rate；Described slow channel is used for the amplitude that realizes and extracts and baseline restorer, Jin Erjin
Line amplitude adjusts.
Further, pile up identify in, described judgement signal there occurs pulse pile-up and can the concrete judge process of spectrum unscrambling such as
Under:
Whether impulsing is piled up, and depends on time difference Δ ti and the i & lt pulse of i+1 subpulse and i & lt pulse
Persistent period ti, if Δ ti >=ti, non-impulsing is piled up；If Δ ti ＜ ti, there occurs pulse pile-up；Whether pulse pile-up
Can depend on the size of Δ ti with spectrum unscrambling, Δ ti the least spectrum unscrambling difficulty is the biggest, and accuracy is the poorest, otherwise spectrum unscrambling difficulty is the least, accurate
Really property is the highest.
Further, described a number of baseline point is the arbitrfary point numerical value between 1024-16384.
The beneficial effects of the present invention is: making full use of GPU and support Floating-point Computation, programmability is strong；Multithreading calculates, meter
Calculation speed is fast；The advantages such as data transmission bauds is fast.Reliable hardware foundation, energy of the present invention is provided for solving pulse pile-up problem
Enough crack the technological difficulties that pulse pile-up processes, improve pulse signal utilization rate, final lifting system accuracy of detection.Furthermore due to
GPU small volume, present invention can apply to various types of detectors in the fields such as core medical treatment, core geological prospecting, industrial detection
Device, range is wider.
Accompanying drawing explanation
The present invention is described further with embodiment below in conjunction with the accompanying drawings.
Fig. 1 is the workflow diagram of the present invention；
Fig. 2 is pulse pile-up schematic diagram, in figure: 1 piles up for dipulse；2 is three pulse pile-ups；3 is four pulse pile-ups；
Fig. 3 is the graph of relation of actual count rate and effective counter rate；
The circuit diagram that Fig. 4 is follower and peaker is connected to be constituted；
Fig. 5 be firsts and seconds amplifying circuit be connected constitute circuit diagram；
Fig. 6 is inverting amplifier circuit figure；
Fig. 7 is the overall schematic of Fig. 4,5,6；
Fig. 8 is the sawtooth waveforms collected of popping one's head in the embodiment of the present invention；
Fig. 9 is the negative exponent ripple formed after sawtooth waveforms passes through peaker；
Figure 10 is the negative exponent ripple schematic diagram after one-level is amplified；
Figure 11 is the negative exponent ripple schematic diagram after two grades of amplifications；
Figure 12 be reversely amplify after the positive exponent ripple schematic diagram that formed；
Figure 13 is the pulse schematic diagram that non-impulsing is piled up；
Figure 14 is pulse spectrum unscrambling schematic diagram；Δ t represents pulse interval, t1Represent the first pulse duration, t2Represent
The pulse pile-up time, if Δ t < t1, then impulsing is piled up.
Figure 15 is the pulse schematic diagram after superimposed pulses and spectrum unscrambling.
Detailed description of the invention
As it is shown in figure 1, a kind of high speed acquisition board based on electronic filtering techniques of the present invention, including ARM chip, client,
Server and be sequentially connected preamplifier, follower, peaker, first stage amplifier, two-stage amplifier, reversely amplify
Device, analog-digital converter (AD), field programmable gate array (FPGA), GPU；Described analog-digital converter is for the mould exported front end
Intend signal and be converted to digital signal through over sampling, quantization, cataloged procedure；Described FPGA is for exporting described analog-digital converter
Digital signal be filtered shape and pile up identify, by impulsing pile up and can spectrum unscrambling data transmit to GPU, GPU enter
Row spectrum unscrambling computing；Described FPGA and GPU is transmitted to client through ARM chip by serial ports, and client is sent out to FPGA or GPU simultaneously
Send instruction, the processing procedure of control wave；Two-way communication is carried out by network, for solving between client and server
The spectrogram information file that spectrum computing obtains transmits to server, transmits calculated for server analysis destination file to client
End.Server is calculated constituent content information by constituent content quantitative analysis algorithm, forms destination file.
As shown in Figure 4, a kind of embodiment of the circuit constituted that is connected with peaker for follower of the present invention, its bag
Include: signal acquiring board joint P1, resistance R1-R3, resistance R5, electric capacity C1 and amplifier U1；One end of signal acquiring board joint P1 with
One end of resistance R1 is connected, and the other end of resistance R1 is connected with the electrode input end of amplifier U1, one end of resistance R2 and amplifier U1
Negative input be connected, the other end of resistance R2 is connected with one end of resistance R3 after being connected with the outfan of amplifier U1, resistance
The other end of R3 is connected with one end of electric capacity C1, and the other end of electric capacity C1 is connected with one end of resistance R5, signal acquiring board joint
The other end of P1 and the equal ground connection of the other end of resistance R5；The positive and negative power input of amplifier U1 connects+5V and-5V power supply respectively.
As it is shown in figure 5, be a kind of embodiment of the circuit of first stage amplifier of the present invention and two-stage amplifier composition, it
Including: amplifier U2, amplifier U3, electric capacity C2, electric capacity C3, resistance R6-R13, channel to channel adapter U5 and channel to channel adapter U6；Electric capacity C1
It is connected with the electrode input end of amplifier U2 with the common port of resistance R5, the channel output end of channel to channel adapter U5 and the one of electric capacity C2
End is connected with the negative input of amplifier U2 after being connected, and the other end of electric capacity C2 is connected with the gain compensation port of amplifier U2；Logical
One end of the first passage input port resistance R6 of track selector U5 is connected, the second channel input port D2 of channel to channel adapter U5
Being connected with one end of resistance R7, one end of third channel input port D3 and the resistance R13 of channel to channel adapter U5 is connected, and passage selects
The one end of fourth lane input port D1 and the resistance R8 selecting device U5 is connected, the other end of resistance R6, the other end of resistance R7, electricity
The outfan of the resistance other end of R13, the other end of resistance R8 and amplifier U2 is all connected with the electrode input end mouth of amplifier U2；
The channel output end of channel to channel adapter U6 is connected with the negative input of amplifier U3 after being connected with one end of electric capacity C3,
The other end of electric capacity C3 is connected with the gain compensation port of amplifier U3；The first passage input port D1 of channel to channel adapter U6 and electricity
One end of resistance R9 is connected, and one end of second channel input port D2 and the resistance R10 of channel to channel adapter U6 is connected, channel to channel adapter
One end of third channel input port D3 and the resistance R11 of U6 is connected, the fourth lane input port D1 of channel to channel adapter U6 with
One end of resistance R12 be connected, the other end of resistance R9, the other end of resistance R10, the other end of resistance R111, resistance R12 another
The outfan of one end and amplifier U3 is all connected with the electrode input end mouth of amplifier U2.
As shown in Figure 6, for a kind of embodiment of sign-changing amplifier of the present invention, it includes: amplifier U4, resistance R4, electricity
Resistance R14-R16, electric capacity C4 and electric capacity C5；The common port of resistance R9, resistance R10, resistance R111, resistance R12 and amplifier U3 with
One end of resistance R4 is connected, one end of the other end of resistance R4, one end of resistance R15 and electric capacity C5 all with the negative pole of amplifier U4
Input is connected, and the other end of resistance R15 is all connected with the outfan of amplifier U4 with the other end of electric capacity C5, the positive pole of amplifier U4
One end of input, one end of resistance R16 and electric capacity C4 is all connected with+5V power supply, the other end of resistance R16 and electric capacity C4's
The equal ground connection of the other end.
Fig. 7 is that follower of the present invention, peaker, first stage amplifier, two-stage amplifier, sign-changing amplifier are sequentially connected structure
The circuit diagram become.
A kind of acquiring and processing method of high speed acquisition board based on electronic filtering techniques, the method includes:
(1) signal pre-treatment
The sawtooth signal that collection plate receiving transducer is collected, after preamplifier amplifies, is transferred to follower,
The driving force making its sawtooth waveforms is improved, and is then passed through peaker, and sawtooth waveforms, after peaker, forms negative finger
Number ripple；Negative exponent ripple is amplified by negative exponent ripple through first stage amplifier and two-stage amplifier；Negative exponent ripple is put through two grades
After great, then through sign-changing amplifier so that it is negative exponent waveform becomes positive exponent ripple；
(2) analog digital conversion and filtering molding
The positive exponent ripple that front end is exported by analog-digital converter is converted to digital signal through over sampling, quantization, cataloged procedure；
The digital signal that analog-digital converter exports is filtered shaping and piling up identifying by FPGA；
Described filtering shaping can be that gaussian filtering shapes, matched filtering shaping or trapezoidal filtering shape, described in be filtered into
Shape includes a fast passage and a slow channel；Described fast passage is used for obtaining pulse interval, and this time interval is used for heap
Long-pending type judges；Obtain fast channel counts rate, for correction of the count rate simultaneously；Described slow channel is used for the amplitude that realizes and extracts and base
Line recovers, and then the amplitude of carrying out adjustment.
Pile up identify in, described judgement signal there occurs pulse pile-up and can the concrete judge process of spectrum unscrambling as follows:
Whether impulsing is piled up, and depends on time difference Δ ti and the i & lt pulse of i+1 subpulse and i & lt pulse
Persistent period ti, if Δ ti >=ti, non-impulsing is piled up；If Δ ti ＜ ti, there occurs pulse pile-up；Whether pulse pile-up
Can depend on the size of Δ ti with spectrum unscrambling, Δ ti the least spectrum unscrambling difficulty is the biggest, and accuracy is the poorest, otherwise spectrum unscrambling difficulty is the least, accurate
Really property is the highest.
Pile up identify in, if judge signal there occurs pulse pile-up and can spectrum unscrambling, enter step (3)；If judging, signal is not
Impulsing is piled up and is then directly entered step (4)；If judge signal there occurs pulse pile-up and can not spectrum unscrambling, abandoned；
(3) spectrum unscrambling computing
By impulsing pile up and can spectrum unscrambling data transmit to GPU, GPU carry out spectrum unscrambling computing, described spectrum unscrambling computing
Comprise the steps (as a example by the spectrum unscrambling that dipulse is piled up):
(3.1) there is the exponential damping part (as shown in Figure 2) of several pulses piled up in matching respectively, and general employing is double
Exponential fitting, such as formula (1), naturally it is also possible to use other various approximating methods；
U (t)=a exp (bt)-c exp (dt) (1)
In formula: a, b, c, d are fitting coefficient；U (t) is amplitude；T is the time；
(3.2) baseline restorer, amplitude extraction, amplitude adjust
The recovery of baseline mainly has two kinds of methods: 1. counting rate is less than 105During cps, determine that a number of baseline clicks on
Row weighted average, obtains baseline position；2. when counting rate is more than 105During cps, owing to determining that the difficulty of baseline point becomes big, by arteries and veins
Rushing signal deduction, remaining is baseline point, is weighted average, obtains baseline position.The most a number of baseline point one
As be the arbitrfary point numerical value between 1024-16384.
Amplitude is extracted: extracting the amplitude of several pulses that accumulation occurs, the amplitude of described pulse is the pole of pulse signal
Big value；
Amplitude adjusts: the amplitude extracted due to previous step (amplitude extraction) is the amplitude not considering pulse pile-up, and is
Eliminating pulse pile-up and the impact of amplitude need to carry out amplitude adjustment, amplitude adjusts and extracts based on previous step (amplitude extraction)
The baseline position that amplitude and upper previous step (baseline restorer) obtain.
First pulse fit line is the first impulse waveform after spectrum unscrambling, and the second impulse waveform after spectrum unscrambling is the second arteries and veins
Rush fit line and the difference of the first pulse fit line；The 3rd impulse waveform after spectrum unscrambling is the 3rd pulse fit line and first and second
The difference of pulse fit line, can be represented by the formula:
U (t) in formulaiThe amplitude of i-th pulse after spectrum unscrambling；
u(t)iThe amplitude of i-th pulse；
ub(t) baseline voltage.
(4) when the non-impulsing of FPGA is piled up or when GPU impulsing piles up, by the pulse information file that processed by
Depositor is transmitted to client through ARM chip by serial ports, and client sends instruction to FPGA or GPU simultaneously, controls pulse letter
Number processing procedure；Two-way communication is carried out by network (3G, 4G, WiFi), for being believed by spectrogram between client and server
Breath file transmits to server, transmits destination file to client.
Claims (10)
1. a high speed acquisition board based on electronic filtering techniques, it is characterised in that include ARM chip, client, server and
The preamplifier that is sequentially connected, follower, peaker, first stage amplifier, two-stage amplifier, sign-changing amplifier, modulus turn
Parallel operation, FPGA, GPU etc.；The analogue signal that described analog-digital converter is used for exporting front end is through over sampling, quantization, cataloged procedure
Be converted to digital signal；Described FPGA knows for being filtered the digital signal that described analog-digital converter exports shaping and piling up
Not, by impulsing pile up and can spectrum unscrambling data transmit to GPU, GPU carry out spectrum unscrambling computing；Described FPGA and GPU passes through
Serial ports transmits to client through ARM chip, and client sends instruction, the process of control wave to FPGA or GPU simultaneously
Journey；Carry out two-way communication by network between client and server, pass for the spectrogram information file that spectrum unscrambling computing is obtained
Transport to server, calculated for server analysis destination file is transmitted to client.
High speed acquisition board based on electronic filtering techniques the most according to claim 1, it is characterised in that described follower and
Peaker be connected constitute circuit include: signal acquiring board joint P1, resistance R1-R3, resistance R5, electric capacity C1 and amplifier U1；
One end of signal acquiring board joint P1 is connected with one end of resistance R1, the electrode input end phase of the other end of resistance R1 and amplifier U1
Even, one end of resistance R2 is connected with the negative input of amplifier U1, after the other end of resistance R2 is connected with the outfan of amplifier U1
Being connected with one end of resistance R3, the other end of resistance R3 is connected with one end of electric capacity C1, and the other end of electric capacity C1 is with resistance R5's
One end is connected, the other end of signal acquiring board joint P1 and the equal ground connection of the other end of resistance R5；The positive and negative power supply input of amplifier U1
End connects+5V and-5V power supply respectively.
High speed acquisition board based on electronic filtering techniques the most according to claim 2, it is characterised in that described one-level is amplified
The circuit that device and two-stage amplifier are constituted includes: amplifier U2, amplifier U3, electric capacity C2, electric capacity C3, resistance R6-R13, channel selecting
Device U5 and channel to channel adapter U6；Electric capacity C1 is connected with the electrode input end of amplifier U2 with the common port of resistance R5, channel to channel adapter
The channel output end of U5 is connected with the negative input of amplifier U2 after being connected with one end of electric capacity C2, the other end of electric capacity C2 and fortune
The gain compensation port putting U2 is connected；One end of the first passage input port resistance R6 of channel to channel adapter U5 is connected, and passage selects
The one end of second channel input port D2 and the resistance R7 selecting device U5 is connected, the third channel input port D3 of channel to channel adapter U5
Being connected with one end of resistance R13, one end of fourth lane input port D1 and the resistance R8 of channel to channel adapter U5 is connected, resistance R6
The other end, the other end of resistance R7, the other end of resistance R13, the other end of resistance R8 and amplifier U2 outfan all with
The electrode input end mouth of amplifier U2 is connected；
The channel output end of channel to channel adapter U6 is connected with the negative input of amplifier U3 after being connected with one end of electric capacity C3, electric capacity
The other end of C3 is connected with the gain compensation port of amplifier U3；The first passage input port D1 and resistance R9 of channel to channel adapter U6
One end be connected, one end of second channel input port D2 and the resistance R10 of channel to channel adapter U6 is connected, channel to channel adapter U6's
One end of third channel input port D3 and resistance R11 is connected, the fourth lane input port D1 of channel to channel adapter U6 and resistance
One end of R12 is connected, the other end of resistance R9, the other end of resistance R10, the other end of resistance R111, the other end of resistance R12
And the outfan of amplifier U3 is all connected with the electrode input end mouth of amplifier U2.
High speed acquisition board based on electronic filtering techniques the most according to claim 3, it is characterised in that described reverse amplification
Device includes: amplifier U4, resistance R4, resistance R14-R16, electric capacity C4 and electric capacity C5；Resistance R9, resistance R10, resistance R111, resistance
The common port of R12 and amplifier U3 is connected with one end of resistance R4, the other end of resistance R4, one end of resistance R15 and electric capacity
One end of C5 is all connected with the negative input of amplifier U4, the other end of resistance R15 and the other end of electric capacity C5 all with amplifier U4
Outfan be connected, one end of the electrode input end of amplifier U4, one end of resistance R16 and electric capacity C4 is all connected with+5V power supply,
The other end of resistance R16 and the equal ground connection of the other end of electric capacity C4.
5. the acquiring and processing method of a high speed acquisition board based on electronic filtering techniques, it is characterised in that the method includes:
(1) signal pre-treatment
The sawtooth signal that collection plate receiving transducer is collected, after preamplifier amplifies, is transferred to follower so that it is
The driving force of sawtooth waveforms is improved, and is then passed through peaker, and sawtooth waveforms, after peaker, forms negative exponent
Ripple；Negative exponent ripple is amplified by negative exponent ripple through first stage amplifier and two-stage amplifier；Negative exponent ripple is through two grades of amplifications
After, then through sign-changing amplifier so that it is negative exponent waveform becomes positive exponent ripple；
(2) analog digital conversion and filtering molding
The positive exponent ripple that front end is exported by analog-digital converter is converted to digital signal through over sampling, quantization, cataloged procedure；FPGA will
The digital signal of analog-digital converter output is filtered shaping and piling up identifying；
Pile up identify in, if judge signal there occurs pulse pile-up and can spectrum unscrambling, enter step (3)；If judging, signal does not occurs
Pulse pile-up is then directly entered step (4)；If judge signal there occurs pulse pile-up and can not spectrum unscrambling, abandoned；
(3) spectrum unscrambling computing
By impulsing pile up and can spectrum unscrambling data transmit to GPU, GPU carry out spectrum unscrambling computing, described spectrum unscrambling computing includes
Following steps:
(3.1) spectrum unscrambling calculates
There is the exponential damping part of several pulses piled up in matching respectively, obtains fitted trend line.
(3.2) baseline restorer, amplitude extraction, amplitude adjust
The recovery of baseline mainly has two kinds of methods: 1. counting rate is less than 105During cps, determine that a number of baseline point is weighted
Averagely, baseline position is obtained；2. when counting rate is more than 105During cps, owing to determining that the difficulty of baseline point becomes big, by pulse signal
Deduction, remaining is baseline point, is weighted average, obtains baseline position.
Amplitude is extracted: extracting the amplitude of several pulses that accumulation occurs, the amplitude of described pulse is the maximum of pulse signal；
Amplitude adjusts: the first pulse fit line is the first impulse waveform after spectrum unscrambling, and the second impulse waveform after spectrum unscrambling is
Second pulse fit line and the difference of the first pulse fit line；The 3rd impulse waveform after spectrum unscrambling is the 3rd pulse fit line and
One, the difference of two pulse fit lines, the like can be represented by the formula:
In formula: U (t)iFor the amplitude of i-th pulse after spectrum unscrambling；u(t)iAmplitude for i-th pulse；ubT () is baseline voltage.
(4) when the non-impulsing of FPGA is piled up or when GPU impulsing piles up, by the pulse information file that processed by depositing
Device is transmitted to client through ARM chip by serial ports, and client sends instruction to FPGA or GPU simultaneously, control wave
Processing procedure；Two-way communication is carried out by network, for by spectrogram information file transmission extremely service between client and server
Device, by destination file transmit to client.
The acquiring and processing method of high speed acquisition board based on electronic filtering techniques the most according to claim 5, its feature exists
In, described filtering is configured to gaussian filtering shaping, matched filtering shaping or trapezoidal filtering and shapes.
The acquiring and processing method of high speed acquisition board based on electronic filtering techniques the most according to claim 6, its feature exists
In, described filtering shaping includes a fast passage and a slow channel.
The acquiring and processing method of high speed acquisition board based on electronic filtering techniques the most according to claim 7, its feature exists
In, described fast passage is used for obtaining pulse interval, and this time interval is used for piling up type and judges；Obtain fast passage meter simultaneously
Digit rate, for correction of the count rate；Described slow channel is used for the amplitude that realizes and extracts and baseline restorer, and then the amplitude of carrying out adjustment.
The acquiring and processing method of high speed acquisition board based on electronic filtering techniques the most according to claim 8, its feature exists
In, pile up identify in, described judgement signal there occurs pulse pile-up and can the concrete judge process of spectrum unscrambling as follows:
Whether impulsing is piled up, and depends on time difference Δ ti and the i & lt pulse persistance of i+1 subpulse and i & lt pulse
Time ti, if Δ ti >=ti, non-impulsing is piled up；If Δ ti ＜ ti, there occurs pulse pile-up；Pulse pile-up is the most permissible
Spectrum unscrambling depends on the size of Δ ti, and Δ ti the least spectrum unscrambling difficulty is the biggest, and accuracy is the poorest, otherwise spectrum unscrambling difficulty is the least, accuracy
The highest.
The acquiring and processing method of high speed acquisition board based on electronic filtering techniques the most according to claim 8, its feature exists
In, described a number of baseline point is the arbitrfary point numerical value between 1024-16384.
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| CN112764082A (en) * | 2020-12-08 | 2021-05-07 | 武汉第二船舶设计研究所(中国船舶重工集团公司第七一九研究所) | FPGA-based nuclear pulse digital forming sampling method |
| CN112764082B (en) * | 2020-12-08 | 2023-05-23 | 武汉第二船舶设计研究所(中国船舶重工集团公司第七一九研究所) | FPGA-based nuclear pulse digital forming sampling method |
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