US20180130830A1 - Ltps array substrate and method for producing the same - Google Patents

Ltps array substrate and method for producing the same Download PDF

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US20180130830A1
US20180130830A1 US15/863,988 US201815863988A US2018130830A1 US 20180130830 A1 US20180130830 A1 US 20180130830A1 US 201815863988 A US201815863988 A US 201815863988A US 2018130830 A1 US2018130830 A1 US 2018130830A1
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layer
substrate
gate
forming
insulating layer
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US15/863,988
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Cong Wang
Peng DU
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Assigned to SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. reassignment SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DU, PENG, WANG, CONG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Definitions

  • the present invention relates to the field of display technology, and more particularly, to a low temperature poly-silicon (LTPS) array substrate and a method for producing the LTPS array substrate.
  • LTPS low temperature poly-silicon
  • an LTPS array substrate and a method for producing the LTPS array substrate is proposed by the embodiment of the present invention for the purpose of reducing the masks used in the LTPS technology in types and in numbers.
  • a method for producing a low temperature poly-silicon (LTPS) array substrate comprises: forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one in which an upper surface of the first insulating layer is a plane; exposing one side of the substrate on the opposite side of the gate for preserving the positive photoresist layer disposed on a first section disposed right above the gate only; injecting first impurity ions into the semiconductor layer outside the first section; exposing one side of the substrate on the opposite side of the gate for forming the positive photoresist layer disposed on a second section disposed right above the gate, and the second section being smaller than the first section; injecting second impurity ions into the semiconductor layer outside the second section; removing the positive photoresist layer disposed on the second section to form a polycrystalline silicon layer;
  • TFT thin-film transistor
  • the method further comprises: forming a buffer layer on the substrate without being covered by the gate and forming a plane using an upper surface of the buffer layer and an upper surface of the gate.
  • a step of forming the buffer layer on the substrate without being covered by the gate comprises: forming the buffer layer and a negative photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for removing the negative photoresist layer disposed right above the gate; removing the buffer layer disposed right above the gate, and preserving the buffer layer disposed on the substrate without being covered by the gate.
  • the first impurity ions are N+ type impurity ions
  • the second impurity ions are N ⁇ type impurity ions.
  • a method for producing a low temperature poly-silicon (LTPS) array substrate comprises: forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one in which an upper surface of the first insulating layer is a plane; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a second insulating layer on the substrate of the polycrystalline silicon layer, and forming a first contact hole in the second insulating layer for exposing both sides of the polycrystalline silicon layer; forming a source and a drain of the TFT on the second insulating layer so that the source and the drain is electrically connected to the polycrystalline silicon layer via the first contact hole.
  • TFT thin-film transistor
  • the method further comprises: forming a buffer layer on the substrate without being covered by the gate and forming a plane using an upper surface of the buffer layer and an upper surface of the gate.
  • a step of forming the buffer layer on the substrate without being covered by the gate comprises: forming the buffer layer and a negative photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for removing the negative photoresist layer disposed right above the gate; removing the buffer layer disposed right above the gate, and preserving the buffer layer disposed on the substrate without being covered by the gate.
  • a step of exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer comprises: exposing one side of the substrate on the opposite side of the gate for preserving the positive photoresist layer disposed on a first section disposed right above the gate only; injecting first impurity ions into the semiconductor layer outside the first section; exposing one side of the substrate on the opposite side of the gate for forming the positive photoresist layer disposed on a second section disposed right above the gate, and the second section being smaller than the first section; injecting second impurity ions into the semiconductor layer outside the second section; removing the positive photoresist layer disposed on the second section.
  • the first impurity ions are N+ type impurity ions
  • the second impurity ions are N ⁇ type impurity ions.
  • a step of exposing one side of the substrate on the opposite side of the gate for forming the polycrystalline silicon layer comprises: exposing one side of the substrate on the opposite side of the gate for preserving the positive photoresist layer disposed on a first section disposed right above the gate only; injecting P type impurity ions into the semiconductor layer outside the first section; exposing one side of the substrate on the opposite side of the gate for forming the positive photoresist layer disposed on a second section disposed right above the gate, and the second section being smaller than the first section; removing the positive photoresist layer disposed on the second section.
  • a step comprises: forming a plain passivation layer on a source and drain electrode layer, which is fabricated from the source and the drain, and forming a second contact hole in the plain passivation layer for exposing surface of the drain; forming a common electrode of the LTPS array substrate on one side of the plain passivation layer where the second contact hole is far away from the TFT; forming a third insulating layer on the plain passivation layer and the common electrode layer, wherein the third insulating layer does not cover the second contact hole; forming a pixel electrode on the plain passivation layer and electrically connected to the drain via the second contact hole.
  • a low temperature poly-silicon (LTPS) array substrate comprises: a substrate; a gate, disposed on the substrate; forming a first insulating layer, a polycrystalline silicon layer, and a second insulating layer on the substrate one by one in which a first contact hole is formed in the second insulating layer; a source and a drain, disposed on the second insulating layer so that the source and the drain electrically connected to the polycrystalline silicon layer via the first contact hole; a plain passivation layer, disposed on a source and drain electrode layer fabricated from the source and the drain, and a second contact hole formed in the plain passivation layer for exposing surface of the drain; a third insulating layer, disposed on the plain passivation layer, without covering the second contact hole; a pixel electrode, disposed on the plain passivation layer and electrically connected to the drain via the second contact hole.
  • LTPS low temperature poly-silicon
  • the LTPS array substrate further comprises a buffer layer, the buffer layer is disposed on the substrate without being covered by the gate, and an upper surface of the buffer layer and an upper surface of the gate form a plane.
  • the LTPS array substrate further comprises a common electrode, and the common electrode is formed on one side of the plain passivation layer where the second contact hole is far away from the TFT.
  • the fact about the LTPS array substrate and the method for producing the LTPS array substrate proposed by the present invention is that one side of a substrate on the opposite side of a gate is exposed for forming a polycrystalline silicon layer. In other words, an opaque gate is exposed for forming a polycrystalline silicon layer. It is unnecessary to use any masks in producing polycrystalline silicon layers so the use of masks in types and in numbers in the LTPS technology will be reduced. So, both of the processes and the production costs are reduced.
  • FIG. 1 is a flow chart of a method for producing an LTPS array substrate according to a preferred embodiment of the present invention.
  • FIG. 2 shows a process of forming a gate according to the present invention.
  • FIG. 3 shows a process of forming a first insulating layer, a semiconductor layer, and a positive photoresist formed on the substrate according to the present invention.
  • FIG. 4 shows a process of forming a polycrystalline silicon layer according to the present invention.
  • FIG. 5 shows a process of forming a second insulating layer according to the present invention.
  • FIG. 6 shows a process of forming a source and a drain according to the present invention.
  • FIG. 7 shows a process of forming a pixel electrode according to the present invention.
  • FIG. 1 is a flow chart of a method for producing an LTPS array substrate according to one embodiment of the present invention. The method comprises following steps:
  • Step 11 forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate.
  • TFT thin-film transistor
  • the substrate 21 is used for forming the LTPS array substrate of an LCD panel.
  • the substrate 21 can be a glass substrate, a plastic substrate, or a flexible substrate.
  • a first metallic layer is formed on the substrate 21 and the first metallic layer is exposed through a first mask in this embodiment.
  • the exposed first metallic layer is patterned after being developed and etched.
  • a gate 22 is formed.
  • the first metallic layer is etched with etching liquid comprising phosphoric acid, nitric acid, acetic acid, and deionized water. Certainly, the first metallic layer can undergo dry etching as well.
  • the gate 22 can be also acquired through other methods in this embodiment such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, vacuum evaporation deposition, or low pressure chemical vapor deposition (LP-CVD).
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • sputtering vacuum evaporation deposition
  • LP-CVD low pressure chemical vapor deposition
  • the method of deposition is not confined in the specification.
  • the gate 22 with a default pattern is formed on the substrate 21 directly.
  • the first metallic layer is fabricated from metal such as aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), or cuprum (Cu).
  • the first metallic layer is fabricated from a metallic oxide, such as titanium oxide, or a metallic alloy or other conducting materials.
  • Step 12 forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one in which an upper surface of the first insulating layer is a plane.
  • a buffer layer 23 needs to be formed on the substrate 21 without being covered by the gate 22 before a first insulating layer 25 , a semiconductor layer 26 , and a positive photoresist layer 27 are formed in this embodiment.
  • the concrete processes are described below while it does not mean that the processes are limited.
  • the buffer layer 23 and the negative photoresist layer 24 are formed on the substrate 21 of the gate 22 one by one.
  • the buffer layer 23 can be a SiN x layer, a SiO x layer or a combination of other non-conducting materials.
  • the buffer layer 23 is used for preventing upward spreading of the impurity in the substrate 21 in the following processes so that the quality of an LTPS layer which will be formed in the following processes will not be affected.
  • the SiN x layer and the SiO x layer are deposited through CVD, PECVD, sputtering, vacuum evaporation deposition, or LP-CVD. The method of deposition is not confined in the specification.
  • the negative photoresist layer 24 disposed right above the gate 22 is not exposed under the shelter of the gate 22 so the negative photoresist layer 24 can be removed with ash after being developed.
  • the remaining negative photoresist layer 24 is peeled off.
  • the buffer layer 23 disposed right above the gate 22 is etched and removed. Therefore, the buffer layer 23 without being covered by the gate 22 is preserved.
  • Step 13 exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer.
  • one side of the substrate 21 on the opposite side of the gate 22 is exposed.
  • the positive photoresist layer 27 disposed on the first section Q 1 of the gate 22 is not exposed under the shelter of the gate 22 so the positive photoresist layer 27 can be preserved after being developed.
  • the positive photoresist layer 27 without being exposed under the shelter of the gate 22 can be removed with ash after being developed. Therefore, only the positive photoresist layer 27 is preserved on the first section Q 1 disposed right above the gate 22 is preserved.
  • first impurity ions are injected into the semiconductor layer 26 outside the first section Q 1 .
  • the semiconductor layer 26 is heavily doped.
  • the intensity of this exposure is larger than the intensity of exposure on the positive photoresist layer 27 formed on the first section Q 1 . So the positive photoresist layer 27 disposed on both sides of the first section Q 1 is removed. So the positive photoresist layer 27 of the second section Q 2 is formed right above the gate 22 . The second section Q 2 is smaller than the first section Q 1 .
  • second impurity ions are injected into the semiconductor layer 26 outside the second section Q 2 .
  • the semiconductor layer 26 is softly doped.
  • the first impurity ions in this embodiment can be N+ type impurity ions, and correspondingly, the second impurity ion can be N ⁇ type impurity ions. While the first impurity ion is P+ type impurity ions, the doping of the second impurity ion is unnecessary. In other words, soft doping is unnecessary.
  • a polycrystalline silicon layer 28 with a default pattern is formed through exposure, development, and etching through a second mask, as shown in FIG. 4 .
  • Step S 14 forming a second insulating layer on the substrate of the polycrystalline silicon layer, and forming a first contact hole in the second insulating layer for exposing both sides of the polycrystalline silicon layer.
  • a second insulating layer 29 covers the polycrystalline silicon layer 28 and the first insulating layer 25 .
  • a first contact hole O 1 is formed through exposure, development, and etching through a third mask in this embodiment, as shown in FIG. 5 .
  • Step S 15 forming a source and a drain of the TFT on the second insulating layer so that the source and the drain can be electrically connected to the polycrystalline silicon layer via the first contact hole.
  • a source S and a drain D of the TFT are formed through exposure, development, and etching through a fourth mask in this embodiment, as shown in FIG. 6 .
  • one side of the substrate 21 on the opposite side of the gate 22 is exposed.
  • the opaque gate 22 is exposed for forming the polycrystalline silicon layer 28 without using any masks. Therefore, the type and number of masks for producing the conventional LTPS array panel is reduced. It not only simplifies the manufacture procedure but also reduces costs.
  • the method proposed by this embodiment of the present invention further comprises following steps:
  • the second contact hole O 2 is formed through exposure, development, and etching through a fifth mask.
  • the common electrode 31 with a default pattern is formed through exposure, development, and etching through a sixth mask.
  • the third insulating layer 32 with a default pattern is formed through exposure, development, and etching through a seventh mask. Furthermore, the third insulating layer 32 with a default pattern can be also formed through CVD, PECVD, sputtering, vacuum evaporation deposition, or LP-CVD directly. The method of deposition is not confined in the specification.
  • a pixel electrode 33 is formed on the plain passivation layer 30 .
  • the pixel electrode 33 is electrically connected to the drain D via the second contact hole O 2 .
  • the pixel electrode 33 with a default pattern is formed through exposure, development, and etching through an eighth mask.
  • the gate 22 of the TFT is correspondingly electrically connected to a gate wire formed on the substrate 21 (array substrate).
  • the source S of the TFT is correspondingly electrically connected to a data wire formed on the array substrate.
  • the gate wire and the data wire are vertically crossed and form a pixel display section where the pixel electrode 33 is disposed.
  • the present invention further proposes an LCD panel comprising the LTPS array panel as shown in FIG. 7 and an LCD.
  • the benefit is the same as what is described above.

Abstract

An LTPS array substrate and a method for producing the same are proposed. The method includes: forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a second insulating layer on the substrate of the polycrystalline silicon layer; forming a source and a drain of the TFT on the second insulating layer so that the source and the drain is electrically connected to the polycrystalline silicon layer via a contact hole. The method involves a reduced number of masks.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This is a divisional application of co-pending patent application Ser. No. 14/762,458, filed on Jul. 21, 2015, which is a national stage of PCT Application Number PCT/CN2015/081635, filed on Jun. 17, 2015, claiming foreign priority of Chinese patent application number 201510310280.0, filed on Jun. 8, 2015.
    • BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The present invention relates to the field of display technology, and more particularly, to a low temperature poly-silicon (LTPS) array substrate and a method for producing the LTPS array substrate.
    • 2. Description of Prior Art
  • Higher electron mobility is demonstrated in a liquid crystal display (LCD) adopting LTPS. The square of a thin film transistor (TFT) is actually smaller in this kind of LCD in which the aperture rate of a pixel is higher, and the brightness is larger. Anyway, power consumption and production costs are less using an LCD with LTPS. Owing to these features, the research on the LCD with LTPS is popular in LCD technology. However, the LTPS technology is sophisticated. It requires a lot of masks in various types to fabricate an array substrate (array substrate). Also, it needs many processes to produce an array substrate. Therefore, production costs are always high, which is a problem. To find ways to reduce the masks used in the LTPS technology in numbers and types requires the whole industry to work together.
    • SUMMARY OF THE INVENTION
  • In view of this, an LTPS array substrate and a method for producing the LTPS array substrate is proposed by the embodiment of the present invention for the purpose of reducing the masks used in the LTPS technology in types and in numbers.
  • According to a preferred embodiment of the present invention, a method for producing a low temperature poly-silicon (LTPS) array substrate, comprises: forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one in which an upper surface of the first insulating layer is a plane; exposing one side of the substrate on the opposite side of the gate for preserving the positive photoresist layer disposed on a first section disposed right above the gate only; injecting first impurity ions into the semiconductor layer outside the first section; exposing one side of the substrate on the opposite side of the gate for forming the positive photoresist layer disposed on a second section disposed right above the gate, and the second section being smaller than the first section; injecting second impurity ions into the semiconductor layer outside the second section; removing the positive photoresist layer disposed on the second section to form a polycrystalline silicon layer; forming a second insulating layer on the substrate of the polycrystalline silicon layer, and forming a first contact hole in the second insulating layer for exposing both sides of the polycrystalline silicon layer; forming a source and a drain of the TFT on the second insulating layer so that the source and the drain is electrically connected to the polycrystalline silicon layer via the first contact hole; forming a plain passivation layer on a source and drain electrode layer, which is fabricated from the source and the drain, and forming a second contact hole in the plain passivation layer for exposing surface of the drain; forming a common electrode of the LTPS array substrate on one side of the plain passivation layer where the second contact hole is far away from the TFT; forming a third insulating layer on the plain passivation layer and the common electrode layer, wherein the third insulating layer does not cover the second contact hole; and forming a pixel electrode on the plain passivation layer and electrically connected to the drain via the second contact hole.
  • Furthermore, before the insulating layer is formed on the substrate, the method further comprises: forming a buffer layer on the substrate without being covered by the gate and forming a plane using an upper surface of the buffer layer and an upper surface of the gate.
  • Furthermore, a step of forming the buffer layer on the substrate without being covered by the gate comprises: forming the buffer layer and a negative photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for removing the negative photoresist layer disposed right above the gate; removing the buffer layer disposed right above the gate, and preserving the buffer layer disposed on the substrate without being covered by the gate.
  • Furthermore, the first impurity ions are N+ type impurity ions, and the second impurity ions are N− type impurity ions.
  • According to another embodiment of the present invention, a method for producing a low temperature poly-silicon (LTPS) array substrate, comprises: forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one in which an upper surface of the first insulating layer is a plane; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a second insulating layer on the substrate of the polycrystalline silicon layer, and forming a first contact hole in the second insulating layer for exposing both sides of the polycrystalline silicon layer; forming a source and a drain of the TFT on the second insulating layer so that the source and the drain is electrically connected to the polycrystalline silicon layer via the first contact hole.
  • Furthermore, before the insulating layer is formed on the substrate, the method further comprises: forming a buffer layer on the substrate without being covered by the gate and forming a plane using an upper surface of the buffer layer and an upper surface of the gate.
  • Furthermore, a step of forming the buffer layer on the substrate without being covered by the gate comprises: forming the buffer layer and a negative photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for removing the negative photoresist layer disposed right above the gate; removing the buffer layer disposed right above the gate, and preserving the buffer layer disposed on the substrate without being covered by the gate.
  • Furthermore, a step of exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer comprises: exposing one side of the substrate on the opposite side of the gate for preserving the positive photoresist layer disposed on a first section disposed right above the gate only; injecting first impurity ions into the semiconductor layer outside the first section; exposing one side of the substrate on the opposite side of the gate for forming the positive photoresist layer disposed on a second section disposed right above the gate, and the second section being smaller than the first section; injecting second impurity ions into the semiconductor layer outside the second section; removing the positive photoresist layer disposed on the second section.
  • Furthermore, the first impurity ions are N+ type impurity ions, and the second impurity ions are N− type impurity ions.
  • Furthermore, a step of exposing one side of the substrate on the opposite side of the gate for forming the polycrystalline silicon layer comprises: exposing one side of the substrate on the opposite side of the gate for preserving the positive photoresist layer disposed on a first section disposed right above the gate only; injecting P type impurity ions into the semiconductor layer outside the first section; exposing one side of the substrate on the opposite side of the gate for forming the positive photoresist layer disposed on a second section disposed right above the gate, and the second section being smaller than the first section; removing the positive photoresist layer disposed on the second section.
  • Furthermore, after forming the source and the drain of the TFT on the second insulating layer, a step comprises: forming a plain passivation layer on a source and drain electrode layer, which is fabricated from the source and the drain, and forming a second contact hole in the plain passivation layer for exposing surface of the drain; forming a common electrode of the LTPS array substrate on one side of the plain passivation layer where the second contact hole is far away from the TFT; forming a third insulating layer on the plain passivation layer and the common electrode layer, wherein the third insulating layer does not cover the second contact hole; forming a pixel electrode on the plain passivation layer and electrically connected to the drain via the second contact hole.
  • According to another embodiment of the present invention, a low temperature poly-silicon (LTPS) array substrate, comprises: a substrate; a gate, disposed on the substrate; forming a first insulating layer, a polycrystalline silicon layer, and a second insulating layer on the substrate one by one in which a first contact hole is formed in the second insulating layer; a source and a drain, disposed on the second insulating layer so that the source and the drain electrically connected to the polycrystalline silicon layer via the first contact hole; a plain passivation layer, disposed on a source and drain electrode layer fabricated from the source and the drain, and a second contact hole formed in the plain passivation layer for exposing surface of the drain; a third insulating layer, disposed on the plain passivation layer, without covering the second contact hole; a pixel electrode, disposed on the plain passivation layer and electrically connected to the drain via the second contact hole.
  • Furthermore, the LTPS array substrate further comprises a buffer layer, the buffer layer is disposed on the substrate without being covered by the gate, and an upper surface of the buffer layer and an upper surface of the gate form a plane.
  • Furthermore, the LTPS array substrate further comprises a common electrode, and the common electrode is formed on one side of the plain passivation layer where the second contact hole is far away from the TFT.
  • The fact about the LTPS array substrate and the method for producing the LTPS array substrate proposed by the present invention is that one side of a substrate on the opposite side of a gate is exposed for forming a polycrystalline silicon layer. In other words, an opaque gate is exposed for forming a polycrystalline silicon layer. It is unnecessary to use any masks in producing polycrystalline silicon layers so the use of masks in types and in numbers in the LTPS technology will be reduced. So, both of the processes and the production costs are reduced.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a flow chart of a method for producing an LTPS array substrate according to a preferred embodiment of the present invention.
  • FIG. 2 shows a process of forming a gate according to the present invention.
  • FIG. 3 shows a process of forming a first insulating layer, a semiconductor layer, and a positive photoresist formed on the substrate according to the present invention.
  • FIG. 4 shows a process of forming a polycrystalline silicon layer according to the present invention.
  • FIG. 5 shows a process of forming a second insulating layer according to the present invention.
  • FIG. 6 shows a process of forming a source and a drain according to the present invention.
  • FIG. 7 shows a process of forming a pixel electrode according to the present invention.
    •  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • FIG. 1 is a flow chart of a method for producing an LTPS array substrate according to one embodiment of the present invention. The method comprises following steps:
  • Step 11: forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate.
  • Referring to FIG. 2, the substrate 21 is used for forming the LTPS array substrate of an LCD panel. The substrate 21 can be a glass substrate, a plastic substrate, or a flexible substrate.
  • A first metallic layer is formed on the substrate 21 and the first metallic layer is exposed through a first mask in this embodiment. The exposed first metallic layer is patterned after being developed and etched. Then, a gate 22 is formed. The first metallic layer is etched with etching liquid comprising phosphoric acid, nitric acid, acetic acid, and deionized water. Certainly, the first metallic layer can undergo dry etching as well.
  • Definitely, the gate 22 can be also acquired through other methods in this embodiment such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, vacuum evaporation deposition, or low pressure chemical vapor deposition (LP-CVD). The method of deposition is not confined in the specification. The gate 22 with a default pattern is formed on the substrate 21 directly. The first metallic layer is fabricated from metal such as aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), or cuprum (Cu). Or, the first metallic layer is fabricated from a metallic oxide, such as titanium oxide, or a metallic alloy or other conducting materials.
  • Step 12: forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one in which an upper surface of the first insulating layer is a plane.
  • Referring to FIG. 3 as well, a buffer layer 23 needs to be formed on the substrate 21 without being covered by the gate 22 before a first insulating layer 25, a semiconductor layer 26, and a positive photoresist layer 27 are formed in this embodiment. The concrete processes are described below while it does not mean that the processes are limited.
  • Firstly, the buffer layer 23 and the negative photoresist layer 24 are formed on the substrate 21 of the gate 22 one by one. The buffer layer 23 can be a SiNx layer, a SiOx layer or a combination of other non-conducting materials. The buffer layer 23 is used for preventing upward spreading of the impurity in the substrate 21 in the following processes so that the quality of an LTPS layer which will be formed in the following processes will not be affected. The SiNx layer and the SiOx layer are deposited through CVD, PECVD, sputtering, vacuum evaporation deposition, or LP-CVD. The method of deposition is not confined in the specification.
  • Next, one side of the substrate 21 on the opposite side of the gate 22 is exposed. The negative photoresist layer 24 disposed right above the gate 22 is not exposed under the shelter of the gate 22 so the negative photoresist layer 24 can be removed with ash after being developed.
  • Finally, the remaining negative photoresist layer 24 is peeled off. The buffer layer 23 disposed right above the gate 22 is etched and removed. Therefore, the buffer layer 23 without being covered by the gate 22 is preserved.
  • Step 13: exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer.
  • Referring to FIG. 4 as well, firstly, one side of the substrate 21 on the opposite side of the gate 22 is exposed. The positive photoresist layer 27 disposed on the first section Q1 of the gate 22 is not exposed under the shelter of the gate 22 so the positive photoresist layer 27 can be preserved after being developed. The positive photoresist layer 27 without being exposed under the shelter of the gate 22 can be removed with ash after being developed. Therefore, only the positive photoresist layer 27 is preserved on the first section Q1 disposed right above the gate 22 is preserved.
  • Next, first impurity ions are injected into the semiconductor layer 26 outside the first section Q1. In other words, conventionally, the semiconductor layer 26 is heavily doped.
  • Next, one side of the substrate 21 on the opposite side of the gate 22 is exposed. The intensity of this exposure is larger than the intensity of exposure on the positive photoresist layer 27 formed on the first section Q1. So the positive photoresist layer 27 disposed on both sides of the first section Q1 is removed. So the positive photoresist layer 27 of the second section Q2 is formed right above the gate 22. The second section Q2 is smaller than the first section Q1.
  • Further, second impurity ions are injected into the semiconductor layer 26 outside the second section Q2. In other words, conventionally, the semiconductor layer 26 is softly doped. The first impurity ions in this embodiment can be N+ type impurity ions, and correspondingly, the second impurity ion can be N− type impurity ions. While the first impurity ion is P+ type impurity ions, the doping of the second impurity ion is unnecessary. In other words, soft doping is unnecessary.
  • Finally, the positive photoresist layer 27 on the second section Q2 is removed. A polycrystalline silicon layer 28 with a default pattern is formed through exposure, development, and etching through a second mask, as shown in FIG. 4.
  • Step S14: forming a second insulating layer on the substrate of the polycrystalline silicon layer, and forming a first contact hole in the second insulating layer for exposing both sides of the polycrystalline silicon layer.
  • A second insulating layer 29 covers the polycrystalline silicon layer 28 and the first insulating layer 25. A first contact hole O1 is formed through exposure, development, and etching through a third mask in this embodiment, as shown in FIG. 5.
  • Step S15: forming a source and a drain of the TFT on the second insulating layer so that the source and the drain can be electrically connected to the polycrystalline silicon layer via the first contact hole.
  • A source S and a drain D of the TFT are formed through exposure, development, and etching through a fourth mask in this embodiment, as shown in FIG. 6.
  • As mentioned above, one side of the substrate 21 on the opposite side of the gate 22 is exposed. In other words, the opaque gate 22 is exposed for forming the polycrystalline silicon layer 28 without using any masks. Therefore, the type and number of masks for producing the conventional LTPS array panel is reduced. It not only simplifies the manufacture procedure but also reduces costs.
  • Referring to FIG. 7, the method proposed by this embodiment of the present invention further comprises following steps:
  • Forming a plain passivation layer 30 on a source and drain electrode layer, which is fabricated from the source S and the drain D, and forming a second contact hole O2 in the plain passivation layer 30 for exposing the surface of the gate D. The second contact hole O2 is formed through exposure, development, and etching through a fifth mask.
  • Forming a common electrode 31 of the LTPS array substrate on one side of the plain passivation layer 30 where the second contact hole O2 is far away from the TFT. The common electrode 31 with a default pattern is formed through exposure, development, and etching through a sixth mask.
  • Forming a third insulating layer 32 on the plain passivation layer 30 and the common electrode 31. The second contact hole O2 is not covered by the third insulating layer 32. The third insulating layer 32 with a default pattern is formed through exposure, development, and etching through a seventh mask. Furthermore, the third insulating layer 32 with a default pattern can be also formed through CVD, PECVD, sputtering, vacuum evaporation deposition, or LP-CVD directly. The method of deposition is not confined in the specification.
  • A pixel electrode 33 is formed on the plain passivation layer 30. The pixel electrode 33 is electrically connected to the drain D via the second contact hole O2. The pixel electrode 33 with a default pattern is formed through exposure, development, and etching through an eighth mask. Moreover, the gate 22 of the TFT is correspondingly electrically connected to a gate wire formed on the substrate 21 (array substrate). The source S of the TFT is correspondingly electrically connected to a data wire formed on the array substrate. The gate wire and the data wire are vertically crossed and form a pixel display section where the pixel electrode 33 is disposed.
  • The present invention further proposes an LCD panel comprising the LTPS array panel as shown in FIG. 7 and an LCD. The benefit is the same as what is described above.
  • The present disclosure is described in detail in accordance with the above contents with the specific preferred examples. However, this present disclosure is not limited to the specific examples. For the ordinary technical personnel of the technical field of the present disclosure, on the premise of keeping the conception of the present disclosure, the technical personnel can also make simple deductions or replacements, and all of which should be considered to belong to the protection scope of the present disclosure.

Claims (20)

What is claimed is:
1. A method for producing a low temperature poly-silicon (LTPS) array substrate, comprising:
forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate;
forming a buffer layer and a negative photoresist layer on the substrate one by one;
exposing one side of the substrate that is opposite to the gate to remove a portion of the negative photoresist layer that is located exactly above the gate;
removing a first portion of the buffer layer located above the gate such that a second portion of the buffer layer that is disposed on the substrate and away from the gate is preserved on substrate and the gate is exposed outside the buffer layer;
forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one in which an upper surface of the first insulating layer is a plane;
exposing one side of the substrate that is opposite to the gate to form a polycrystalline silicon layer through a process comprising the following sub-steps:
(1) exposing one side of the substrate that is opposite to the gate to remove a first portion of the positive photoresist layer such that a second portion of the positive photoresist layer that is located in a first section corresponding in position to the gate is preserved,
(2) injecting impurity ions into a portion of the semiconductor layer outside the first section, and
(3) completely removing the positive photoresist layer;
forming a second insulating layer on the substrate of the polycrystalline silicon layer such that first contact holes are formed in the second insulating layer to respectively expose two opposite ends of the polycrystalline silicon layer; and
forming a source and a drain of the TFT on the second insulating layer so that the source and the drain are electrically connected to the polycrystalline silicon layer via the first contact holes, respectively.
2. The method as claimed in claim 1, wherein the gate is formed by first forming a first metallic layer on the substrate and then patterning the first metallic layer.
3. The method as claimed in claim 2, wherein the first metallic layer is formed of a conducting material, which comprises one of a metal, a metal oxide, and a metal alloy.
4. The method as claimed in claim 3, wherein the metal comprises one of aluminum, molybdenum, titanium, chromium, and copper.
5. The method as claimed in claim 3, wherein the metal oxide comprises titanium oxide.
6. The method as claimed in claim 2, wherein the step of patterning the first metallic layer comprises etching the first metallic layer with an etching liquid comprising phosphoric acid, nitric acid, acetic acid, and deionized water.
7. The method as claimed in claim 1, wherein the gate is formed through direct deposition on the substrate.
8. The method as claimed in claim 1, wherein the buffer layer is formed of a material comprising one of silicon nitride and silicon oxide.
9. The method as claimed in claim 1, wherein the first portion of the buffer layer is removed through etching.
10. The method as claimed in claim 1, wherein the impurity ions are P type ions.
11. The method as claimed in claim 1, wherein the first portion of the buffer layer is removed through etching.
12. The method as claimed in claim 1 further comprising, after the step of forming the source and the drain of the TFT on the second insulating layer:
forming a passivation layer on the source and the drain electrode layer such that a second contact hole is formed in the passivation layer to expose a surface of the drain;
forming a common electrode on the passivation layer;
forming a third insulating layer on the passivation layer and the common electrode layer in such a way that the second contact hole is exposed outside the third insulating layer; and
forming a pixel electrode on the third insulating layer to electrically connect to the drain via the second contact hole.
13. The method as claimed in claim 12, wherein the gate is formed by first forming a first metallic layer on the substrate and then patterning the first metallic layer.
14. The method as claimed in claim 13, wherein the first metallic layer is formed of a conducting material, which comprises one of a metal, a metal oxide, and a metal alloy.
15. The method as claimed in claim 14, wherein the metal comprises one of aluminum, molybdenum, titanium, chromium, and copper.
16. The method as claimed in claim 14, wherein the metal oxide comprises titanium oxide.
17. The method as claimed in claim 13, wherein the step of patterning the first metallic layer comprises etching the first metallic layer with an etching liquid comprising phosphoric acid, nitric acid, acetic acid, and deionized water.
18. The method as claimed in claim 12, wherein the gate is formed through direct deposition on the substrate.
19. The method as claimed in claim 12, wherein the buffer layer is formed of a material comprising one of silicon nitride and silicon oxide.
20. The method as claimed in claim 12, wherein the impurity ions are P type ions.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60103677A (en) * 1983-11-11 1985-06-07 Seiko Instr & Electronics Ltd Manufacture of thin film transistor
US5602047A (en) * 1996-06-13 1997-02-11 Industrial Technology Research Institute Process for polysilicon thin film transistors using backside irradiation and plasma doping
US20090227075A1 (en) * 2008-03-05 2009-09-10 Bong-Kyun Kim Etchant composition, patterning conductive layer and manufacturing flat panel, display device using the same
US20150316814A1 (en) * 2012-12-12 2015-11-05 Sharp Kabushiki Kaisha Liquid-crystal display panel, liquid-crystal display, and method for manufacturing liquid-crystal display panels

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001119029A (en) * 1999-10-18 2001-04-27 Fujitsu Ltd Thin-film transistor, manufacturing method therefor, and liquid crystal display provided, with the transistor
KR100731750B1 (en) * 2005-06-23 2007-06-22 삼성에스디아이 주식회사 Fabricating Method of TFT and Fabricating Method of Organic Electroluminescence Display Device using the same
CN1921076A (en) * 2006-09-25 2007-02-28 广辉电子股份有限公司 Manufacturing method of thin film transistor
KR101484297B1 (en) * 2007-08-31 2015-01-19 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Display device and manufacturing method of the same
CN102723307A (en) * 2011-03-30 2012-10-10 京东方科技集团股份有限公司 Preparation method of array substrate and TFT structure
KR101283009B1 (en) * 2011-05-26 2013-07-05 주승기 Electroplating system and electroplating method
KR20130078666A (en) * 2011-12-30 2013-07-10 삼성디스플레이 주식회사 Thin film transistor and manufacturing method thereof
JP5557304B1 (en) * 2013-09-26 2014-07-23 国立大学法人東北大学 Organic semiconductor device and CMIS semiconductor device provided with the same
CN104466020B (en) * 2014-12-12 2017-12-15 深圳市华星光电技术有限公司 A kind of LTPS pixel cells and its manufacture method
CN104882485A (en) * 2015-03-30 2015-09-02 深超光电（深圳）有限公司 Thin film transistor and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60103677A (en) * 1983-11-11 1985-06-07 Seiko Instr & Electronics Ltd Manufacture of thin film transistor
US5602047A (en) * 1996-06-13 1997-02-11 Industrial Technology Research Institute Process for polysilicon thin film transistors using backside irradiation and plasma doping
US20090227075A1 (en) * 2008-03-05 2009-09-10 Bong-Kyun Kim Etchant composition, patterning conductive layer and manufacturing flat panel, display device using the same
US20150316814A1 (en) * 2012-12-12 2015-11-05 Sharp Kabushiki Kaisha Liquid-crystal display panel, liquid-crystal display, and method for manufacturing liquid-crystal display panels

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