CN114389585A - High-speed low-offset latch comparator - Google Patents

High-speed low-offset latch comparator Download PDF

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Publication number
CN114389585A
CN114389585A CN202210036895.9A CN202210036895A CN114389585A CN 114389585 A CN114389585 A CN 114389585A CN 202210036895 A CN202210036895 A CN 202210036895A CN 114389585 A CN114389585 A CN 114389585A
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China
Prior art keywords
nmos transistor
transistor
nmos
tube
pmos
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CN202210036895.9A
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彭析竹
谢玉龙
唐鹤
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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Priority to CN202210036895.9A priority Critical patent/CN114389585A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage

Abstract

The invention belongs to the technical field of comparators, and particularly relates to a high-speed low-offset latching comparator. According to the invention, the cross coupling capacitor is inserted into the latch, and the grid voltage of the PMOS tube is reset to the ground in the reset stage by introducing the reset tube, so that the static offset of the comparator can be reduced and the speed of the latch can be improved. In addition, the introduction of the pre-amplifier provides higher speed, bandwidth and gain, further reduces the input offset of the comparator, simultaneously isolates the input signal from the output signal, and reduces kickback noise, thereby realizing a latching comparator with high speed and low offset.

Description

High-speed low-offset latch comparator
Technical Field
The invention belongs to the technical field of comparators, and particularly relates to a high-speed low-offset latching comparator.
Background
The comparator is an important component of an analog integrated circuit, particularly an analog-to-digital or digital-to-analog converter, and has the function of comparing two analog signals input in a differential mode and outputting to obtain a corresponding binary logic level 0 or 1 according to the relative magnitude of the differential input signals. The comparator is used as a core module of the analog-to-digital converter, and the speed and the precision of the comparator directly influence the overall performance of the analog-to-digital converter. The offset voltage of the comparator is larger, which causes the code loss of the analog-digital converter and causes the conversion error; if the speed of the comparator is low, the comparison cannot be completed within a specified time, and a correct comparison result is output, so that a metastable state occurs. Therefore, to realize a high-speed and high-precision analog-to-digital converter, the speed and precision of the comparator are critical.
In a high-speed comparator, the fast comparison characteristic of a latch comparator is often adopted, fig. 1 is a schematic circuit structure diagram of a conventional latch comparator, two amplifying units (inverters) form a loop by end-to-end connection, and the loop is a positive feedback loop, when a difference exists between differential input voltages, the positive feedback is used for increasing a signal difference until one end of the signal difference is close to a power supply VDD and the other end of the signal difference is close to a ground GND, so that a corresponding binary logic level 0 or 1 is realized. The comparison speed of the latch comparator is inversely proportional to the size of the device, and thus the contradiction between offset and speed, namely the contradiction between precision and speed, is formed. Meanwhile, the kickback noise of the structure is very large due to the direct connection of the input end and the output end of the comparator.
Disclosure of Invention
Aiming at the contradiction existing in the existing latch comparator, the invention provides the high-speed low-offset latch comparator which can improve the speed, reduce the offset of the comparator and reduce kickback noise.
The technical scheme of the invention is as follows:
a high speed low offset latching comparator comprising:
the pre-amplifier is used for amplifying the input differential signal, loading the amplified input differential signal to the latch input and isolating the input signal from the output signal;
the latch is connected with the preamplifier and used for comparing the differential signal amplified by the preamplifier;
the preamplifier consists of a differential input pair and a load resistor;
the latch is composed of two amplifying units which are connected end to end, each amplifying unit is coupled through a cross coupling capacitor, the input end of each amplifying unit is controlled by a switch tube, the output end of each amplifying unit is reset to the ground through a reset tube, the switch tube and the reset tube receive the same clock signal and are synchronously switched on or switched off, and the reset stage or the comparison stage is respectively adopted.
Further, the preamplifier includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first load resistor R1, and a second load resistor R2; the first NMOS transistor MN1 and the second NMOS transistor MN2 are a differential input pair, and gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 respectively receive a differential input signal; the third NMOS transistor MN3 is used as a bias current source, the gate thereof is connected to a bias voltage, the source thereof is grounded, and the drain thereof is respectively connected to the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 for providing a bias current; the drain electrode of the first NMOS tube MN1 is connected with a power supply through a first resistor R1, the second NMOS tube MN2 is connected with the power supply through a second load resistor R2, and the connection point of the first NMOS tube MN1 and the first resistor R1 and the connection point of the second NMOS tube MN2 and the second load resistor R2 are differential signal output ends of the preamplifier.
Further, the latch comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a first coupling capacitor C1 and a second coupling capacitor C2; the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are switching transistors, the drain electrode of the fourth NMOS transistor MN4 is connected with the drain electrode of the first NMOS transistor MN1, the drain electrode of the fifth NMOS transistor MN5 is connected with the drain electrode of the second NMOS transistor MN2, and the grid electrodes of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are connected with the same clock signal;
a sixth NMOS transistor MN6 and a first PMOS transistor MP1 form a first amplification unit, the source electrode of the first PMOS transistor MP1 is connected with a power supply, the drain electrode of the first PMOS transistor MP1 is connected with the drain electrode of the sixth NMOS transistor MN6, and the grid electrode of the first PMOS transistor MP1 is connected with the drain electrode of the second PMOS transistor MP 2; the grid electrode of the sixth NMOS transistor MN6 is connected with the source electrode of the fourth NMOS transistor MN4, and the source electrode of the sixth NMOS transistor MN6 is grounded; the gate of the sixth NMOS transistor MN6 is coupled to the gate of the first PMOS transistor MP1 through a first coupling capacitor C1;
a seventh NMOS transistor MN7 and a second PMOS transistor MP2 form a second amplification unit, the source electrode of the second PMOS transistor MP2 is connected with the power supply, the drain electrode of the second PMOS transistor MP2 is connected with the drain electrode of the seventh NMOS transistor MN7, and the grid electrode of the second PMOS transistor MP2 is connected with the drain electrode of the first PMOS transistor MP 1; the grid electrode of the seventh NMOS transistor MN7 is connected with the source electrode of the fifth NMOS transistor MN5, and the source electrode of the seventh NMOS transistor MN7 is grounded; the gate of the seventh NMOS transistor MN7 and the gate of the second PMOS transistor MP2 are coupled through a second coupling capacitor C2;
the connection point of the grid electrode of the first PMOS tube MP1, the drain electrode of the seventh NMOS tube MN7 and the drain electrode of the second PMOS tube MP2, and the connection point of the grid electrode of the second PMOS tube MP2, the drain electrode of the sixth NMOS tube MN6 and the drain electrode of the first PMOS tube MP1 are two output ends of the latch;
the eighth NMOS transistor MN8 and the ninth NMOS transistor MN9 are reset transistors, the drain of the eighth NMOS transistor MN8 is connected to the drain of the first PMOS transistor MP1, the gate of the eighth NMOS transistor MN8 is connected to the gate of the fourth NMOS transistor MN4, and the source of the eighth NMOS transistor MN8 is grounded; the drain of the ninth NMOS transistor MN9 is connected to the drain of the second PMOS transistor MP2, the gate of the ninth NMOS transistor MN9 is connected to the gate of the fifth NMOS transistor MN5, and the source of the ninth NMOS transistor MN9 is grounded.
The invention has the beneficial effects that: according to the invention, the cross coupling capacitor is inserted into the latch, and the grid voltage of the PMOS tube is reset to the ground in the reset stage by introducing the reset tube, so that the static offset of the comparator can be reduced and the speed of the latch can be improved. In addition, the introduction of the pre-amplifier provides higher speed, bandwidth and gain, further reduces the input offset of the comparator, simultaneously isolates the input signal from the output signal, and reduces kickback noise, thereby realizing a latching comparator with high speed and low offset.
Drawings
FIG. 1 is a circuit diagram of a conventional latch comparator;
FIG. 2 is a schematic circuit diagram of a high-speed low-offset latch comparator according to the present invention;
FIG. 3 is a schematic circuit diagram of a reset phase of the latch comparator according to the present invention;
fig. 4 is a schematic circuit diagram of the comparison stage of the latch comparator according to the present invention.
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the attached drawings:
the circuit structure diagram of the conventional Latch comparator is shown in fig. 1, and the principle is that the comparison stage and the reset stage of the comparator are controlled by a clock signal Latch, when Latch is at a high potential, the switching tubes MN3 and MN4 and the reset tube MN5 are all turned on, the comparator enters the reset stage, and the output end (input end) of the comparator is pulled to the same potential. When Latch is at low potential, the switching tubes MN3 and MN4 and the reset tube MN5 are all cut off, the comparator enters a comparison stage, the signal difference at the input end triggers a positive feedback loop formed by the two amplifying units, and the signal difference is amplified to one end close to the power supply VDD and one end close to the ground GND. Since the speed of the structure is inversely proportional to the square of the channel length, the minimum channel length is generally selected in order to achieve higher speed, and thus mismatch between transistors is more and more serious, which causes too large offset and limits the precision of the comparator.
The circuit structure of a high-speed low-offset latch comparator, as shown in fig. 2, includes a preamplifier and a latch. The pre-amplifier is used for amplifying the input differential signal, loading the amplified input differential signal to the latch input and isolating the input signal from the output signal; and the latch is connected with the preamplifier and used for comparing the differential signal amplified by the preamplifier.
The preamplifier comprises a differential input pair 1 and a load resistor 2; the differential input pair 1 comprises a first NMOS transistor MN1 and a second NMOS transistor MN2, the grids of the first NMOS transistor MN1 and the second NMOS transistor MN2 are respectively connected with differential input signals Vinn and Vinp, the sources are respectively connected with bias current, and the drains are respectively connected with load resistors to serve as differential outputs of the preamplifier. The bias current source comprises a third NMOS transistor MN3, the gate of which is connected to the bias voltage VB, the source of which is connected to the ground GND, and the drain of which is connected to the sources of the first NMOS transistor MN1 and the second NMOS transistor MN2, for providing bias current for the differential input pair.
The load resistor 2 comprises a first load resistor R1 and a second load resistor R2, two ends of the first load resistor R1 are respectively connected with the drain of the first NMOS transistor MN1 and the power supply VDD, and two ends of the second load resistor R2 are respectively connected with the drain of the second NMOS transistor MN2 and the power supply VDD. One end connected with the drains of the first NMOS transistor MN1 and the second NMOS transistor MN2 is used as the output end of the preamplifier, namely the output node V of FIG. 2onAnd Vop。
The pre-amplifier uses a resistor as a load, and the gain is as follows:
AV＝-gm1RL
the differential input signal can be amplified by a certain multiple and then input to the latch for comparison, so that the input offset of the comparator can be reduced, and on the other hand, the speed of the preamplifier can be increased by using the resistor as a load, so that the speed of the comparator is increased.
The latch comprises a first switch tube, a second switch tube, a first coupling capacitor C1 and a second coupling capacitor C2, C1＝C2C) a first amplifying unit 3 and a second amplifying unit 4 and a first reset tube and a second reset tube; the first switch tube comprises a fourth NMOS tube MN4, the second switch tube comprises a fifth NMOS tube MN5, the drains of the switch tubes are respectively connected with the differential output signal of the preamplifier and are respectively connected with the drains of the first NMOS tube MN1 and the second NMOS tube MN2 (namely VonAnd Vop) The grid is connected with the same clock signal Latch, and the source is used as output and is respectively connected with the input ends of the first amplifying unit and the second amplifying unit. When the clock signal Latch is at a high potential, the switching tubes are all conducted, and the differential signal amplified by the preamplifier is sampled to the input end of the amplifying unit; when the clock signal Latch is at a low potential, the switching tubes are all cut off, and the comparison stage of the comparator is started.
The first amplifying unit comprises a sixth NMOS transistor MN6 and a first PMOS transistor MP1, and the second amplifying unit comprises a seventh NMOS transistor MN7 and a second PMOS transistor MP 2. The grid electrode of the sixth NMOS tube MN6 is coupled with the grid electrode of the first PMOS tube MP1 through a first coupling capacitor C1, the grid electrode of the sixth NMOS tube MN6 is connected with the source electrode of the fourth NMOS tube MN4 to serve as the input end of the first amplification unit, and the grid electrode of the first PMOS tube MP1 is connected with the drain electrodes of the seventh NMOS tube MN7 and the second PMOS tube MP2 to serve as the differential output end of the latch; the grid electrode of the seventh NMOS tube MN7 is coupled with the grid electrode of the second PMOS tube MP2 through a second coupling capacitor C2, the grid electrode of the seventh NMOS tube MN7 is connected with the source electrode of the fifth NMOS tube MN5 to serve as the input end of the second amplification unit, and the grid electrode of the second PMOS tube MP2 is connected with the drain electrodes of the sixth NMOS tube MN6 and the first PMOS tube MP1 to serve as the other differential output end of the latch; the source electrodes of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected with a power supply VDD, and the source electrodes of the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are connected with a power supply VDDAnd is grounded GND. Due to cross-coupling capacitance C1And C2The gate voltages of the PMOS and the NMOS are isolated and can be respectively biased, the bias voltage of the NMOS is determined by the output of the preamplifier, the bias voltage of the PMOS is determined by the reset voltage, and simultaneously, due to the insertion of the coupling capacitor, the gate source voltages V of the NMOS and the PMOS are enabled to be VGSCan be maximized beyond VDD. The sum of the gate-source voltages of the NMOS and PMOS of the conventional structure is:
VGSN+VGSP＝VDD
due to the insertion of the coupling capacitor, the sum of the gate-source voltages of the NMOS and the PMOS is as follows:
VGSN+VGSP＝VDD+VC
therefore, transconductance gm of the MOS tube can be improved, and the speed of the comparator is further improved. Moreover, the insertion of the cross coupling capacitor can also play a role in storing and memorizing, so that the static imbalance of the comparator can be reduced.
The first reset tube comprises an eighth NMOS tube MN8, the second reset tube comprises a ninth NMOS tube MN9, the drain electrode of the eighth NMOS tube MN8 is connected with the drain electrodes of the sixth NMOS tube MN6 and the first PMOS tube MP1, the drain electrode of the ninth NMOS tube MN9 is connected with the drain electrodes of the seventh NMOS tube MN7 and the second PMOS tube MP2, the grid electrodes of the eighth NMOS tube MN8 and the ninth NMOS tube MN9 are connected with the grid electrode of the switch tube and the clock signal Latch, and the source electrodes of the eighth NMOS tube MN8 and the ninth NMOS tube MN9 are grounded GND.
When the clock signal Latch is at a high potential, as shown in fig. 3, the switching tube and the reset tube are both turned on, the differential signal amplified by the preamplifier is sampled to the input end of the amplifying unit, the drain voltage and the source voltage of the sixth NMOS tube MN6 and the seventh NMOS tube MN7 are both 0, the drain-source current is 0, no current flows, and the output signal of the preamplifier is continuously sampled to the cross-coupling capacitor; the gate voltage of the PMOS tube is reset to the ground GND, so that the PMOS is built for a short time in the next comparison stage of the comparator, the speed of the PMOS is increased, and the speed of the comparator is increased; at this time, the differential output is simultaneously reset to ground GND.
When the clock signal Latch is at a low potential, as shown in fig. 4, both the switch tube and the reset tube are turned off,at the moment, the connection between the preamplifier and the latch is disconnected, the comparator enters a comparison stage, and the sampling voltage at the last moment before the switching tube is cut off is compared. At the moment, the cross coupling capacitor plays a role of level shift, and the sum of the grid source voltages of the NMOS and the PMOS is increased to be higher than VDD. Now, suppose that the gate voltage of the sixth NMOS transistor MN6 is slightly higher than the gate voltage of the seventh NMOS transistor MN7, and the drain-source current of the sixth NMOS transistor MN6 increases to VoutpThe voltage at the terminal is reduced due to VoutpThe voltage of the terminal is reduced, the drain-source current flowing through the seventh NMOS transistor MN7 is reduced, and V isoutnThe voltage at the end is further increased, and the working processes of the first PMOS transistor MP1 and the second PMOS transistor MP2 are the same as the sixth NMOS transistor MN6 and the seventh NMOS transistor MN 7. The two amplifying units form a positive feedback structure, and the signal difference can be rapidly amplified to one end close to a power supply VDD and one end close to ground GND due to the positive feedback effect.
Therefore, according to the characteristics of the existing latch comparator, the cross coupling capacitor and the reset tube are inserted into the latch, so that the gate source voltage V of the MOS tube is increasedGSThe transconductance gm is increased, the gate voltage of the PMOS tube is reset to the ground, the speed of the PMOS is increased, and the purpose of increasing the speed of the comparator is further achieved; meanwhile, the pre-amplifier is added, so that certain gain can be provided while the speed of the pre-amplifier is ensured, the input offset of the comparator is reduced, the input and the output of the comparator can be isolated, and the effect of reducing kickback noise is achieved. Therefore, the speed of the comparator is improved, the effect of reducing the offset of the comparator is achieved, and the high-speed high-precision analog-to-digital converter is used.

Claims (3)

1. A high speed low offset latching comparator, comprising:
the pre-amplifier is used for amplifying the input differential signal, loading the amplified input differential signal to the latch input and isolating the input signal from the output signal;
the latch is connected with the preamplifier and used for comparing the differential signal amplified by the preamplifier;
the preamplifier consists of a differential input pair and a load resistor;
the latch is composed of two amplifying units which are connected end to end, each amplifying unit is coupled through a cross coupling capacitor, the input end of each amplifying unit is controlled by a switch tube, the output end of each amplifying unit is reset to the ground through a reset tube, the switch tube and the reset tube receive the same clock signal and are synchronously switched on or switched off, and the reset stage or the comparison stage is respectively adopted.
2. The high speed low offset latch comparator according to claim 1, wherein the preamplifier includes a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), a first load resistor (R1), and a second load resistor (R2); the first NMOS transistor (MN1) and the second NMOS transistor (MN2) are a differential input pair, and the gates of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) respectively receive differential input signals; the third NMOS transistor (MN3) is used as a bias current source, the grid electrode of the third NMOS transistor is connected with bias voltage, the source electrode of the third NMOS transistor is grounded, and the drain electrode of the third NMOS transistor is respectively connected with the source electrodes of the first NMOS transistor (MN1) and the second NMOS transistor (MN2) and is used for providing bias current; the drain electrode of the first NMOS tube (MN1) is connected with a power supply through a first resistor (R1), the second NMOS tube (MN2) is connected with the power supply through a second load resistor (R2), and the connection point of the first NMOS tube (MN1) and the first resistor (R1) and the connection point of the second NMOS tube (MN2) and the second load resistor (R2) are differential signal output ends of the preamplifier.
3. The high-speed low offset latch comparator according to claim 2, wherein the latch comprises a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third NMOS transistor (MN3), a fourth NMOS transistor (MN4), a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), a ninth NMOS transistor (MN9), a first coupling capacitor (C1), and a second coupling capacitor (C2); the fourth NMOS transistor (MN4) and the fifth NMOS transistor (MN5) are switching transistors, the drain electrode of the fourth NMOS transistor (MN4) is connected with the drain electrode of the first NMOS transistor (MN1), the drain electrode of the fifth NMOS transistor (MN5) is connected with the drain electrode of the second NMOS transistor (MN2), and the grid electrodes of the fourth NMOS transistor (MN4) and the fifth NMOS transistor (MN5) are connected with the same clock signal;
a sixth NMOS transistor (MN6) and a first PMOS transistor (MP1) form a first amplification unit, the source electrode of the first PMOS transistor (MP1) is connected with a power supply, the drain electrode of the first PMOS transistor is connected with the drain electrode of the sixth NMOS transistor (MN6), and the grid electrode of the first PMOS transistor (MP1) is connected with the drain electrode of the second PMOS transistor (MP 2); the grid electrode of the sixth NMOS tube (MN6) is connected with the source electrode of the fourth NMOS tube (MN4), and the source electrode of the sixth NMOS tube (MN6) is grounded; the gate of the sixth NMOS transistor (MN6) and the gate of the first PMOS transistor (MP1) are coupled through a first coupling capacitor (C1);
a seventh NMOS transistor (MN7) and a second PMOS transistor (MP2) form a second amplification unit, the source electrode of the second PMOS transistor (MP2) is connected with a power supply, the drain electrode of the second PMOS transistor is connected with the drain electrode of the seventh NMOS transistor (MN7), and the grid electrode of the second PMOS transistor (MP2) is connected with the drain electrode of the first PMOS transistor (MP 1); the grid electrode of the seventh NMOS transistor (MN7) is connected with the source electrode of the fifth NMOS transistor (MN5), and the source electrode of the seventh NMOS transistor (MN7) is grounded; the gate of the seventh NMOS transistor (MN7) and the gate of the second PMOS transistor (MP2) are coupled through a second coupling capacitor (C2);
the connection point of the grid electrode of the first PMOS tube (MP1), the drain electrode of the seventh NMOS tube (MN7) and the drain electrode of the second PMOS tube (MP2), and the connection point of the grid electrode of the second PMOS tube (MP2), the drain electrode of the sixth NMOS tube (MN6) and the drain electrode of the first PMOS tube (MP1) are two output ends of the latch;
the eighth NMOS transistor (MN8) and the ninth NMOS transistor (MN9) are reset transistors, the drain electrode of the eighth NMOS transistor (MN8) is connected with the drain electrode of the first PMOS transistor (MP1), the gate electrode of the eighth NMOS transistor (MN8) is connected with the gate electrode of the fourth NMOS transistor (MN4), and the source electrode of the eighth NMOS transistor (MN8) is grounded; the drain of the ninth NMOS transistor (MN9) is connected to the drain of the second PMOS transistor (MP2), the gate of the ninth NMOS transistor (MN9) is connected to the gate of the fifth NMOS transistor (MN5), and the source of the ninth NMOS transistor (MN9) is grounded.
CN202210036895.9A 2022-01-13 2022-01-13 High-speed low-offset latch comparator Pending CN114389585A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115276619A (en) * 2022-09-28 2022-11-01 奉加微电子（昆山）有限公司 Dynamic comparator, analog-to-digital converter and electronic equipment
CN117394858A (en) * 2023-12-08 2024-01-12 成都通量科技有限公司 Comparator, analog-to-digital converter and device for reducing kickback noise

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106059587A (en) * 2016-05-23 2016-10-26 西安电子科技大学 High speed low offset voltage comparator circuit
CN106374929A (en) * 2016-12-02 2017-02-01 桂林电子科技大学 Rapid-response dynamic latch comparator
CN108832916A (en) * 2018-06-22 2018-11-16 安徽传矽微电子有限公司 A kind of high-speed low-power-consumption comparator circuit of low dynamic imbalance
CN110912540A (en) * 2019-12-06 2020-03-24 南京德睿智芯电子科技有限公司 High-speed pre-amplification latch comparator with low dynamic mismatch

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106059587A (en) * 2016-05-23 2016-10-26 西安电子科技大学 High speed low offset voltage comparator circuit
CN106374929A (en) * 2016-12-02 2017-02-01 桂林电子科技大学 Rapid-response dynamic latch comparator
CN108832916A (en) * 2018-06-22 2018-11-16 安徽传矽微电子有限公司 A kind of high-speed low-power-consumption comparator circuit of low dynamic imbalance
CN110912540A (en) * 2019-12-06 2020-03-24 南京德睿智芯电子科技有限公司 High-speed pre-amplification latch comparator with low dynamic mismatch

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115276619A (en) * 2022-09-28 2022-11-01 奉加微电子（昆山）有限公司 Dynamic comparator, analog-to-digital converter and electronic equipment
CN115276619B (en) * 2022-09-28 2023-02-17 奉加微电子（昆山）有限公司 Dynamic comparator, analog-to-digital converter and electronic equipment
CN117394858A (en) * 2023-12-08 2024-01-12 成都通量科技有限公司 Comparator, analog-to-digital converter and device for reducing kickback noise
CN117394858B (en) * 2023-12-08 2024-03-19 成都通量科技有限公司 Comparator, analog-to-digital converter and device for reducing kickback noise

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