CN106206337A - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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Publication number
CN106206337A
CN106206337A CN201510854778.3A CN201510854778A CN106206337A CN 106206337 A CN106206337 A CN 106206337A CN 201510854778 A CN201510854778 A CN 201510854778A CN 106206337 A CN106206337 A CN 106206337A
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electrode
connection wiring
distribution
hole
orlop
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CN106206337B (zh
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渡边慎也
南部俊弘
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Kioxia Corp
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Toshiba Corp
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Abstract

本发明的实施方式涉及一种半导体装置及半导体装置的制造方法，使具有贯通电极的半导体芯片的配线布局自由度提高。在半导体基板(30)设置着贯通电极(66)及多层配线(MH1)，在多层配线(MH1)设置着最下层连接配线(54)、下层连接配线(57)、上层连接配线(59)及最上层连接配线(61)，将贯通电极(66)与最下层连接配线(54)接合，以避开贯通电极(66)的正上方的方式配置通孔(60)。

Description

半导体装置及半导体装置的制造方法
[相关申请]
本申请享有以日本专利申请2015-110844号(申请日：2015年5月29日)为基础申请的优先权。本申请通过参照所述基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置及半导体装置的制造方法。
背景技术
为了谋求半导体装置的省空间化、高性能化及大容量化，有时将半导体芯片积层。存在以下装置，即为了获得积层的半导体芯片的电连接，使用被称为TSV(Through SiliconVia，硅穿孔)的贯通电极。
发明内容
本发明的一实施方式提供一种能够提高具有贯通电极的半导体芯片的配线布局自由度的半导体装置及半导体装置的制造方法。
根据本发明的一实施方式，具备半导体层、多层配线、栅极电极及贯通电极。多层配线与栅极电极设置在所述半导体层。贯通电极贯通所述半导体层，且与所述多层配线中的最下层配线直接接触。
附图说明
图1是表示第1实施方式的半导体装置的概略构成的剖视图。
图2是将图1的E1部分的构成例放大表示的剖视图。
图3(a)是表示图2的通孔60的配置例的俯视图，图3(b)是表示图2的通孔58的配置例的俯视图，图3(c)是表示图2的通孔56的配置例的俯视图。
图4是表示能够应用于图1的半导体装置的配线布局的一例的剖视图。
图5是表示应用于第2实施方式的半导体装置的贯通电极的连接构造的剖视图。
图6(a)及图6(b)是表示第3实施方式的半导体装置的制造方法的剖视图。
图7(a)及图7(b)是表示第3实施方式的半导体装置的制造方法的剖视图。
图8(a)是表示第4实施方式的半导体装置的正面测试焊垫的布局例的俯视图，图8(b)是将第4实施方式的半导体装置的正面电极放大表示的俯视图，图8(c)是将第4实施方式的半导体装置的正面测试焊垫放大表示的俯视图，图8(d)是表示第4实施方式的半导体装置的背面测试焊垫的布局例的俯视图。
图9是表示图8(c)的正面测试焊垫与贯通电极的连接构造的一例的剖视图。
图10(a)是表示对第4实施方式的半导体装置进行测试时探针卡的配置方法的俯视图，图10(b)是将图10(a)的探针接脚的接触状态放大表示的剖视图。
具体实施方式
以下参照附图，详细地说明实施方式的半导体装置及半导体装置的制造方法。此外，本发明并不受这些实施方式限定。
(第1实施方式)
图1是表示第1实施方式的半导体装置的概略构成的剖视图。此外，在以下的实施方式中，采用积层八层半导体芯片的构成为例，但也可以为积层N(N为2以上的整数)层半导体芯片的构成。另外，在以下的实施方式中，作为半导体装置，采用NAND(Not AND，与非)闪存为例，但半导体装置既可以为DRAM(Dynamic Random Access Memory，动态随机存取存储器)、FRAM(注册商标)(Ferroelectric Random Access Memory，铁电随机存取存储器)、MRAM(Magnetoresistive Random Access Memory，磁阻随机存取存储器)、PCRAM(PhaseChange Random Access Memory，相变随机存取存储器)等，也可以为逻辑电路或处理器等。此外，图1中表示方向的词语即正与背是表示当将图1中的支撑板1侧设为正且将安装基板21侧设为背时的方向，图2～图10中的正与背未必一致。
在图1中，芯片积层体TA1具备积层后的半导体芯片P1～P8。此时，各半导体芯片P1～P8的厚度能够设定为40μm以下。为了防止在操作芯片积层体TA1时破坏芯片积层体TA1，芯片积层体TA1能够经由粘附层2而固定在支撑板1。支撑板1可以使用例如引线框架等金属板。支撑板1的材料既可以为Cu，也可以为42合金(Fe-Ni系合金)。粘附层2既可以使用绝缘性树脂，也可以使用粘片膜。
在各半导体芯片P1～P8设置着单元区域MA1、MA2。在各单元区域MA1、MA2， 可以将NAND单元设置为阵列状或设置读出放大器或解码器等周边电路。此时，在各单元区域MA1、MA2中，能够以维持单元图案的配置的规则性的方式配置NAND单元。
在各半导体芯片P2～P8，设置着贯通电极5。此时，在半导体芯片P1，可以不设置贯通电极5。各贯通电极5是利用侧壁绝缘膜4而与半导体芯片P2～P8绝缘。贯通电极5的材料可以使用Cu、Ni或Al等。在贯通电极5与侧壁绝缘膜4之间也可以有TiN等障壁金属膜。在各半导体芯片P2～P8中，贯通电极5可以配置在不扰乱各单元区域MA1、MA2中的单元图案的配置的规则性的位置。因此，贯通电极5设置在各单元区域MA1、MA2内欠佳，优选设置在各单元区域MA1、MA2的周围。此处，通过维持各单元区域MA1、MA2中的单元图案的配置的规则性，能够提高曝光时的分辨率，且能够提高NAND单元的集成度。另外，为了防止因各半导体芯片P1～P8的翘曲所引起的各半导体芯片P1～P8间的贯通电极5的连接不良，贯通电极5也可以设置在各单元区域MA1、MA2间。
在半导体芯片P1的背面侧设置着背面电极6A。在各半导体芯片P2～P7的背面侧设置着背面电极6B，在半导体芯片P8的背面侧设置着背面电极6C、6D。另外，在半导体芯片P8的背面侧设置着背面配线9C、9D。背面配线9D可以配置在通过背面配线9D的信号不与通过贯通电极5的信号干涉的位置。在各半导体芯片P2～P8的正面侧设置着正面电极7B。
在各半导体芯片P2～P7中，背面电极6B连接在贯通电极5的背面侧。在半导体芯片P8中，背面配线9C连接在贯通电极5的背面侧，背面电极6C连接在背面配线9C。另外，在半导体芯片P8中，背面电极6D连接在背面配线9D。在背面配线9D的端部设置着焊垫电极10。在各半导体芯片P2～P8中，正面电极7B连接在贯通电极5的正面侧。半导体芯片P1的背面电极6A连接在半导体芯片P2的正面电极7B。在半导体芯片P2～P8间，使在积层方向相邻的半导体芯片P2～P8的背面电极6B与正面电极7B连接。在半导体芯片P8的背面侧设置着接口芯片3。此外，接口芯片3能够与各半导体芯片P1～P8进行数据通信。此时，接口芯片3能够经由贯通电极5而对各半导体芯片P1～P8发送写入数据、指令或地址，或从各半导体芯片P1～P8接收读取数据。也可以代替接口芯片3，而设置对各半导体芯片P1～P8进行读写控制的控制器芯片。在接口芯片3设置着正面电极7C、7D。半导体芯片P8的背面电极6C、6D分别连接在接口芯片3的正面电极7C、7D。此外，背面电极6A、6B或正面电极7B可以使用焊料凸块等突出电极，以确保半导体芯片P1～P8间的间隔SP1。此时，背面电极6A、6B及正面电极7B这两者既可以为突出电极，也可以为突出电极与平面电极的组合。背面电极6A、6B 及正面电极7B的材料既可以为Au、Cu、Ni、Sn、Pg、Ag等单层膜，也可以为积层膜。当将焊料材用作背面电极6A、6B及正面电极7B的材料时，可以使用例如Sn-Cu合金、Sn-Ag合金等。背面配线9C、9D的材料可以使用例如Cu等。焊垫电极10的材料可以使用例如形成在Cu上的Ni或Ni-Pd合金等。也可以在焊垫电极10的Ni或Ni-Pd合金的表面设置Au覆膜。也可以对焊垫电极10的Ni或Ni-Pd合金的表面实施Sn镀敷。
在半导体芯片P1～P8间，沿它们的积层方向设置着确保间隔SP1的间隔件8。间隔SP1可以设定在10～20μm左右的范围内。间隔件8的材料可以使用小于背面电极6A、6B、6C、6D与正面电极7B、7C、7D的接合温度且具有粘附性的绝缘性树脂。例如，当将背面电极6A、6B、6C、6D与正面电极7B、7C、7D焊料接合时，可以使用温度低于焊料的回流焊温度且具有粘附性的绝缘性树脂。例如间隔件8的材料可以使用环氧树脂、聚酰亚胺树脂、丙烯酸系树脂、酚树脂或苯并环丁烯树脂等。此处，间隔件8能够利用贯通电极5来加强维持间隔SP1。此时，间隔件8可以配置在单元区域MA1、MA2上。由此，在以避开各单元区域MA1、MA2内的方式配置着贯通电极5的情况下，也能够稳定地维持半导体芯片P1～P8间的间隔SP1。
芯片积层体TA1是以被突出电极11支撑的状态覆晶安装在安装基板21上。此时，在芯片积层体TA1与安装基板21之间设置着间隔SP2。该间隔SP2可以设定为50μm左右。接口芯片3可以配置在间隔SP2。在安装基板21的正面侧设置着焊盘电极22A及印刷配线22B，在安装基板21的背面侧设置着焊盘电极24A及印刷配线24B。焊盘电极22A的周围及印刷配线22B被阻焊剂23覆盖。焊盘电极24A的周围及印刷配线24B被阻焊剂25覆盖。突出电极11与焊垫电极10及焊盘电极22A接合。突出电极26与焊盘电极24A接合。突出电极11、26的材料既可以为Au、Cu、Ni、Sn、Pg、Ag等单层膜，也可以为积层膜。当将焊料材用作突出电极11、26的材料时，可以使用例如Sn-Cu合金、Sn-Ag合金等。焊盘电极22A、24A及印刷配线22B、24B的材料可以使用Cu等。也可以在焊盘电极22A、24A中从阻焊剂23、25露出的部分形成Au覆膜。安装基板21的基材可以使用例如BT(Bismaleimide Triazine，双马来酰亚胺三嗪)树脂等。
在半导体芯片P1～P8间的间隔SP1填充着密封树脂(例如底部填充树脂12A)。在芯片积层体TA1与安装基板21之间的间隔SP2填充着密封树脂(例如底部填充树脂12B)。支撑板1、芯片积层体TA1及接口芯片3是在安装基板21上被密封树脂12C密封。该密封树脂12C可以使用模具树脂。底部填充树脂12A、12B及密封树脂12C可以使用例如环氧树脂。
图2是表示将图1的E1部分的构成例放大表示的剖视图。此外，图2中的表示方 向的词语即正与背是表示与图1中的正与背相反的方向。也就是说，图2中的正面电极64相当于背面电极6B，背面电极67相当于正面电极7A。
在图2中，在半导体芯片P1设置着半导体基板(半导体层)30。在半导体基板30形成着埋式阱31B。在埋式阱31B中形成着单元阱31A，在单元阱31A，可以设置存储单元阵列。此外，半导体基板30的材料可以从例如Si、Ge、SiGe、GaAs、AlGaAs、InP、GaP、InGaAs、GaN、SiC等中选择。另外，在半导体基板30形成着元件分离层52。此外，元件分离层52可以使用例如STI(Shallow Trench Isolation，浅沟槽隔离)构造。
而且，在单元区域MA1中，在单元阱31A上介隔隧道绝缘膜47而配置电荷蓄积层35。另外，在单元阱31A上，在这些电荷蓄积层35的两侧，分别介隔栅极绝缘膜49、50而配置选择栅极电极39、40。另外，在电荷蓄积层35上介隔中间绝缘膜48而配置控制栅极电极36。此处，能够利用一个电荷蓄积层35与电荷蓄积层35上的控制栅极电极36构成一个存储单元。在选择栅极电极39、40内配置着具有开口EI的中间绝缘膜48-1。换句话说，可以说选择栅极电极39、40被中间绝缘膜48-1分为上部电极与下部电极，并通过开口EI而使上部电极与下部电极电连接。
而且，在单元阱31A，形成着配置在电荷蓄积层35间或电荷蓄积层35与选择栅极电极39、40之间的杂质扩散层32，并且形成着分别配置在选择栅极电极39、40的单侧的杂质扩散层33、34。杂质扩散层34是经由接触电极37而连接在位线BL，杂质扩散层33是经由接触电极38而连接在源极线SCE。此外，在平面NAND存储器中，各存储单元的控制栅极电极36能够构成字线WL1～WLh(h为正整数)。
另外，在半导体基板30上，介隔栅极绝缘膜51而形成着栅极电极46。在栅极电极46中配置着具有开口EI的中间绝缘膜48-2。换句话说，可以说栅极电极46被中间绝缘膜48-2分为上部电极与下部电极，并通过开口EI而使上部电极与下部电极电连接。在控制栅极电极36、选择栅极电极39、40及栅极电极46上，设置着顶盖绝缘膜43。顶盖绝缘膜43能够用作形成控制栅极电极36、选择栅极电极39、40及栅极电极46时的硬质掩模。顶盖绝缘膜43可以使用例如SiN等。而且，在半导体基板30，以夹着栅极电极46下的通道区域的方式形成着杂质扩散层44、45。而且，杂质扩散层44、45分别连接在接触电极41、42。此外，例如单元阱31A可以形成为P型，埋式阱31B及杂质扩散层32、33、34、44、45可以形成为N型。电荷蓄积层35的材料可以使用例如多晶硅。控制栅极电极36、选择栅极电极39、40及栅极电极46的材料可以使用例如钨。隧道绝缘膜47及栅极绝缘膜49、50、51的材料可以使用例如SiO2。
另外，在半导体基板30上形成着层间绝缘膜68。在层间绝缘膜68上形成着电源线65。在电源线65上形成着无机系保护膜62，在无机系保护膜62上形成着有机系保护膜63。层间绝缘膜68及无机系保护膜62的材料可以使用例如SiN、SiO2或它们的积层膜。有机系保护膜63的材料可以使用例如聚酰亚胺系树脂膜或酚系树脂膜。
在元件分离层52上形成着中间绝缘膜53，在中间绝缘膜53上形成着多层配线MH1。在多层配线MH1设置着最下层连接配线54、下层连接配线57、上层连接配线59及最上层连接配线61。可以使最上层连接配线61的厚度厚于下层连接配线57及上层连接配线59的厚度。例如，最上层连接配线61的厚度可以设定为500nm以上，下层连接配线57及上层连接配线59的厚度可以设定为100nm以下。在最下层连接配线54上设置着顶盖绝缘膜55。最下层连接配线54与下层连接配线57是经由通孔56而连接。下层连接配线57与上层连接配线59是经由通孔58而连接。上层连接配线59与最上层连接配线61是经由通孔60而连接。通孔60能够以避开贯通电极66的正上方的方式配置(设置在除正上方以外的位置)。
中间绝缘膜48、48-1、48-2、53可以利用相同的材料构成。例如，中间绝缘膜48、48-1、48-2、53可以使用NONON(N为SiN，O为SiO2)的五层构造。中间绝缘膜48、48-1、48-2、53能够通过同一成膜步骤及蚀刻步骤而形成。此外，可以省略中间绝缘膜53。
最下层连接配线54可以利用与栅极电极46相同的材料构成。最下层连接配线54及栅极电极46可以属于多层配线MH1中的最下层配线。栅极电极46与最下层连接配线54能够通过同一成膜步骤及蚀刻步骤形成。
下层连接配线57可以利用与源极线SCE相同的材料构成。下层连接配线57及源极线SCE可以属于多层配线MH1中的下层配线。下层连接配线57及源极线SCE能够通过同一成膜步骤及CMP(Chemical Mechanical Polishing，化学机械抛光)步骤形成。下层连接配线57及通孔56能够通过双道金属镶嵌步骤一次形成。下层连接配线57、通孔56及源极线SCE可以使用W等高熔点金属。作为下层连接配线57、通孔56及源极线SCE的基底层，也可以是Ti或TiN等障壁金属膜。
上层连接配线59可以利用与位线BL相同的材料构成。上层连接配线59及位线BL可以属于多层配线MH1中的上层配线。上层连接配线59及位线BL能够通过同一成膜步骤及CMP步骤形成。上层连接配线59及通孔58能够通过双道金属镶嵌步骤一次形成。上层连接配线59、通孔58及位线BL可以使用Cu等中熔点金属。作为上层连接配线59、通孔58及位线BL的基底层，也可以是Ti或TiN等障壁金属膜。
最上层连接配线61可以利用与电源线65相同的材料构成。最上层连接配线61及电源线65可以属于多层配线MH1中的最上层配线。最上层连接配线61及电源线65能够通过同一成膜步骤及蚀刻步骤形成。最上层连接配线61、通孔60及电源线65可以使用Al等低熔点金属。此时，最上层连接配线61可以使用刚性比上层连接配线59及下层连接配线57低的金属。最下层连接配线54、下层连接配线57、上层连接配线59及通孔56、58、60可以埋入至层间绝缘膜68。最上层连接配线61可以配置在层间绝缘膜68上。最上层连接配线61的周围被无机系保护膜62覆盖，并且在最上层连接配线61上，形成有正面电极64作为图1的背面电极6B。
在半导体基板30，设置着贯通电极66作为图1的贯通电极5。贯通电极66是利用侧壁绝缘膜65而与半导体基板30绝缘。贯通电极66的正面侧与最下层连接配线54接合。在贯通电极66的背面侧，设置着背面电极67作为图1的正面电极7A。
此处，通过使贯通电极66与最下层连接配线54直接接触，能够在贯通电极66的上方设置配线。因此，与将贯通电极66连接在最上层连接配线61的构成相比，能够提高多层配线MH1的配线布局的自由度。另外，当最下层连接配线54使用蚀刻配线，并且下层连接配线57及上层连接配线59使用金属镶嵌配线时，在最下层连接配线54未产生凹陷，在下层连接配线57及上层连接配线59却产生凹陷。因此，通过将贯通电极66与最下层连接配线54接合，和将贯通电极66与下层连接配线57或上层连接配线59接合的构成相比，能够提高与贯通电极66的接合面为相反侧的面的平坦性。因此，能够减少贯通电极66穿透最下层连接配线54的危险性，能够减少高电阻不良。
进而，通过以避开贯通电极66的正上方的方式配置通孔60，能够提高最上层连接配线61的可挠性。因此，能够使最上层连接配线61具有缓冲性，而能够使通过正面电极64或背面电极67对贯通电极66施加荷重时的应力分散，因此能够防止最下层连接配线54、下层连接配线57或上层连接配线59破坏。
图3(a)是表示图2的通孔60的配置例的俯视图，图3(b)是表示图2的通孔58的配置例的俯视图，图3(c)是表示图2的通孔56的配置例的俯视图。
在图3(a)中，在最上层连接配线61下，在贯通电极66的周围配置着通孔60，在贯通电极66的正上方未配置通孔60。由此，能够提高最上层连接配线61的可挠性，而能够使对正面电极64或贯通电极66施加荷重时的应力分散。
在图3(b)中，在上层连接配线59下能以均等的间隔配置通孔58。此时，为了减少对通孔58施加的荷重，可以在贯通电极66的正上方也配置通孔58。
在图3(c)中，在下层连接配线57下能以均等的间隔配置通孔56。此时，为了减少对通孔56施加的荷重，可以在贯通电极66的正上方也配置通孔56。
此外，在上述实施方式中，作为与形成在半导体基板30上的贯通电极66连接的多层配线MH1，采用四层配线(最下层配线、下层配线、上层配线及最上层配线)为例，但只要为两层以上的配线，则无论几层均可。此时，在主动区域中，最下层配线能够用于控制形成在半导体基板30的通道区域的导电性的栅极电极。
图4是表示能够应用于图1的半导体装置的配线布局的一例的剖视图。此外，在图4中，采用配置着三个贯通电极66A～66C的构成为例。
在图4中，在半导体基板30形成着元件分离层52。在元件分离层52上形成着中间绝缘膜53A～53C，在中间绝缘膜53A～53C上形成着多层配线MH2。在多层配线MH2，设置着最下层连接配线54A～54C、下层连接配线57A、57B、上层连接配线59A及最上层连接配线61A～61C。在最下层连接配线54A～54C上分别设置着顶盖绝缘膜55A～55C。最下层连接配线54A～54C分别配置在中间绝缘膜53A～53C上。下层连接配线57A配置在最下层连接配线54A上。下层连接配线57B配置在最下层连接配线54B、54C上。上层连接配线59A配置在下层连接配线57A、57B上。最上层连接配线61A、61B配置在上层连接配线59A上。最上层连接配线61C配置在下层连接配线57B上。
最下层连接配线54A与下层连接配线57A是经由通孔56A而连接。最下层连接配线54B与下层连接配线57B是经由通孔56B而连接，最下层连接配线54C与下层连接配线57B是经由通孔56C而连接。下层连接配线57A与上层连接配线59A是经由通孔58A而连接，下层连接配线57B与上层连接配线59A是经由通孔58B而连接。上层连接配线59A与最上层连接配线61A是经由通孔60A而连接，上层连接配线59A与最上层连接配线61B是经由通孔60B而连接。通孔60A能够以避开贯通电极66A的正上方的方式配置，通孔60B能够以避开贯通电极66B的正上方的方式配置。
最下层连接配线54A～54C、下层连接配线57A、57B、上层连接配线59A及最上层连接配线61A～61C及通孔56A～56C、58A、58B、60A、60B可以埋入至层间绝缘膜68。最上层连接配线61A～61C可以配置在层间绝缘膜68上。最上层连接配线61A～61C的周围被无机系保护膜62覆盖，并且在最上层连接配线61A～61C上，分别形成着正面电极64A～64C。
在半导体基板30，设置着贯通电极66A～66C。贯通电极66A～66C分别利用侧壁绝缘膜65A～65C而与半导体基板30绝缘。贯通电极66A～66C的正面侧与最下层连接配线54A～54C分别接合。在贯通电极66A～66C的背面侧，分别设置着背面电极67A～67C。
此处，通过使贯通电极66A～66C与最下层连接配线54A～54C分别直接接触，能 够将下层连接配线57A及上层连接配线59A设置在贯通电极66A的正上方，或将下层连接配线57B及上层连接配线59B设置在贯通电极66B的正上方，或将下层连接配线57B设置在贯通电极66C的正上方。因此，能够经由上层连接配线59A而将贯通电极66A、66B电连接，或经由下层连接配线57B而将贯通电极66B、66C电连接，而能够提高多层配线MH1的配线布局的自由度。
(第2实施方式)
图5是表示应用于第2实施方式的半导体装置的贯通电极的连接构造的剖视图。
在图5的构成中，将第1导电层54-1、第2导电层54-2及第3导电层54-3的积层构造用于图2的最下层连接配线54。第1导电层54-1可以使用多晶硅，第2导电层54-2可以使用WN，第3导电层54-3可以使用W。第3导电层54-3的材料可以从Al、Cu、W、NiSi、CoSi及Mn中选择。在第1导电层54-1、第2导电层54-2及第3导电层54-3的侧壁形成着侧墙69。侧墙69的材料可以使用例如SiO2。而且，贯通电极66与第3导电层54-3接合。此时，贯通电极66能够与第1导电层54-1、第2导电层54-2及第3导电层54-3的电阻最低的导电层直接接触。
另外，作为层间绝缘膜68，设置着层间绝缘膜68A～68D。第1导电层54-1、第2导电层54-2及第3导电层54-3埋入至层间绝缘膜68A。利用蚀刻而使第1导电层54-1、第2导电层54-2及第3导电层54-3图案化，由此，能够使在第1导电层54-1、第2导电层54-2及第3导电层54-3不产生凹陷。
通孔56及下层连接配线57埋入至层间绝缘膜68B。此时，由于利用双道金属镶嵌形成通孔56及下层连接配线57，所以在下层连接配线57产生凹陷57D。
通孔58及上层连接配线59埋入至层间绝缘膜68C。此时，由于利用双道金属镶嵌形成通孔58及上层连接配线59，所以在上层连接配线59产生凹陷59D。
通孔60埋入至层间绝缘膜68D，最上层连接配线61配置在层间绝缘膜68D上。
此处，通过使贯通电极66与第3导电层54-3直接接触，和与第1导电层54-1或第2导电层54-2接合的情况相比，能够减小接触电阻。另外，通过使贯通电极66与第3导电层54-3直接接触，相对于使贯通电极66与下层连接配线57或上层连接配线59接合的构成来说，能够防止因凹陷57D、59D而引起的接合不良。
此外，在图5的实施方式中，表示出图2的最下层连接配线54为三层构造的情况，但最下层连接配线54并不限定于三层构造，无论几层均可。
(第3实施方式)
图6(a)、图6(b)、图7(a)及图7(b)是表示第3实施方式的半导体装置的制造方法的剖视图。
在图6(a)中，在半导体基板71形成元件分离层72。接下来，利用CVD或溅镀等方法在元件分离层72上使中间绝缘材及最下层导电材依次成膜之后，利用光刻技术及RIE(Reactive Ion Etching，反应性离子蚀刻)技术而将中间绝缘材及最下层导电材图案化，由此，在元件分离层72上形成中间绝缘膜73及最下层连接配线74。接下来，在利用CVD等方法在最下层连接配线74上成膜层间绝缘膜82之后，利用双道金属镶嵌将经由通孔76而连接在最下层连接配线74的下层连接配线77埋入至层间绝缘膜82。接下来，在利用CVD等方法在下层连接配线77上成膜层间绝缘膜82之后，利用双道金属镶嵌将经由通孔78而连接在下层连接配线77的上层连接配线79埋入至层间绝缘膜82。接下来，在利用CVD等方法在上层连接配线79上成膜层间绝缘膜82之后，将连接在上层连接配线79的通孔80埋入至层间绝缘膜82。接下来，在层间绝缘膜82上形成经由通孔80而连接在上层连接配线79的最上层连接配线81。接下来，在层间绝缘膜82上形成以最上层连接配线81的表面露出的方式经图案化的无机系保护膜83A。接下来，在无机系保护膜83A上形成以最上层连接配线81的表面露出的方式经图案化的有机系保护膜83B。接下来，在最上层连接配线81上形成障壁金属膜84A及凸块电极84B，在凸块电极84B上形成金属被覆膜84C。障壁金属膜84A的材料可以使用例如积层在Ti上的包含Cu的两层构造。凸块电极84B的材料可以使用例如Ni。金属被覆膜84C能够使凸块电极84B提高焊料润湿性，且金属被覆膜84C可以使用例如Au。
接下来，经由粘附层S1而将半导体基板71的正面侧粘附在支撑基板S2。此时，能够使半导体基板71为晶片状态。此外，支撑基板S2的材料既可以为Si，也可以为玻璃。粘附层S1的材料可以使用热固性树脂。接下来，通过利用CMP或BSG等方法对半导体基板71的背面侧进行研磨，而使半导体基板71薄膜化。此时，半导体基板71的厚度TS可以设定为50μm以下。接下来，利用CVD等方法在半导体基板71的背面依次成膜绝缘膜70A、70B。绝缘膜70A的材料可以使用SiO2，绝缘膜70B的材料可以使用SiN。
接下来，如图6(b)所示，利用光刻技术及RIE技术在半导体基板71形成贯通孔TB。此时，贯通孔TB的前端能够利用中间绝缘膜73封止。贯通孔TB的直径KS可以设定为10μmφ左右。
接下来，如图7(a)所示，利用CVD等方法在贯通孔TB的侧壁成膜侧壁绝缘膜88。然后，通过贯通孔TB而蚀刻侧壁绝缘膜88与中间绝缘膜73，由此使最下层连接配线74露出。
接下来，如图7(b)所示，利用溅镀等方法以将贯通孔TB的侧壁覆盖的方式依次成膜障壁金属膜86A及籽晶层86B。障壁金属膜86A的材料可以使用Ti，籽晶层86B的材料可以使用Cu。接下来，利用电场镀敷等方法将贯通电极86C埋入至贯通孔TB内。贯通电极86C的材料可以使用Ni。接下来，在贯通电极86C的表面形成基底金属膜87A之后，在基底金属膜87A上形成凸块电极87B。基底金属膜87A的材料可以使用Cu，凸块电极87B的材料可以使用Sn。而且，在半导体基板71被支撑基板S2支撑的状态下，使探针接脚与凸块电极87B接触，由此进行半导体基板71的器件的测试。之后，在将切割带等支撑带贴附在半导体基板71的背面侧之后，将粘附层S1及支撑基板S2从半导体基板71剥离。接下来，通过切割半导体基板71而将半导体基板71单片化为半导体芯片P1～P8。然后，当将半导体芯片P1～P8积层时，上层的半导体芯片的凸块电极87B与下层的半导体芯片的凸块电极84B接合。此处，当对凸块电极84B使用Ni，对凸块电极87B使用Sn时，在凸块电极84B、87B接合时形成Ni-Sn合金。
(第4实施方式)
图8(a)是表示第4实施方式的半导体装置的正面测试焊垫的布局例的俯视图，图8(b)是将第4实施方式的半导体装置的正面电极放大表示的俯视图，图8(c)是将第4实施方式的半导体装置的正面测试焊垫放大表示的俯视图，图8(d)是表示第4实施方式的半导体装置的背面测试焊垫的布局例的俯视图。
在图8(a)～图8(d)中，在半导体芯片P11的正面侧，设置着正面电极91及正面测试焊垫93。正面电极91能够针对每一晶片在半导体芯片P11配置数万个左右。正面测试焊垫93能够针对每一晶片在半导体芯片P11配置数千个左右。在半导体芯片P11的背面侧，设置着背面电极95及背面测试焊垫96。背面测试焊垫96间的间隔能够以如下方式测定：即便在测试时对背面测试焊垫96施加荷重，而将背面测试焊垫96破坏的情况下，相邻的背面测试焊垫96也不会相互接触。在半导体芯片P11埋入着贯通电极92、94。正面电极91与背面电极95是经由贯通电极92而电连接。正面测试焊垫93与背面测试焊垫96是经由贯通电极94而电连接。可以使各贯通电极92、94的直径R1、R2相互相等，且可以设定为20μmφ以下。
此处，一个正面电极91及一个背面电极95连接在一个贯通电极92。一个正面测试焊垫93连接在三个贯通电极94，一个背面测试焊垫96连接在一个贯通电极94。连接在一个正面测试焊垫93的三个贯通电极94可以配置在假想三角形的顶点。此处，所谓假想三角形是方便表示贯通电极94的位置关系的假想图形，不论有无呈三角形形状的某些构成自身。正面测试焊垫93的尺寸可以大于正面电极91的尺寸。正面测试焊垫93 的边的长度X2、Y2可以设定为80μm左右，正面电极91的边的长度X1、Y1可以设定为40μm左右。正面测试焊垫93的边的长度X2、Y2可以小于探针接脚的前端的直径R3。此时，探针接脚121的前端的直径R3可以设定为120～130μm左右。优选在探针接脚121的可动范围内，不配置除正面测试焊垫93以外的电极或间隔件8。
图9是表示图8(c)的正面测试焊垫与贯通电极的连接构造的一例的剖视图。此外，在图9中，为了容易判断，为方便起见而将连接在一个正面测试焊垫93的三个贯通电极94在一截面并排地表示。
在图9中，在半导体芯片P11设置着半导体基板101。在半导体基板101形成着元件分离层102。在元件分离层102上形成着中间绝缘膜103，在中间绝缘膜103上形成着多层配线MH3。在多层配线MH3，设置着最下层连接配线104、下层连接配线107、上层连接配线109及最上层连接配线93。对于最下层连接配线104，可以使用第1导电层104-1、第2导电层104-2及第3导电层104-3的积层构造。多层配线MH3能够以与图5的构成相同的方式构成。在最下层连接配线104上设置着顶盖绝缘膜105。在第1导电层104-1、第2导电层104-2及第3导电层104-3的侧壁形成着侧墙119。最下层连接配线104与下层连接配线107是经由通孔106而连接。下层连接配线107与上层连接配线109是经由通孔108而连接。上层连接配线109与最上层连接配线93是经由通孔110而连接。通孔110能够以避开贯通电极94的正上方的方式配置。
另外，在半导体基板101上，形成着层间绝缘膜118。在层间绝缘膜118上形成着无机系保护膜112。最上层连接配线93的周围被无机系保护膜112覆盖，并且在最上层连接配线93及无机系保护膜112上形成着有机系保护膜113。
在半导体基板101，设置着贯通电极94。贯通电极94是利用侧壁绝缘膜105而与半导体基板101绝缘。三个贯通电极94的正面侧与一个第3导电层104-3接合。在各贯通电极94的背面侧，设置着一个背面电极96。
图10(a)是表示对第4实施方式的半导体装置进行测试时探针卡的配置方法的俯视图，图10(b)是将图10(a)的探针接脚的接触状态放大表示的剖视图。
在图10(a)中，在探针卡120设置着探针接脚121。探针接脚121可以使用例如弹簧针(spring pin)。探针卡120的材料可以使用例如陶瓷等。此时，探针接脚121收纳在保持器122内，探针接脚121以能够升降的方式被弹簧123支撑。探针接脚可以设置相当于正面测试焊垫93的个数的数量。可以使探针接脚121的配置与正面测试焊垫93的配置对应。探针卡120可以连接在测试器124。
而且，能够通过以与连接在一个正面测试焊垫93的三个背面测试焊垫96同时接触的方式压抵探针接脚121，而对半导体芯片P11进行测试。通过将探针接脚121一次性压抵至设置在半导体芯片P11的每一晶片数千个的背面测试焊垫96，能够缩短半导体芯片P11的测试时间。只将在该测试中合格的半导体芯片P1～P8用于芯片积层体TA1，由此，能够提高芯片积层体TA1的制造良率。
此处，在一个正面测试焊垫93连接三个贯通电极94，使一个探针接脚121同时与三个背面测试焊垫96接触，由此，与利用两个以下的背面测试焊垫96承受一个探针接脚121的荷重的情况相比，能够减少对一个贯通电极94施加的负荷，从而能够减少贯通电极94的损坏。进而，使一个探针接脚121同时与三个背面测试焊垫96接触，由此，与利用两个以下的背面测试焊垫96承受一个探针接脚121的荷重的情况相比，能够使对一个贯通电极94施加的负荷相等，能够提高弹簧123的弹力，而能够减少因弹簧123不回弹而造成的接触不良。
另外，根据探针卡120与半导体芯片P11的热膨胀系数的差异等，有探针卡120上的探针接脚121间的间隔与半导体芯片P11上的正面测试焊垫93间的间隔有偏差的情况。即便在该情况下，也能够通过将连接在一个正面测试焊垫93的三个贯通电极94配置在三角形的顶点，而使一个探针接脚121始终同时与三个背面测试焊垫96接触，与利用四个以上的背面测试焊垫96承受一个探针接脚121的荷重的情况相比，能够使对一个贯通电极94施加的负荷均匀化。
虽对本发明的若干个实施方式进行了说明，但这些实施方式是作为示例而提出的，并非意图限定发明的范围。这些新颖的实施方式能以其他各种方式实施，且能够在不脱离发明主旨的范围内，进行各种省略、替换、变更。这些实施方式或其变化包含在发明的范围或主旨内，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1 支撑板
2 粘附层
3 接口芯片
P1～P8 半导体芯片
MA1、MA2 单元区域
4 侧壁绝缘膜
5 贯通电极
6A～6D 背面电极
7A～7D 正面电极
8 间隔件
9C、9D 背面配线
10 焊垫电极
11、26 突出电极
12A、12B 底部填充树脂
12C 密封树脂
21 安装基板
22A、24A 焊盘电极
22B、24B 印刷配线
23、25 阻焊剂。

Claims (6)

1.一种半导体装置，其特征在于具备：半导体层；
多层配线，设置在所述半导体层；
栅极电极，设置在所述半导体层；以及
贯通电极，贯通所述半导体层，且与所述多层配线中的最下层配线直接接触。
2.根据权利要求1所述的半导体装置，其特征在于：所述最下层配线具备积层多个导电层而得的积层构造，所述贯通电极与所述积层构造中电阻最低的导电层接合。
3.根据权利要求1所述的半导体装置，其特征在于：所述最下层配线与所述栅极电极包含相同的金属。
4.根据权利要求1至3中任一项所述的半导体装置，其特征在于具备：无机系保护膜，保护所述多层配线中的最上层配线；
第1通孔，使所述最上层配线与第1下层配线直接连接；以及
第2通孔，使所述第1下层配线与所述最下层配线电连接；且
所述第1通孔设置在除所述贯通电极的正上方以外的位置。
5.一种半导体装置，其特征在于具备：半导体层；
多个贯通电极，贯通所述半导体层；
多个正面测试焊垫，在所述半导体层的正面侧连接在所述贯通电极；以及
多个背面测试焊垫，在所述半导体层的背面侧连接在所述贯通电极；且
所述多个背面测试焊垫中的一个与所述多个贯通电极中的一个连接，所述多个正面测试焊垫中的一个与所述多个贯通电极中的三个连接。
6.一种半导体装置的制造方法，其特征在于：在半导体层上形成具有栅极配线的最下层配线，
在所述最下层配线上利用金属镶嵌(damascene process)而形成第1下层配线，
在所述第1下层配线上利用蚀刻而形成最上层配线，
形成贯通所述半导体层且到达所述最下层配线的贯通孔，
在所述贯通孔的侧壁形成侧壁绝缘膜，
将与所述最下层配线直接接触的贯通电极形成在形成着所述侧壁绝缘膜的所述贯通孔内。
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