CN105897223B - A kind of primary particle inversion resistant d type flip flop - Google Patents
A kind of primary particle inversion resistant d type flip flop Download PDFInfo
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- CN105897223B CN105897223B CN201610196541.5A CN201610196541A CN105897223B CN 105897223 B CN105897223 B CN 105897223B CN 201610196541 A CN201610196541 A CN 201610196541A CN 105897223 B CN105897223 B CN 105897223B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
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Abstract
The invention discloses a kind of primary particle inversion resistant d type flip flops, it is connected in series by principal and subordinate's two stage latch (Latch), the structure of master-slave latch is identical, the kernel of Latch is no longer end to end two phase inverters, but is made of 6 PMOS transistor P1~P6 and 6 NMOS transistor N1~N6.It is that may make up the main Latch of the present invention or from Latch by increasing the transistor with clock control on the basis of the Latch kernels.Compared with traditional triplication redundancy technology, the present invention has not only saved the area overhead of an election circuit, also eliminates the single-particle sensitive question that election circuit is brought.Meanwhile the single-particle sensibility when storing numerical value 0 of the d type flip flop in the present invention is lower, anti-single particle overturning ability is stronger.Since many triggers need to keep same numerical value for a long time in practical application, thus the present invention overturns ability to the anti-single particle for further increasing this kind of trigger and is of great significance.
Description
Technical field
The present invention relates to triggers in integrated circuit fields, especially primary particle inversion resistant d type flip flop under radiation environment.
Background technology
There are a large amount of high energy particles (proton, heavy ion etc.) and high-energy rays in cosmic space.Sequential in integrated circuit
Unit, such as trigger after the bombardment by these high energy particles and ray, will produce single-particle inversion (Single Event
Upset, abbreviation SEU).The generation of single-particle inversion will produce soft error, so that integrated circuit operational malfunctions.With technique
The continual reductions of size, integrated circuit transistor density continue to increase, the probability that multiple transistors are bombarded by single-particle simultaneously
It greatly promotes, and the reduction of transistor size itself is so that indicate that the critical charge of device state persistently reduces, this gives nanometer
Flip-flop design brings great challenge under scale.On the one hand, multiple transistors are received by the multinode charge that bombardment causes simultaneously
Rally brings single event multiple bit upset (Multiple Cell Upset, abbreviation MCU)；On the other hand, while multinode charge is received
Collection is so that many traditional trigger reinforcement design technology (such as double interlocking unitsDual Interlocked CeLl is (referred to as
DICE) etc.) consolidation effect weakens significantly.Thus at the nanoscale, novel highly reliable anti-single particle overturning triggering is designed
Device circuit seems necessary.
Common d type flip flop as shown in Figure 1, be connected in series by principal and subordinate's two stage latch (Latch), be denoted as main Latch and from
Latch, main Latch are as from the logical construction of Latch, as shown in Fig. 2 (a), by 2 input inversions with clock control
Device Inv1 and feedback inverter Inv2 and 1 phase inverter (being denoted as third phase inverter Inv3) without clock control are constituted.It is defeated
The input terminal for entering reverser receives data-signal D, and output end is connected with node M N, when separately being received respectively there are two input end of clock
Clock signal CLK andFrom the perspective of function, as shown in Fig. 2 (b), feedback inverter Inv2 and third phase inverter Inv3
It joins end to end and constitutes the storage organization of Latch or the kernel of Lacth in common d type flip flop, the input of third phase inverter Inv3
Connecting node MN, node M N is held to be connected with the output end of input inverter Inv1, the output end connection section of third phase inverter Inv3
The input terminal of point M and feedback inverter Inv2, node M are actually directly connected to the output Q of Latch；Feedback inverter Inv2
Input terminal be connected with node M, output end is connected with node M N, another to receive clock signal clk respectively there are two input end of clock
With
Shown in the realization of third phase inverter such as Fig. 3 (a), by a PMOS transistor P0With a NMOS transistor N0Composition,
Wherein PMOS transistor is connected with the drain electrode of NMOS transistor constitutes the output end Y of phase inverter, and PMOS transistor and NMOS are brilliant
The grid of body pipe, which is connected, constitutes the input terminal A of phase inverter；The source electrode of PMOS transistor is connected on power vd D, and NMOS crystal
The source electrode of pipe is connected on ground VSS.As shown in Fig. 3 (b)-(d), input inverter or feedback inverter with clock control then by
2 PMOS transistor P1And P2And 2 NMOS transistor N1And N2Composition, there is 3 kinds of realization methods.Make a general survey of this 3 kinds realization shapes
Formula, they are the third phase inverters shown in Fig. 3 (a) (by PMOS transistor P1With NMOS transistor N1Constitute) on the basis of
Add the PMOS transistor P of a clock control2With the NMOS transistor N of a clock control2；And its increased transistor or
It is connected in series shown in person such as Fig. 3 (b)-(c), or with transmission gate (Transmission as shown in Fig. 3 (d)
Gate, TG) form be connected to the output end of phase inverter.Transmission gate is by a PMOS transistor and a NMOS transistor group
At wherein the source electrode of PMOS transistor and NMOS transistor is connected with each other, drain electrode is also connected with each other, and respective grid is by outside
Signal is controlled to control source electrode to the break-make to drain.It is worth noting that, clock signal in the input inverter with clock control
It is 180 degree with clock signal phase difference in the feedback inverter with clock control.That is, when the input with clock control is anti-
When the grid of PMOS transistor P2 is connected to certain external signal CLK in phase device, PMOS is brilliant in the feedback inverter with clock control
Body pipe P2Grid be connected to by CLK signal through a phase inverter generate CLK non-signalOn.
T.Calin et al. is in IEEE Transaction on Nuclear Science (IEEE atomic energy sciences journal)
On " Upset hardened memory design for submicro CMOS Technology " (sub-micron for delivering
CMOS technology moderate resistance overturning reinforce storage unit design) (volume 43, the 2874-2878 pages of the 6th phase of December in 1996) for the first time
DICE structures are proposed, which uses the form of double interlocking, effectively single-particle can be inhibited to turn under micron and submicrometer processing
Turn, thus up to the present DICE structures extensive use trigger Design of Reinforcement.However under nanometer technology, N.Gaspard etc.
What people delivered on IEEE Transaction on Nuclear Science (IEEE atomic energy sciences journal)
“Technology scaling com-parison of flip-flop heavy-ion single event upset
Cross sections " (trigger SEU cross section is influenced to compare by process reduction factor under heavy ion radiation environment)
(volume 60, the 4368-4373 pages of the 6th phase of December in 2013) point out DICE triggers with respect to d type flip flop consolidation effect drastically
Decline, the SEU cross section of DICE triggers and d type flip flop, which is become by differing 1~2 order of magnitude originally, differs only by 1.2
~5 times.Under nanometer CMOS process, the flip-flop design scheme being widely adopted at present also has the D triggerings of triplication redundancy reinforcing
Device, as Y.He et al. is delivered on Science China Information Sciences (Chinese science information science)
“Comparison of heavy-ion induced SEU for D-and TMR-flip-flop designs in 65nm
(d type flip flop and its heavy ion single-particle of triplication redundancy design turn over bulk CMOS technology " under 65 nanometer CMOS process
Turn to compare) (the 10th phase of October in 2014 volume 57, the 102405th:1-7 pages) point out triplication redundancy technology to inhibiting single-particle to turn over
Turn highly effective, however triplication redundancy upset cross section under 65 nanometer technologies also only only reduces about an order of magnitude, and three
The election circuit itself that mould redundancy introduces is also that single-particle is sensitive.
Process is reduced in 65nm and its following technique, the shared single-particle multinode induced of charge in integrated circuit
Charge-trapping has become a kind of universal phenomenon.On the one hand, current reinforcing d type flip flop is increasingly difficult to avoid single-particle more piece
Single-particle inversion caused by point charge-trapping, so that primary particle inversion resistant demand under radiation environment cannot be met；It is another
Aspect can not avoid three moulds although traditional d type flip flop triplication redundancy reinforcement technique can inhibit single-particle inversion well
Single-particle inversion caused by election circuit needed for redundancy simultaneously needs the area of 4 times (area of the circuit containing election) or more to open
Pin.How the SEU cross section of reinforcing d type flip flop is reduced, and then it is ability to promote d type flip flop anti-single particle overturning ability
The technical issues of field technique personnel extremely pay close attention to.
Invention content
The technical problem to be solved by the present invention is to：It cannot meet anti-simple grain under radiation environment for existing reinforcing d type flip flop
The demand of son overturning, traditional d type flip flop triplication redundancy reinforcement technique can not avoid single-particle inversion caused by election circuit
And the problem that area overhead is big, a kind of primary particle inversion resistant d type flip flop is provided, it is stronger and effective that anti-single particle overturns ability
The area overhead for reducing triplication redundancy reinforcement technique eliminates the single-particle sensitive question that election circuit is brought.
The technical scheme is that：D type flip flop is connected by main latch and from latch two stage latch in the present invention
It forms, main latch is identical with the structure from latch, but the Latch and the Latch in common d type flip flop are incomplete
Identical, wherein the kernel of Latch is no longer end to end two phase inverters, but as shown in figure 4, by 6 PMOS transistors
P1~P6 and 6 NMOS transistor N1~N6 is constituted.As shown in figure 4, the drain electrode of N1 is connected with the drain electrode of P1, node M N1, and even
It is connected on the grid of P2 and N4, the grid of N1 is connected with the drain electrode of N2；The drain electrode of N2 is connected with the drain electrode of P2, node M 1, and even
It is connected on the grid of P3 and N1, the grid of N2 is connected with the drain electrode of N5；The drain electrode of N3 is connected with the drain electrode of P3, node M N2, and even
It is connected on the grid of P4 and N6, the grid of N3 is connected with the drain electrode of N4；The drain electrode of N4 is connected with the drain electrode of P4, node M 2, and even
It is connected on the grid of P5 and N3, the grid of N4 is connected with the drain electrode of N1；The drain electrode of N5 is connected with the drain electrode of P5, node M N3, and even
It is connected on the grid of P6 and N2, the grid of N5 is connected with the drain electrode of N6；The drain electrode of N6 is connected with the drain electrode of P6, node M 3, and even
It is connected on the grid of P1 and N5, the grid of N6 is connected with the drain electrode of N3.The grid of P1 is connected with the drain electrode of N6, the drain electrode of P1 and N1
Drain electrode be connected；The grid of P2 is connected with the drain electrode of N1, and the drain electrode of P2 is connected with the drain electrode of N2；The drain electrode phase of the grid of P3 and N2
Even, the drain electrode of P3 is connected with the drain electrode of N3；The grid of P4 is connected with the drain electrode of N3, and the drain electrode of P4 is connected with the drain electrode of N4；P5's
Grid is connected with the drain electrode of N4, and the drain electrode of P5 is connected with the drain electrode of N5；The grid of P6 is connected with the drain electrode of N5, the drain electrode of P6 and N6
Drain electrode be connected.The source electrode of 6 PMOS transistor P1~P6 meets power vd D；The source electrode of 6 NMOS transistor N1~N6 connects
Ground VSS.
On the basis of kernel shown in Fig. 4, the master of the present invention is may make up by increasing transistor with clock control etc.
Latch or from latch.Main latch is still identical with from latch in d type flip flop of the present invention.As shown in figure 5, main latch
The data input D of device is connected respectively to node M N1, MN2 in latch kernel by 3 input inverters with clock control
And MN3, and only need to be according to the phase inverter in the prior art with clock control like that (such as at latch core nodes M1, M2 and M3
Transmission gate mode shown in series system or Fig. 3 (d) shown in Fig. 3 (b)-(c)) respectively increase a PMOS by clock control and
NMOS transistor, any one node in M1 or M2 or the M3 node of final main latch are connected to the number from latch
According to input D, and exported from the data that any one node in M1 or M2 or the M3 node of latch is d type flip flop of the present invention
Q。
Fig. 5-Fig. 7 is 3 kinds of specific implementation forms of (or from) latch main in d type flip flop of the present invention.
Latch shown in Fig. 5 uses realization method shown in Fig. 3 (b), and the source electrode of PMOS transistor P2, P4 and P6 respectively lead to
It crosses a PMOS transistor controlled by clock signal (i.e. P7, P8 and P9) and is connected to power vd D, and NMOS transistor N2, N4
With the source electrode of N6 ground VSS is connected to each by a NMOS transistor (i.e. N7, N8 and N9) by clock signal control.It latches
Device data input D by three input inverter Inv1~Inv3 with clock control be connected respectively to node M N1, MN2 and
MN3, and node M 3 is chosen as output signal Q.Two such latch are together in series in the way of Fig. 1 and may make up the present invention
D type flip flop, any one node in M1 or M2 or the M3 node of main latch is connected to from the data of latch and inputs D,
And in this example, it is chosen as output signal Q from the node M 3 of latch.
Latch shown in Fig. 6 uses realization method shown in Fig. 3 (c), the drain electrode of PMOS transistor P2 and NMOS transistor
It has been sequentially inserted into PMOS transistor P10 that one is controlled by clock signal between the drain electrode of N2 and one is controlled by clock signal
One has been sequentially inserted by clock between the drain electrode and the drain electrode of NMOS transistor N4 of NMOS transistor N10, PMOS transistor P4
The PMOS transistor P11 of a signal control and NMOS transistor N11 controlled by clock signal, the drain electrode of PMOS transistor P6
Be sequentially inserted between the drain electrode of NMOS transistor N6 PMOS transistor P12 that one is controlled by clock signal and one by when
The NMOS transistor N12 of clock signal control.Equally, the data input D of latch passes through three input inversions with clock control
Device Inv1~Inv3 is connected respectively to node M N1, MN2 and MN3, and node M 3 is chosen as output signal Q.It is latched as two
Device is together in series in the way of Fig. 1 and may make up the d type flip flop of the present invention, arbitrary in M1 or M2 or the M3 node of main latch
One node is connected to from the data of latch and inputs D, and in this example, it is chosen as output signal Q from the node M 3 of latch.
Latch shown in Fig. 7 uses transmission gate mode shown in Fig. 3 (d), i.e., real by transmission gate TG1, TG2 and TG3
The control of current clock data signal access.PMOS transistor P13 and NMOS tube N13 constitute transmission gate TG1, PMOS transistor
P14 and NMOS tube N14 constitutes transmission gate TG2, PMOS transistor P15 and NMOS tube N15 and constitutes transmission gate TG3.Transmission gate TG1's
One end is connected to M1 nodes, and the other end is connected to the grid of NMOS transistor N1 and PMOS transistor P3；One end of transmission gate TG2
M2 nodes are connected to, the other end is connected to the grid of NMOS transistor N3 and PMOS transistor P5；One end of transmission gate TG3 connects
To M3 nodes, the other end is connected to the grid of NMOS transistor N5 and PMOS transistor P1.Similarly, the data input of latch
D is connected respectively to node M N1, MN2 and MN3 by three input inverter Inv1~Inv3 with clock control, and node M 3
It is chosen as output signal Q.Two such latch are together in series in the way of Fig. 1 and may make up the d type flip flop of the present invention, main
Any one node in M1 or M2 or the M3 node of latch is connected to from the data of latch and inputs D, and in this example, from
The node M 3 of latch is chosen as output signal Q.
The primary particle inversion resistant course of work of the present invention is：
When in space high energy particle or ray bombard to main latch in d type flip flop of the present invention or from certain in latch
When place, such as the PMOS transistor P2 and P3 in Fig. 4, single-ion transient state is will produce on P3,0 → 1 full pendulum is will produce on node M N2
Width voltage jump opens NMOS transistor N6, so that the voltage in node M 3 becomes an intermediate level value；It is same with this
When, PMOS transistor P2 so that the voltage in node M 1 is enhanced by particle bombardment, and maintains high level state, it is acted on
In N1 transistors so that node M N1 is not influenced by N6 transistor drivings P1 and remains logic low, thus the lock
Numerical value overturning will not occur for the storage organization of storage.Certainly, from the perspective of circuit, the latch that is constituted with kernel shown in Fig. 4
Device simultaneously will not non-fully generate single-particle inversion, when such as transistor to (P1, P3) while by particle bombardment, node M N1 and MN2
0 → 1 full amplitude of oscillation voltage jump will be generated；So that generating 1 → 0 full amplitude of oscillation voltage jump, node M 3 in node M 2
Half amplitude of oscillation voltage jump of upper generation 1 → 1/2；At this moment MN3 nodes are driven stronger by P5, and MN3 nodes, which slowly occur 0 → 1, expires
Amplitude of oscillation saltus step, and drive the full amplitude of oscillation saltus step of generation 1 → 0 on M3；Numerical value overturning occurs for final Lacth.Kernel shown in Fig. 4 is constituted
Latch in, for storage 0 and storage 1 two kinds of data patterns, particle simultaneously bombard can cause overturning transistor to having 9
It is right, and these transistors to all only in the case where store 1 this data pattern sensitivity；However transistor is to (P1, P3) and (P3, P5)
Spacing distance is nearest in domain realization, has all reached 1.79 μm by the realization of minimum layout design rules；Thus these transistors
To being actually difficult simultaneously by particle bombardment, i.e. latch in the present invention and the d type flip flop of the present invention has very high
Anti-single particle overturns ability.
Following technique effect can be reached using the present invention：
1, since the kernel of each latch in the present invention is made of 6 PMOS transistors and 6 NMOS transistors, this
The area overhead that an election circuit has not only been saved compared with traditional triplication redundancy technology also eliminates election circuit and brings
Single-particle sensitive question；
2, the numerical value stored in d type flip flop in the present invention has significant impact to the single-particle sensibility of the unit.For depositing
0 this data pattern is stored up, by particle bombardment simultaneously numerical value overturning will not all be occurred for any two transistor in d type flip flop, this
So that the single-particle sensibility when storing numerical value 0 of the d type flip flop in the present invention is lower, anti-single particle overturning ability is stronger.Due to
Many triggers need to keep same numerical value for a long time in practical application, thus the present invention is to further increasing this kind of trigger
Anti-single particle overturning ability is of great significance.
Description of the drawings
Fig. 1 is the building-block of logic using the d type flip flop of principal and subordinate's two stage latch structure；
Fig. 2 is the building-block of logic of principal and subordinate's two stage latch and latch kernel in common d type flip flop in background technology；
Fig. 3 (a) is the logical construction of third phase inverter in common d type flip flop in background technology, when Fig. 3 (b)-(d) is band
The logical construction of the input inverter of clock or the 3 of feedback inverter kinds of ways of realization；
Fig. 4 is the building-block of logic of latch kernel in the present invention；
Fig. 5 is the latch core logic structure chart realized with mode shown in Fig. 3 (b) in the present invention；
Fig. 6 is the latch core logic structure chart realized with mode shown in Fig. 3 (c) in the present invention；
Fig. 7 is the latch core logic structure chart realized with mode shown in Fig. 3 (d) in the present invention.
Specific implementation mode
Fig. 1 is the building-block of logic using the d type flip flop of principal and subordinate's two stage latch structure.
Common d type flip flop and d type flip flop of the present invention are formed by main latch (latch) and from latch tandem,
Main latch is identical with the structure from latch.
Fig. 2 is the building-block of logic of principal and subordinate's two stage latch and latch kernel in common d type flip flop in background technology.
The main latch of common d type flip flop or from latch by 1 input inverter with clock control, 1 band when
The feedback inverter of clock and a phase inverter are constituted.And the kernel of latch is made of two end to end phase inverters.
Fig. 3 (a) is third phase inverter, it is made of 1 PMOS transistor and 1 NMOS transistor, wherein PMOS crystal
Pipe is connected with the drain electrode of NMOS transistor constitutes the output end of phase inverter, and PMOS transistor is connected with the grid of NMOS transistor
Constitute the input terminal of phase inverter；The source electrode of PMOS transistor is connected on power supply, and the source electrode of NMOS transistor is connected on the ground.
Fig. 3 (b)-(d) is 3 kinds of ways of realization of the input inverter with clock control or feedback inverter.Make a general survey of this 3 kinds realization shapes
Formula, on the basis of they are the third phase inverter shown in Fig. 3 (a) (being made of PMOS transistor P1 and NMOS transistor N1)
Add the NMOS transistor N2 of the PMOS transistor P2 and a clock control of a clock control；And its increased transistor or
It is connected in series shown in person such as Fig. 3 (b)-(c), or phase inverter is connected in the form of transmission gate as shown in Fig. 3 (d)
Output end.It is worth noting that, clock signal and the feedback reverse phase with clock control in the input inverter with clock control
Clock signal phase difference is 180 degree in device.That is, when the grid of PMOS transistor P2 in the input inverter with clock control
When pole is connected to certain external signal CLK, PMOS transistor P in the feedback inverter with clock control2Grid be connected to by CLK
Signal generates the non-signal of CLK through a phase inverterOn.
Fig. 4 is the kernel of latch in the present invention.
There are two end to end phase inverters no longer as the kernel (shown in Fig. 2) of latch in common d type flip flop for it
It constitutes, but is made of 6 PMOS transistor P1~P6 and 6 NMOS transistor N1~N6.The drain electrode of N1 to drain with P1,
Node M N1 is connected, and is connected on the grid of P2 and N4, and the grid of N1 is connected with the drain electrode of N2；The drain electrode of N2 to drain with P2,
Node M 1 is connected, and is connected on the grid of P3 and N1, and the grid of N2 is connected with the drain electrode of N5；The drain electrode of N3 to drain with P3,
Node M N2 is connected, and is connected on the grid of P4 and N6, and the grid of N3 is connected with the drain electrode of N4；The drain electrode of N4 to drain with P4,
Node M 2 is connected, and is connected on the grid of P5 and N3, and the grid of N4 is connected with the drain electrode of N1；The drain electrode of N5 to drain with P5,
Node M N3 is connected, and is connected on the grid of P6 and N2, and the grid of N5 is connected with the drain electrode of N6；The drain electrode of N6 to drain with P6,
Node M 3 is connected, and is connected on the grid of P1 and N5, and the grid of N6 is connected with the drain electrode of N3.The drain electrode phase of the grid of P1 and N6
Even, the drain electrode of P1 is connected with the drain electrode of N1；The grid of P2 is connected with the drain electrode of N1, and the drain electrode of P2 is connected with the drain electrode of N2；P3's
Grid is connected with the drain electrode of N2, and the drain electrode of P3 is connected with the drain electrode of N3；The grid of P4 is connected with the drain electrode of N3, the drain electrode of P4 and N4
Drain electrode be connected；The grid of P5 is connected with the drain electrode of N4, and the drain electrode of P5 is connected with the drain electrode of N5；The drain electrode phase of the grid of P6 and N5
Even, the drain electrode of P6 is connected with the drain electrode of N6.The source electrode of 6 PMOS transistor P1~P6 meets power vd D；6 NMOS transistors
The source grounding VSS of N1~N6.
Fig. 5-Fig. 7 is 3 kinds of specific implementation forms of (or from) latch main in d type flip flop of the present invention.
Latch shown in Fig. 5 uses realization method shown in Fig. 3 (b), and the source electrode of PMOS transistor P2, P4 and P6 respectively lead to
It crosses a PMOS transistor controlled by clock signal (i.e. P7, P8 and P9) and is connected to power vd D, and NMOS transistor N2, N4
With the source electrode of N6 ground VSS is connected to each by a NMOS transistor (i.e. N7, N8 and N9) by clock signal control.It latches
Device data input D by three input inverter Inv1~Inv3 with clock control be connected respectively to node M N1, MN2 and
MN3, and node M 3 is chosen as output signal Q.Two such latch are together in series in the way of Fig. 1 and may make up the present invention
D type flip flop, any one node in M1 or M2 or the M3 node of main latch is connected to from the data of latch and inputs D,
And in this example, it is chosen as output signal Q from the node M 3 of latch.
Latch shown in Fig. 6 uses realization method shown in Fig. 3 (c), the drain electrode of PMOS transistor P2 and NMOS transistor
It has been sequentially inserted into PMOS transistor P10 that one is controlled by clock signal between the drain electrode of N2 and one is controlled by clock signal
One has been sequentially inserted by clock between the drain electrode and the drain electrode of NMOS transistor N4 of NMOS transistor N10, PMOS transistor P4
The PMOS transistor P11 of a signal control and NMOS transistor N11 controlled by clock signal, the drain electrode of PMOS transistor P6
Be sequentially inserted between the drain electrode of NMOS transistor N6 PMOS transistor P12 that one is controlled by clock signal and one by when
The NMOS transistor N12 of clock signal control.Equally, the data input D of latch passes through three input inversions with clock control
Device Inv1~Inv3 is connected respectively to node M N1, MN2 and MN3, and node M 3 is chosen as output signal Q.It is latched as two
Device is together in series in the way of Fig. 1 and may make up the d type flip flop of the present invention, arbitrary in M1 or M2 or the M3 node of main latch
One node is connected to from the data of latch and inputs D, and in this example, it is chosen as output signal Q from the node M 3 of latch.
Latch shown in Fig. 7 uses transmission gate mode shown in Fig. 3 (d), i.e., real by transmission gate TG1, TG2 and TG3
The control of current clock data signal access.PMOS transistor P13 and NMOS tube N13 constitute transmission gate TG1, PMOS transistor
P14 and NMOS tube N14 constitutes transmission gate TG2, PMOS transistor P15 and NMOS tube N15 and constitutes transmission gate TG3.Transmission gate TG1's
One end is connected to M1 nodes, and the other end is connected to the grid of NMOS transistor N1 and PMOS transistor P3；One end of transmission gate TG2
M2 nodes are connected to, the other end is connected to the grid of NMOS transistor N3 and PMOS transistor P5；One end of transmission gate TG3 connects
To M3 nodes, the other end is connected to the grid of NMOS transistor N5 and PMOS transistor P1.Similarly, the data input of latch
D is connected respectively to node M N1, MN2 and MN3 by three input inverter Inv1~Inv3 with clock control, and node M 3
It is chosen as output signal Q.Two such latch are together in series in the way of Fig. 1 and may make up the d type flip flop of the present invention, main
Any one node in M1 or M2 or the M3 node of latch is connected to from the data of latch and inputs D, and in this example, from
The node M 3 of latch is chosen as output signal Q.
Claims (4)
1. a kind of primary particle inversion resistant d type flip flop is connected in series by main latch and from latch two stage latch, main latch
Device is identical with the structure from latch, which is characterized in that main latch and latch kernel from latch are by 6
PMOS transistor P1~P6 and 6 NMOS transistor N1~N6 are constituted；The drain electrode of N1 is connected with the drain electrode of P1, node M N1, and even
It is connected on the grid of P2 and N4, the grid of N1 is connected with the drain electrode of N2；The drain electrode of N2 is connected with the drain electrode of P2, node M 1, and even
It is connected on the grid of P3 and N1, the grid of N2 is connected with the drain electrode of N5；The drain electrode of N3 is connected with the drain electrode of P3, node M N2, and even
It is connected on the grid of P4 and N6, the grid of N3 is connected with the drain electrode of N4；The drain electrode of N4 is connected with the drain electrode of P4, node M 2, and even
It is connected on the grid of P5 and N3, the grid of N4 is connected with the drain electrode of N1；The drain electrode of N5 is connected with the drain electrode of P5, node M N3, and even
It is connected on the grid of P6 and N2, the grid of N5 is connected with the drain electrode of N6；The drain electrode of N6 is connected with the drain electrode of P6, node M 3, and even
It is connected on the grid of P1 and N5, the grid of N6 is connected with the drain electrode of N3；The grid of P1 is connected with the drain electrode of N6, the drain electrode of P1 and N1
Drain electrode be connected；The grid of P2 is connected with the drain electrode of N1, and the drain electrode of P2 is connected with the drain electrode of N2；The drain electrode phase of the grid of P3 and N2
Even, the drain electrode of P3 is connected with the drain electrode of N3；The grid of P4 is connected with the drain electrode of N3, and the drain electrode of P4 is connected with the drain electrode of N4；P5's
Grid is connected with the drain electrode of N4, and the drain electrode of P5 is connected with the drain electrode of N5；The grid of P6 is connected with the drain electrode of N5, the drain electrode of P6 and N6
Drain electrode be connected；The source electrode of 6 PMOS transistor P1~P6 meets power vd D；The source electrode of 6 NMOS transistor N1~N6 connects
Ground VSS；
Main latch is connected respectively to latch from the data of latch input D by 3 input inverters with clock control
Node M N1, MN2 and MN3 in device kernel, and respectively increase one by clock control at latch core nodes M1, M2 and M3
PMOS and NMOS transistor, any one node in M1 or M2 or the M3 node of final main latch are connected to from latch
Data input D, and are that data export Q from any one node in M1 or M2 or the M3 node of latch.
2. primary particle inversion resistant d type flip flop as described in claim 1, which is characterized in that the latch core nodes M1,
Respectively increase PMOS transistor P7, P8 and a P9 and NMOS transistor N7, N8 and N9 by clock control at M2 and M3；PMOS
PMOS transistor, that is, P7, P8 and P9 that the source electrode of transistor P2, P4 and P6 are controlled each by one by clock signal, is connected to
Power vd D, and the source electrode of NMOS transistor N2, N4 and N6 are each by a NMOS transistor by clock signal control
N7, N8 and N9 are connected to ground VSS；Latch data input D by three input inverter Inv1 with clock control~
Inv3 is connected respectively to node M N1, MN2 and MN3.
3. primary particle inversion resistant d type flip flop as described in claim 1, which is characterized in that the latch core nodes M1,
Respectively increase at M2 and M3 one by PMOS transistor P10, P11 and P12 and NMOS transistor N10, N11 of clock control and
N12；One has been sequentially inserted between the drain electrode and the drain electrode of NMOS transistor N2 of PMOS transistor P2 to be controlled by clock signal
PMOS transistor P10 and a NMOS transistor N10 controlled by clock signal, the drain electrode of PMOS transistor P4 and NMOS crystal
It has been sequentially inserted into PMOS transistor P11 that one is controlled by clock signal between the drain electrode of pipe N4 and one is controlled by clock signal
NMOS transistor N11, be sequentially inserted between the drain electrode and the drain electrode of NMOS transistor N6 of PMOS transistor P6 one by when
The PMOS transistor P12 of a clock signal control and NMOS transistor N12 controlled by clock signal, the data input of latch
D is connected respectively to node M N1, MN2 and MN3 by three input inverter Inv1~Inv3 with clock control.
4. primary particle inversion resistant d type flip flop as described in claim 1, which is characterized in that the latch core nodes M1,
Respectively increase at M2 and M3 one by PMOS transistor P13, P14 and P15 and NMOS transistor N13, N14 of clock control and
N15；PMOS transistor P13 and NMOS tube N13 constitutes transmission gate TG1, PMOS transistor P14 and NMOS tube N14 and constitutes transmission gate
TG2, PMOS transistor P15 and NMOS tube N15 constitute transmission gate TG3；One end of transmission gate TG1 is connected to M1 nodes, the other end
It is connected to the grid of NMOS transistor N1 and PMOS transistor P3；One end of transmission gate TG2 is connected to M2 nodes, other end connection
To the grid of NMOS transistor N3 and PMOS transistor P5；One end of transmission gate TG3 is connected to M3 nodes, and the other end is connected to
The grid of NMOS transistor N5 and PMOS transistor P1；Similarly, the data of latch input D by three with clock control
Input inverter Inv1~Inv3 is connected respectively to node M N1, MN2 and MN3.
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| CN106788341B (en) * | 2017-01-12 | 2020-07-10 | 深圳大学 | Asynchronous reset D trigger resisting single event upset |
| CN106788380B (en) * | 2017-01-12 | 2020-03-24 | 深圳大学 | Asynchronous set D trigger resistant to single event upset |
| CN108199698A (en) * | 2017-12-13 | 2018-06-22 | 北京时代民芯科技有限公司 | A kind of doubleclocking anti-single particle latch |
| CN112567631A (en) * | 2018-06-04 | 2021-03-26 | 国立大学法人京都工芸纤维大学 | D-type flip-flop circuit |
| CN110138377B (en) * | 2019-06-03 | 2023-06-13 | 上海华力微电子有限公司 | Latch device |
| CN110311655A (en) * | 2019-06-27 | 2019-10-08 | 北京嘉楠捷思信息技术有限公司 | Hold-free dynamic D trigger, data processing unit, chip, force calculation board and computing equipment |
| CN110838834B (en) * | 2019-11-11 | 2021-07-23 | 西安电子科技大学 | Reinforced improved QUATRO D trigger of anti single event upset |
| CN111241770B (en) * | 2020-01-08 | 2023-11-24 | 中国人民武装警察部队海警学院 | Low-power-consumption SET suppression circuit for trigger under radiation environment |
| CN111223503B (en) * | 2020-03-11 | 2021-10-01 | 河海大学常州校区 | Double-node single-particle upset immune memory cell and latch |
| CN117767918A (en) * | 2022-09-19 | 2024-03-26 | 长鑫存储技术有限公司 | Trigger circuit and electronic device |
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| CN103021456A (en) * | 2012-12-19 | 2013-04-03 | 电子科技大学 | Nonvolatile high-resistance single-particle configuration memory unit |
| CN103903645A (en) * | 2012-12-28 | 2014-07-02 | 中国科学院微电子研究所 | Static random storage unit employing radiation hardening design |
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| CN103021456A (en) * | 2012-12-19 | 2013-04-03 | 电子科技大学 | Nonvolatile high-resistance single-particle configuration memory unit |
| CN103903645A (en) * | 2012-12-28 | 2014-07-02 | 中国科学院微电子研究所 | Static random storage unit employing radiation hardening design |
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