CN108134597A - A kind of completely immune latch of three internal nodes overturning - Google Patents
A kind of completely immune latch of three internal nodes overturning Download PDFInfo
- Publication number
- CN108134597A CN108134597A CN201810015566.XA CN201810015566A CN108134597A CN 108134597 A CN108134597 A CN 108134597A CN 201810015566 A CN201810015566 A CN 201810015566A CN 108134597 A CN108134597 A CN 108134597A
- Authority
- CN
- China
- Prior art keywords
- tube
- pmos tube
- nmos tube
- signal input
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Static Random-Access Memory (AREA)
Abstract
The present invention provides a kind of three internal nodes overturning completely immune latch, by eight pairs of PN transistors to building a memory module, realize reliable data storage feedback loop, the memory module is fed back into four input C cells again, the complete tolerance to binode upset is not only realized, and realizes complete tolerance (immune) function of three internal node overturnings.On the other hand, transmission gate is inserted into so as to which electric current be avoided to compete due to the use of fewer number of transistor and high speed channel technology and in output stage, reduce circuit area overhead, delay overhead and power dissipation overhead.The present invention can be effectively applicable to the integrated circuit and system of high reliability demand, can be widely applied to the field higher to latch reliability and cost requirement such as space flight and aviation.
Description
Technical field
The invention belongs to the anti-multiple node upsets of integrated circuit to reinforce fault-tolerant design technique field, and in particular in three a kind of
The completely immune latch of portion's node overturning.
Background technology
With the fast development of semiconductor technology, the manufacturing process of integrated circuit enters nanometer ruler from sub-micro grade
Degree.Due to the reduction of supply voltage and node capacitance, the quantity of electric charge stored in circuit node is also fewer and fewer.When neutron or matter
Son causes when a sensitive nodes of energetic particle hits storage unit required for the logic state of circuit node overturns
The quantity of electric charge (critical charge) also decrease.Soft error is the important origin cause of formation that integrated circuit fails.In strong radiation environment
In, under charge sharing mechanism, it is a kind of typical soft error that particle, which hits the multiple node upset that circuit node is induced,.By grain
Multiple node upset caused by son is hit is more very important.
Latch is a kind of storage unit circuit to impulse level sensitivity, can be under the effect of specific input pulse level
Change state.There is statistical data to show under nanometer technology, especially in strong radiation environment, multiple node upset has become shadow
Ring the main problem of latch circuit reliability design.It is largely existing in high energy particle and cosmic ray for working long hours
Latch circuit in strong radiation environment only carries out single-particle inversion Design of Reinforcement and is not enough, it is necessary to which it is carried out
Multiple node upset Design of Reinforcement.
Problems with is primarily present currently for the anti-multiple node upset Design of Reinforcement of latch：First, cannot effectively it tolerate
Binode upset, that is, there is fragile node pair, when each node of the node centering is overturn, the output of latch
It will stay in that the logical value of mistake；Second is that being overturn while cannot tolerating three nodes inside latch completely, that is, there is fragility
Sequence node, when wherein three nodes are overturn simultaneously, latch outputs can output error logical value；Third, energy
The expense (such as area, power consumption) of enough latch of tolerance multiple node upset is larger.
Invention content
Insufficient existing for latch structure in order to which existing anti-multiple node upset is overcome to reinforce, the present invention, which provides one kind, to be held
Bear the latch circuit designing scheme of three nodes overturning, building high reliability data by the PN transistors of eight pairs of phase mutual feedbacks deposits
Module is stored up, and realizes the immune function of three nodes overturning using the C cell of four inputs in output stage.Meanwhile use high speed channel
Latch delay expense is reduced, and electric current competition is reduced in latch outputs, so as to save partial circuit power consumption.The present invention carries
The latch gone out can be widely applied to the every field higher to reliability and cost requirement.
The present invention is achieved by the following technical solutions：
A kind of completely immune latch of three internal nodes overturning, including：One storage by 8 pairs of PN transistors structures
Module, a C cell and six transmission gates；Memory module is equipped with the first signal input part, second signal input terminal, third letter
Number input terminal, fourth signal input terminal and the first signal output end, second signal output terminal, third signal output end, the 4th
Signal output end；C cell is equipped with the first signal input part, second signal input terminal, third signal input part, fourth signal input
End and a signal output end.
Wherein, six transmission gates are respectively with identical clock：First transmission gate, the second transmission gate, third transmission gate,
4th transmission gate, the 5th transmission gate, the 6th transmission gate.
The signal input part of first transmission gate, the signal input part of the second transmission gate, third transmission gate signal input part,
The signal input part of 4th transmission gate and the signal input part of the 5th transmission gate are connected, data of the tie point as latch
Input terminal.
The signal output end of first transmission gate is connected with the first signal input part of memory module；The letter of second transmission gate
Number output terminal is connected with the second signal input terminal of memory module；The signal output end of third transmission gate and the of memory module
Three signal input parts are connected；The signal output end of 4th transmission gate is connected with the fourth signal input terminal of memory module.
First signal output end of memory module is connected with the first signal input part of C cell；The second of memory module
Signal output end is connected with the second signal input terminal of C cell；The third signal output end of memory module and the third of C cell
Signal input part is connected；The fourth signal output terminal of memory module is connected with the fourth signal input terminal of C cell.C cell
Signal output end be connected with the signal input part of the 6th transmission gate.
The signal output end of 5th transmission gate is connected with the signal output end of the 6th transmission gate, and tie point is as latch
Data output end.
The present invention is relative to the advantageous effect of the prior art：
(1) by eight groups of PN transistors reliable data storage feedback loop is realized to building a memory module, then should
Memory module feeds back to four input C cells, not only realizes the complete tolerance to binode upset, and realizes three inside
Complete tolerance (immune) function of node overturning.
(2) expenses such as delay and area are relatively low.It is reduced and postponed by high speed channel, improve circuit performance；Make in output stage
Output end current is reduced with transmission gate to compete, and reduces power dissipation overhead；It is built using fewer number of transistor, reduces area
Expense.
Description of the drawings
Fig. 1 is the latch circuit schematic diagram that a kind of three internal nodes overturning that embodiment 1 provides is immunized completely.
Fig. 2 is the circuit diagram of memory module (MCell).
Fig. 3 is the circuit diagram of four input C cells.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, it is right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are only used to explain the present invention,
It is not intended to limit the present invention.
Embodiment 1：
As shown in Figure 1, the latch that a kind of three internal nodes overturning is completely immune, including：One by 8 pairs of PN transistors
The memory module MCell of structure, a C cell and six transmission gates；Memory module MCell is equipped with the first signal input part
I2, second signal input terminal I4, third signal input part I6, fourth signal input terminal I8 and the first signal output end I1,
Binary signal output terminal I3, third signal output end I5, fourth signal output terminal I7；C cell is equipped with the first signal input part, second
Signal input part, third signal input part, fourth signal input terminal and a signal output end.Wherein, six transmission gate difference
For with identical clock：First transmission gate TG1, the second transmission gate TG2, third transmission gate TG3, the 4th transmission gate TG4, the 5th
Transmission gate TG5, the 6th transmission gate TG6.
The signal input part of first transmission gate TG1, the signal input part of the second transmission gate TG2, third transmission gate TG3 letter
The signal input part of number input terminal, the signal input part of the 4th transmission gate TG4 and the 5th transmission gate TG5 is connected, tie point
Data input pin as latch.
The signal output end of first transmission gate TG1 is connected with the first signal input part I2 of memory module MCell；Second
The signal output end of transmission gate TG2 is connected with the second signal input terminal I4 of memory module MCell；Third transmission gate TG3's
Signal output end is connected with the third signal input part I6 of memory module MCell；The signal output end of 4th transmission gate TG4 with
The fourth signal input terminal I8 of memory module MCell is connected.
The first signal output end I1 of memory module MCell is connected with the first signal input part of C cell；Memory module
The second signal output terminal I3 of MCell is connected with the second signal input terminal of C cell；The third signal of memory module MCell
Output terminal I5 is connected with the third signal input part of C cell；The fourth signal output terminal I7 and C cell of memory module MCell
Fourth signal input terminal be connected.
The signal output end of C cell is connected with the signal input part of the 6th transmission gate TG6.
The signal output end of 5th transmission gate TG5 is connected with the signal output end of the 6th transmission gate TG6, tie point conduct
The data output end of latch.
As shown in Fig. 2, the concrete structure of memory module MCell is as follows：Including：First PMOS tube P1, the second PMOS tube P2,
Third PMOS tube P3, the 4th PMOS tube P4, the 5th PMOS tube P5, the 6th PMOS tube P6, the 7th PMOS tube P7, the 8th PMOS tube
P8, the first NMOS tube N1, the second NMOS tube N2, third NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5, the 6th NMOS
Pipe N6, the 7th NMOS tube N7, the 8th NMOS tube N8.
Wherein：
The drain electrode of first PMOS tube P1, the drain electrode of the first NMOS tube N1, the 8th PMOS tube P8 grid and the 2nd NMOS
The grid of pipe N2 is connected, first signal output end I1 of the tie point as memory module MCell.
The drain electrode of second PMOS tube P2, the drain electrode of the second NMOS tube N2, the first PMOS tube P1 grid and the 3rd NMOS
The grid of pipe N3 is connected, first signal input part I2 of the tie point as memory module MCell.
The drain electrode of third PMOS tube P3, the drain electrode of third NMOS tube N3, the second PMOS tube P2 grid and the 4th NMOS
The grid of pipe N4 is connected, second signal output terminal I3 of the tie point as memory module MCell.
The drain electrode of 4th PMOS tube P4, the drain electrode of the 4th NMOS tube N4, third PMOS tube P3 grid and the 5th NMOS
The grid of pipe N5 is connected, second signal input terminal I4 of the tie point as memory module MCell.
The drain electrode of 5th PMOS tube P5, the drain electrode of the 5th NMOS tube N5, the 4th PMOS tube P4 grid and the 6th NMOS
The grid of pipe N6 is connected, third signal output end I5 of the tie point as memory module MCell.
The drain electrode of 6th PMOS tube P6, the drain electrode of the 6th NMOS tube N6, the 5th PMOS tube P5 grid and the 7th NMOS
The grid of pipe N7 is connected, third signal input part I6 of the tie point as memory module MCell.
The drain electrode of 7th PMOS tube P7, the drain electrode of the 7th NMOS tube N7, the 6th PMOS tube P6 grid and the 8th NMOS
The grid of pipe N8 is connected, fourth signal output terminal I7 of the tie point as memory module MCell.
The drain electrode of 8th PMOS tube P8, the drain electrode of the 8th NMOS tube N8, the 7th PMOS tube P7 grid and the first NMOS
The grid of pipe N1 is connected, fourth signal input terminal I8 of the tie point as memory module MCell.
First PMOS tube P1, the second PMOS tube P2, third PMOS tube P3, the 4th PMOS tube P4, the 5th PMOS tube P5, the 6th
PMOS tube P6, the 7th PMOS tube P7, the source electrode of the 8th PMOS tube P8 and substrate are all connected with power vd D.
First NMOS tube N1, the second NMOS tube N2, third NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5, the 6th
NMOS tube N6, the 7th NMOS tube N7, the source electrode of the 8th NMOS tube N8 and substrate are grounded GND.
As shown in figure 3, the concrete structure of C cell CE is as follows：Including：Four PMOS tube and four NMOS tube compositions；Wherein,
Four PMOS tube are respectively the 9th PMOS tube MP1, the tenth PMOS tube MP2, the 11st PMOS tube MP3, the 12nd PMOS tube MP4,
Four NMOS tubes are respectively the 9th NMOS tube MN1, the tenth NMOS tube MN2, the 11st NMOS tube MN3, the 12nd NMOS tube MN4 groups
Into；Wherein：
The grid of 12nd PMOS tube MP4 is connected with the grid of the 12nd NMOS tube MN4, tie point for C cell the
One signal input part；The grid of 11st PMOS tube MP3 is connected with the grid of the 11st NMOS tube MN3, and tie point is C cell
Second signal input terminal；The grid of tenth PMOS tube MP2 is connected with the grid of the tenth NMOS tube MN2, and tie point is C cell
Third signal input part；The grid of 9th PMOS tube MP1 is connected with the grid of the 9th NMOS tube MN1, and tie point is C cell
Fourth signal input terminal；The drain electrode of 12nd PMOS tube MP4 is connected with the drain electrode of the 9th NMOS tube MN1, and tie point is mono- for C
The signal output end of member；The drain electrode of 9th PMOS tube MP1 is connected with the source electrode of the tenth PMOS tube MP2；Tenth PMOS tube MP2's
Drain electrode is connected with the source electrode of the 11st PMOS tube MP3；The drain electrode of 11st PMOS tube MP3 and the source of the 12nd PMOS tube MP4
Pole is connected；The source electrode of 9th NMOS tube MN1 is connected with the drain electrode of the tenth NMOS tube MN2；The source electrode of tenth NMOS tube MN2 with
The drain electrode of 11st NMOS tube MN3 is connected；The source electrode of 11st NMOS tube MN3 is connected with the drain electrode of the 12nd NMOS tube MN4
It connects；The source electrode of 9th PMOS tube MP1, the substrate of the 9th PMOS tube MP1, the substrate of the tenth PMOS tube MP2, the 11st PMOS tube
The substrate of MP3, the 12nd PMOS tube MP4 substrate be all connected with power vd D；The substrate of 9th NMOS tube MN1, the tenth NMOS tube
The substrate of MN2, the substrate of the 11st NMOS tube MN3, substrate, the source electrode of the 12nd NMOS tube MN4 of the 12nd NMOS tube MN4 are equal
Ground connection.
The truth table of table 1C units
Above-mentioned table 1 is the truth table of C cell.By the table it is found that when the first signal input part I1, second signal input terminal
When I3, third signal input part I5 are identical with fourth signal input terminal I7 logical values, signal output end will export opposite with input
Logical value, at this time C cell show as phase inverter；When the first signal input part I1, second signal input terminal I3, third signal are defeated
When entering to hold I5 and fourth signal input terminal I7 logical value differences, signal output end enters hold mode, exports under original state
Logical value.It can be seen that the logical value that C cell can be used for masked nodes is overturn, that is, avoid in input terminal I1, I3, I5, I7
The overturning of part logical value and propagate to output terminal.
The normal work principle of latch proposed by the invention is illustrated below.When CLK is high level, CLKB is
During low level, the arrangement works are under transparent mode.At this point, transmission gate TG1, TG2, TG3, TG4, TG5 are connected.Using D=1 as
Example, i.e. D=I2=I4=I6=I8=Q=1.NMOS transistor N1, N3, N5, N7 conducting in MCell at this time, therefore I1=
I3=I5=I7=0, the input of C cell are determined, therefore C cell will export 1.On the other hand, TG6 is closed, and TG5 conductings, D can
Q is transmitted directly to, Q is not to be driven by the output terminal of C cell, therefore reduces the electric current competition of latch outputs, from
And save circuit power consumption.When CLK is low level, and CLKB is high level, the arrangement works are under latch mode.At this point, TG1,
TG2, TG3, TG4, TG5 are closed, TG6 conductings, therefore Q is only driven by the output terminal of C cell.On the other hand, due to MCell's
Even-numbered nodes are to odd node feedback data, and odd node is to even-numbered nodes feedback data, therefore form several data
Feedback loop, to ensure that MCell being capable of effective latch data.Again due to four groups of outputs of MCell be fed back to four groups of C cell it is defeated
Enter, therefore Q can also latch correct data.
The fault-tolerant operation principle of latch proposed by the invention is illustrated below.Mould (is latched with storage 1 herein
Q=I2=I4=I6=I8=1 under formula, I1=I3=I5=I7=0) for be specifically described.When storage 0, situation is similar,
As space is limited, it is omitted herein.First discuss single node upset situation, key node sequence for I1, I2, I3, I4, I5, I6,
I7、I8、Q}.In preceding 8 nodes, odd node logical value is identical, and even-numbered nodes logical value is identical, odd node and even number section
Point logical value is different.Herein by taking single node upset occurs for I5 as an example.Before overturning, I4=1, after overturning, I5 is by initial value 0
Being temporarily changed 1 will cause P4 to close, but the value of I4 is constant, therefore N5 is connected, so as to make I5 self- recoverages.On the other hand, I5 is overturn
When being 1, I7 is not affected, therefore P6 is connected, I6=1 (strong 1).Meanwhile N6 is temporarily connected, I6=0 (weak 0).But I6
Strong 1 can neutralize weak 0, therefore I6 is still correct.Similarly, similar fault tolerant mechanism can be obtained for other nodes.But for Q
For single node upset occurs, because MCell is not affected by influence, therefore Q being capable of self- recoverage.In short, any section of the latch
Point can from single node self- recoverage.Also that is, the latch is single node upset restoration-online.
Next the situation of binode upset is discussed, since the data mode of any two node all may be used under latch mode
It can overturn, there are two kinds of possible situations：(1) binode upset occurs for MCell；(2) node and Q are same in MCell
Shi Fasheng is overturn.
For the situation of (1), the key node sequence of MCell is { I1, I2, I3, I4, I5, I6, I7, I8 }, so as to there is hair
The situation of raw binode upset amounts to C82=28 kinds.If the distance between two neighboring node is represented with NL, MCell
The distance between middle any two node is only possible to as 1L, 2L, 3L, 4L, because the node in MCell is cycle, as I1 is arrived
The distance of I6 is really that I6 is recycled to the distance of I1 and is not 5L and is 3L.On the other hand, it is got over from the distance between domain angle, node
Far, it is just smaller or even can be ignored that the probability of binode upset occurs.Thus 4 kinds of exemplary binode upset sections can be chosen
Point to sequence<I1、I2>、<I1、I3>、<I1、I4>、<I1、I5>}.Obviously, the distance between corresponding two nodes point in sequence
Not Wei 1L, 2L, 3L, 4L, and every other node is similar to one kind all respectively with above-mentioned 4 kinds of node centerings in latch
's.Below to above-mentioned exemplary binode upset node to sequence<I1、I2>、<I1、I3>、<I1、I4>、<I1、I5>Appearance
Wrong principle is discussed analysis respectively：For<I1、I2>The situation of overturning, is analyzed below：<I1、I2>Before overturning,
The value of whole odd nodes (such as I1, I3) is 0, and the value of whole even-numbered nodes (such as I2, I4) is 1, odd number NMOS tube (such as N1, N3)
It all turns on, even number PMOS tube (such as P2, P4) all turns on, other metal-oxide-semiconductors are not turned on.<I1、I2>When overturning, i.e. I1
Temporarily from 0 overturning be 1, I2 temporarily from 1 overturn be that 0, N2 and P1 is temporarily connected, other nodes are not affected.I8 outputs 1,
N1 is connected, therefore I1 self- recoverages.I2 by initial value 1 overturn be 0 when can't influence the value of I3, therefore I3 is still connected for 0, P2, therefore
I2 self- recoverages.It can be seen that MCell can from the DNU (i.e. binode upset) self- recoverage, therefore the input of C cell is whole
Correctly, it is clear that Q still maintains correct value, i.e., the latch can from the DNU self- recoverage.Similarly, for<I1、I4>Or<
I1、I5>The situation of overturning, MCell remains able to the self- recoverage from DNU, therefore the i.e. latch can be from above-mentioned DNU from extensive
It is multiple.
For<I1、I3>The situation of overturning, is analyzed below：<I1、I3>Before overturning, I1=I3=0.<I1、
I3>When DNU occurs, i.e. I1 and I3 are 1 from 0 overturning, therefore N2 and N4 are both turned on, and I2 overturnings are 0, therefore P1 is connected.Because of the initial value 1 of I8
It is unaffected, therefore N1 is connected, I1 will enter indeterminate state and not interfere with I8 at this time.And due to<I1、I3>Hair
During raw overturning, the initial value 0 of I5 is not affected, and P4 is constantly on, and N4 is also switched on from the above mentioned, thus I4 value it is indefinite and
I5 is not interfered with, i.e. I5 is unaffected always.It can be seen that the input of C cell is not affected all, it is clear that Q
Correct value is still maintained, i.e., the latch can tolerate the DNU.
For the situation of (2), because of MCell single node self- recoverages, the subsequent also self- recoverages of Q.I.e. for the situation of (2) latch
Device can from DNU self- recoverage.
The situation of internal three nodes overturning is finally discussed.Due to the data shape of arbitrary three internal nodes under latch mode
State may all be overturn, and understand to amount to comprising three kinds of situations through analysis.
The first situation, three nodes are the input of C cell, the input key node sequence of C cell for I1, I3,
I5, I7 }, so as to there is the situation that the overturning of three nodes occurs to amount to C43=4 kinds, that is,<I1、I3、I5>、<I1、I3、I7>、<I1、
I5、I7>、<I3、I5、I7>}.Below with<I1、I3、I5>For overturning, analyzed：When I1, I3, I5 are turned over by initial value 0
Switch to 1, I7 and I8 is unaffected, this is because all will not even if I6 is overturn to be overturn by initial value 0 for 0, I1 by initial value 1 for 1
By error propagation to I7 and I8.When I1 overturnings are 1, N2 conductings, therefore I2=0.Since I3 is also overturn, therefore P2 can not be connected, I2
The value 0 of mistake is remained, P1 is connected at this time, and because of I8=1, N1 is also switched on, therefore I1 enters underrange.When I3 overturnings are 1
When, N4 conductings, therefore I4=0.Since I5 is also overturn, therefore P4 can not be connected, and I4 remains the value 0 of mistake, and P3 is connected at this time, therefore
I3 remains the value 1 of mistake.When I5 overturnings are 1, N6 conductings, since I7=0 is unaffected, P6 can also be connected, therefore I6 enters
Underrange.In short, there is no all overturn, therefore the logic state of the signal output end of C cell will protect for the input of C cell
Hold constant, i.e., the latch can tolerate the overturning of above-mentioned three node.For<I1、I3、I7>、<I1、I5、I7>With<I3、I5、I7>
It is similar to the above there is a situation where overturning, it is omitted herein.
The second situation, the input of the non-C cell of three nodes, the key node sequence of non-C cell input for I2, I4,
I6, I8 }, so as to there is the situation that the overturning of three nodes occurs to amount to C43=4 kinds, that is,<I2、I4、I6>、<I2、I4、I8>、<I2、
I6、I8>、<I4、I6、I8>}.Below with<I2、I4、I6>For overturning, analyzed：When I2, I4, I6 are turned over by initial value 1
Switch to 0, I7 and I8 is unaffected, this is because I1 to be caused to be overturn by initial value 0 for 0, I2 be 1 even if I6 is overturn by initial value 1
It all will not be by error propagation to I7 and I8.Through analysis it is found that when I2, I4, I6 overturning will enter underrange for 0, I1 and I6, and
I2, I3, I4, I5 will occur overturning and be unable to self- recoverage.But there is no all overturn, therefore C is mono- for the input of C cell
The logic state of the signal output end of member will remain unchanged, i.e., the latch can tolerate above-mentioned three nodes overturning.For<I2、
I4、I8>、<I2、I6、I8>With<I4、I6、I8>It is similar to the above there is a situation where overturning, it is omitted herein.
The third situation, in three nodes the input of existing C cell also have the input of non-C cell, be divided into as two kinds of situations：
(A) there are two odd node and an even-numbered nodes in three nodes, share C42 × 4=24 kind situations；(B) in three nodes
There are one odd node and two even-numbered nodes, share C42 × 4=24 kind situations.
In the case of (A), below with<I1、I2、I3>For overturning, analyzed：When I1, I2, I3 respectively by
The overturning of initial value 0,1,0 is 1,0,1, and I5, I6, I7 and I8 are unaffected, this is because even if it is 0, I1 that I4 is overturn by initial value 1
Being overturn by initial value 0 all will not be by error propagation to I5 and I8 for 1, therefore will not be by error propagation to I6, I7.It can through analysis
Know, when I1, I2, I3 are overturn, I1 and I4 will enter underrange, and I2, I3 will occur overturning and be unable to self- recoverage.But
It is that the input of C cell is there is no all overturning, therefore the logic state of the signal output end of C cell will remain unchanged, i.e.,
The latch can tolerate above-mentioned three nodes overturning.It is similar to the above for other three nodes there is a situation where overturning, herein from
Slightly.
In the case of (B), below with<I2、I4、I5>For overturning, analyzed：When I2, I4, I5 respectively by
Initial value 1,1,0 is overturn to be unaffected for 0,0,1, I7 and I8, this is because even if it is 0, I2 that I5, which causes I6 to be overturn by initial value 1,
I1 is caused to be overturn by initial value 0 all will not be by error propagation to I7 and I8 for 1.Through analysis it is found that when I2, I4, I5 are overturn, I1
It will enter underrange, and I2, I3, I4, I5 will occur overturning and be unable to self- recoverage with I6.But the input of C cell is not
It all overturns, therefore the logic state of the signal output end of C cell will remain unchanged, i.e., the latch can be tolerated above-mentioned
Three nodes are overturn.It is similar to the above for other three nodes there is a situation where overturning, it is omitted herein.
In conclusion the present invention provides the multinode that radiated particle strikes latch circuit in radiation environment causes is (main
If binode and three nodes) the restoration-online solution of overturning, which thereby enhance the reliability of latch circuit.With this
Simultaneously as transmission gate is inserted into so as to avoid electricity using fewer number of transistor and high speed channel technology and in output stage respectively
Stream competition, reduces circuit area overhead, delay overhead and power dissipation overhead.The invention can be effectively applicable to high reliability demand
Integrated circuit and system, can be widely applied to the field higher to latch reliability and cost requirement such as space flight and aviation.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, all any modification, equivalent and improvement made all within the spirits and principles of the present invention etc., should all include
Within protection scope of the present invention.
Claims (3)
1. a kind of completely immune latch of three internal nodes overturning, which is characterized in that including：One by 8 pairs of PN transistors
Memory module (MCell), a C cell and six transmission gates of structure；The memory module (MCell) is equipped with the first signal
Input terminal (I2), second signal input terminal (I4), third signal input part (I6), fourth signal input terminal (I8) and the first letter
Number output terminal (I1), second signal output terminal (I3), third signal output end (I5), fourth signal output terminal (I7)；The C is mono-
It is defeated that member is equipped with the first signal input part, second signal input terminal, third signal input part, fourth signal input terminal and a signal
Outlet；
Wherein, six transmission gates are respectively with identical clock：First transmission gate (TG1), the second transmission gate (TG2),
Third transmission gate (TG3), the 4th transmission gate (TG4), the 5th transmission gate (TG5), the 6th transmission gate (TG6)；First transmission
Door the signal input part of (TG1), the signal input part of second transmission gate (TG2), the third transmission gate (TG3) signal
The signal input part of input terminal, the signal input part of the 4th transmission gate (TG4) and the 5th transmission gate (TG5) is connected
It connects, data input pin of the tie point as the latch；
The signal output end of first transmission gate (TG1) and the first signal input part (I2) of the memory module (MCell)
It is connected；The signal output end of second transmission gate (TG2) and the second signal input terminal of the memory module (MCell)
(I4) it is connected；The signal output end of the third transmission gate (TG3) is inputted with the third signal of the memory module (MCell)
End (I6) is connected；The signal output end and the fourth signal of the memory module (MCell) of 4th transmission gate (TG4) are defeated
Enter end (I8) to be connected；
The first signal output end (I1) of the memory module (MCell) is connected with the first signal input part of the C cell；
The second signal output terminal (I3) of the memory module (MCell) is connected with the second signal input terminal of the C cell；It is described
The third signal output end (I5) of memory module (MCell) is connected with the third signal input part of the C cell；The storage
The fourth signal output terminal (I7) of module (MCell) is connected with the fourth signal input terminal of the C cell；
The signal output end of the C cell is connected with the signal input part of the 6th transmission gate (TG6)；
The signal output end of 5th transmission gate (TG5) is connected with the signal output end of the 6th transmission gate (TG6), even
Data output end of the contact as the latch.
2. a kind of completely immune latch of three internal nodes overturning according to claim 1, it is characterised in that：
The memory module (MCell) includes：First PMOS tube (P1), the second PMOS tube (P2), third PMOS tube (P3), the 4th
PMOS tube (P4), the 5th PMOS tube (P5), the 6th PMOS tube (P6), the 7th PMOS tube (P7), the 8th PMOS tube (P8), first
NMOS tube (N1), the second NMOS tube (N2), third NMOS tube (N3), the 4th NMOS tube (N4), the 5th NMOS tube (N5), the 6th
NMOS tube (N6), the 7th NMOS tube (N7), the 8th NMOS tube (N8)；Wherein：
The drain electrode of first PMOS tube (P1), the drain electrode of the first NMOS tube (N1), the 8th PMOS tube (P8) grid and second
The grid of NMOS tube (N2) is connected, first signal output end (I1) of the tie point as the memory module (MCell)；
The drain electrode of second PMOS tube (P2), the drain electrode of the second NMOS tube (N2), the first PMOS tube (P1) grid and third
The grid of NMOS tube (N3) is connected, first signal input part (I2) of the tie point as the memory module (MCell)；
The drain electrode of third PMOS tube (P3), the drain electrode of third NMOS tube (N3), the second PMOS tube (P2) grid and the 4th
The grid of NMOS tube (N4) is connected, second signal output terminal (I3) of the tie point as the memory module (MCell)；
The drain electrode of 4th PMOS tube (P4), the drain electrode of the 4th NMOS tube (N4), third PMOS tube (P3) grid and the 5th
The grid of NMOS tube (N5) is connected, second signal input terminal (I4) of the tie point as the memory module (MCell)；
The drain electrode of 5th PMOS tube (P5), the drain electrode of the 5th NMOS tube (N5), the 4th PMOS tube (P4) grid and the 6th
The grid of NMOS tube (N6) is connected, third signal output end (I5) of the tie point as the memory module (MCell)；
The drain electrode of 6th PMOS tube (P6), the drain electrode of the 6th NMOS tube (N6), the 5th PMOS tube (P5) grid and the 7th
The grid of NMOS tube (N7) is connected, third signal input part (I6) of the tie point as the memory module (MCell)；
The drain electrode of 7th PMOS tube (P7), the drain electrode of the 7th NMOS tube (N7), the 6th PMOS tube (P6) grid and the 8th
The grid of NMOS tube (N8) is connected, fourth signal output terminal (I7) of the tie point as the memory module (MCell)；
The drain electrode of 8th PMOS tube (P8), the drain electrode of the 8th NMOS tube (N8), the 7th PMOS tube (P7) grid and first
The grid of NMOS tube (N1) is connected, fourth signal input terminal (I8) of the tie point as the memory module (MCell)；
First PMOS tube (P1), the second PMOS tube (P2), third PMOS tube (P3), the 4th PMOS tube (P4), the 5th PMOS tube
(P5), the 6th PMOS tube (P6), the 7th PMOS tube (P7), the source electrode of the 8th PMOS tube (P8) and substrate are all connected with power supply (VDD)；
First NMOS tube (N1), the second NMOS tube (N2), third NMOS tube (N3), the 4th NMOS tube (N4), the 5th NMOS tube
(N5), the 6th NMOS tube (N6), the 7th NMOS tube (N7), the source electrode of the 8th NMOS tube (N8) and substrate are grounded (GND).
3. a kind of completely immune latch of three internal nodes overturning according to claim 1 or 2, it is characterised in that：
The C cell is made of four PMOS tube and four NMOS tubes；Wherein, four PMOS tube are respectively the 9th PMOS tube (MP1),
Ten PMOS tube (MP2), the 11st PMOS tube (MP3), the 12nd PMOS tube (MP4), four NMOS tubes are respectively the 9th NMOS tube
(MN1), the tenth NMOS tube (MN2), the 11st NMOS tube (MN3), the 12nd NMOS tube (MN4) composition；Wherein：
The grid of 12nd PMOS tube (MP4) is connected with the grid of the 12nd NMOS tube (MN4), tie point for C cell the
One signal input part；The grid of 11st PMOS tube (MP3) is connected with the grid of the 11st NMOS tube (MN3), tie point C
The second signal input terminal of unit；The grid of tenth PMOS tube (MP2) is connected with the grid of the tenth NMOS tube (MN2), connection
Third signal input part of the point for C cell；The grid of 9th PMOS tube (MP1) is connected with the grid of the 9th NMOS tube (MN1),
Tie point is the fourth signal input terminal of C cell；The drain electrode of 12nd PMOS tube (MP4) and the drain electrode of the 9th NMOS tube (MN1)
It is connected, tie point is the signal output end of C cell；
The drain electrode of 9th PMOS tube (MP1) is connected with the source electrode of the tenth PMOS tube (MP2)；The drain electrode of tenth PMOS tube (MP2)
It is connected with the source electrode of the 11st PMOS tube (MP3)；The drain electrode of 11st PMOS tube (MP3) and the 12nd PMOS tube (MP4)
Source electrode is connected；The source electrode of 9th NMOS tube (MN1) is connected with the drain electrode of the tenth NMOS tube (MN2)；Tenth NMOS tube (MN2)
Source electrode be connected with the drain electrode of the 11st NMOS tube (MN3)；The source electrode and the 12nd NMOS tube of 11st NMOS tube (MN3)
(MN4) drain electrode is connected；The source electrode of 9th PMOS tube (MP1), the substrate of the 9th PMOS tube (MP1), the tenth PMOS tube (MP2)
Substrate, the substrate of the 11st PMOS tube (MP3), the substrate of the 12nd PMOS tube (MP4) be all connected with power supply (VDD)；9th
The substrate of NMOS tube (MN1), the substrate of the tenth NMOS tube (MN2), the substrate of the 11st NMOS tube (MN3), the 12nd NMOS tube
(MN4) substrate, the source grounding of the 12nd NMOS tube (MN4).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810015566.XA CN108134597B (en) | 2018-01-08 | 2018-01-08 | Latch with three internal nodes completely immune in overturning |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810015566.XA CN108134597B (en) | 2018-01-08 | 2018-01-08 | Latch with three internal nodes completely immune in overturning |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108134597A true CN108134597A (en) | 2018-06-08 |
| CN108134597B CN108134597B (en) | 2021-05-25 |
Family
ID=62400332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810015566.XA Active CN108134597B (en) | 2018-01-08 | 2018-01-08 | Latch with three internal nodes completely immune in overturning |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108134597B (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109104167A (en) * | 2018-08-20 | 2018-12-28 | 上海华虹宏力半导体制造有限公司 | latch |
| CN109150138A (en) * | 2018-08-20 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | latch |
| CN109525236A (en) * | 2018-11-26 | 2019-03-26 | 中北大学 | The D-latch of anti-binode upset |
| CN109687850A (en) * | 2018-12-19 | 2019-04-26 | 安徽大学 | A kind of latch that any three nodes overturning is tolerated completely |
| CN110518904A (en) * | 2019-07-31 | 2019-11-29 | 安徽大学 | A kind of N-1 grades of fault filtering voting machine |
| CN111162772A (en) * | 2020-01-15 | 2020-05-15 | 合肥工业大学 | High-performance low-overhead three-point flip self-recovery latch |
| CN111988030A (en) * | 2020-08-24 | 2020-11-24 | 合肥工业大学 | Single-particle three-point overturning reinforced latch |
| CN112260679A (en) * | 2020-10-16 | 2021-01-22 | 安徽大学 | Three-node overturning self-recovery latch based on C unit |
| CN112636738A (en) * | 2020-12-28 | 2021-04-09 | 长沙理工大学 | Self-recovery latch and integrated chip allowing three-node turnover |
| CN113098449A (en) * | 2021-03-31 | 2021-07-09 | 安徽理工大学 | Three-node overturning self-recovery latch with high robustness |
| CN114900176A (en) * | 2022-05-11 | 2022-08-12 | 合肥工业大学 | Three-point overturning self-recovery latch based on heterogeneous C unit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060015786A1 (en) * | 2004-06-30 | 2006-01-19 | Intel Corporation | System and shadow bistable circuits coupled to output joining circuit |
| US20120038386A1 (en) * | 2006-05-18 | 2012-02-16 | Fujitsu Semiconductor Limited | Latch circuit |
| US20120182048A1 (en) * | 2011-01-19 | 2012-07-19 | Paul Eaton | Radiation hardened circuit design for multinode upsets |
| CN104270141A (en) * | 2014-08-14 | 2015-01-07 | 合肥工业大学 | Latch capable of resisting single event upset and single event transient pulse |
| CN104901676A (en) * | 2015-06-06 | 2015-09-09 | 合肥工业大学 | Latch resistant to single-particle multi-node overturning |
| CN106788379A (en) * | 2016-11-29 | 2017-05-31 | 合肥工业大学 | A kind of radiation hardening latch based on isomery duplication redundancy |
| CN106849913A (en) * | 2017-01-12 | 2017-06-13 | 安徽大学 | High-performance low-overhead double-node flip online self-recovery latch |
-
2018
- 2018-01-08 CN CN201810015566.XA patent/CN108134597B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060015786A1 (en) * | 2004-06-30 | 2006-01-19 | Intel Corporation | System and shadow bistable circuits coupled to output joining circuit |
| US20120038386A1 (en) * | 2006-05-18 | 2012-02-16 | Fujitsu Semiconductor Limited | Latch circuit |
| US20120182048A1 (en) * | 2011-01-19 | 2012-07-19 | Paul Eaton | Radiation hardened circuit design for multinode upsets |
| CN104270141A (en) * | 2014-08-14 | 2015-01-07 | 合肥工业大学 | Latch capable of resisting single event upset and single event transient pulse |
| CN104901676A (en) * | 2015-06-06 | 2015-09-09 | 合肥工业大学 | Latch resistant to single-particle multi-node overturning |
| CN106788379A (en) * | 2016-11-29 | 2017-05-31 | 合肥工业大学 | A kind of radiation hardening latch based on isomery duplication redundancy |
| CN106849913A (en) * | 2017-01-12 | 2017-06-13 | 安徽大学 | High-performance low-overhead double-node flip online self-recovery latch |
Non-Patent Citations (2)
| Title |
|---|
| AIBIN YAN: "High-performance, low-cost, and double node upset tolerant latch design", 《2017 IEEE 35TH VLSI TEST SYMPOSIUM (VTS)》 * |
| 黄正峰: "容忍单粒子多节点翻转的三模互锁加固锁存器", 《电子科技大学学报》 * |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109150138A (en) * | 2018-08-20 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | latch |
| CN109104167A (en) * | 2018-08-20 | 2018-12-28 | 上海华虹宏力半导体制造有限公司 | latch |
| CN109525236B (en) * | 2018-11-26 | 2022-03-08 | 中北大学 | D latch resistant to double-node overturning |
| CN109525236A (en) * | 2018-11-26 | 2019-03-26 | 中北大学 | The D-latch of anti-binode upset |
| CN109687850A (en) * | 2018-12-19 | 2019-04-26 | 安徽大学 | A kind of latch that any three nodes overturning is tolerated completely |
| CN109687850B (en) * | 2018-12-19 | 2022-09-23 | 安徽大学 | Latch completely tolerating any three-node overturning |
| CN110518904A (en) * | 2019-07-31 | 2019-11-29 | 安徽大学 | A kind of N-1 grades of fault filtering voting machine |
| CN110518904B (en) * | 2019-07-31 | 2024-03-08 | 安徽大学 | N-1 level fault filtering voter |
| CN111162772A (en) * | 2020-01-15 | 2020-05-15 | 合肥工业大学 | High-performance low-overhead three-point flip self-recovery latch |
| CN111988030A (en) * | 2020-08-24 | 2020-11-24 | 合肥工业大学 | Single-particle three-point overturning reinforced latch |
| CN112260679A (en) * | 2020-10-16 | 2021-01-22 | 安徽大学 | Three-node overturning self-recovery latch based on C unit |
| CN112260679B (en) * | 2020-10-16 | 2022-10-14 | 安徽大学 | Three-node overturning self-recovery latch based on C unit |
| CN112636738A (en) * | 2020-12-28 | 2021-04-09 | 长沙理工大学 | Self-recovery latch and integrated chip allowing three-node turnover |
| CN112636738B (en) * | 2020-12-28 | 2024-03-22 | 长沙理工大学 | Self-recovery latch allowing three-node overturn and integrated chip |
| CN113098449A (en) * | 2021-03-31 | 2021-07-09 | 安徽理工大学 | Three-node overturning self-recovery latch with high robustness |
| CN113098449B (en) * | 2021-03-31 | 2023-11-10 | 安徽理工大学 | High-robustness three-node overturning self-recovery latch |
| CN114900176A (en) * | 2022-05-11 | 2022-08-12 | 合肥工业大学 | Three-point overturning self-recovery latch based on heterogeneous C unit |
| CN114900176B (en) * | 2022-05-11 | 2024-03-05 | 合肥工业大学 | Three-point flip self-recovery latch based on heterogeneous C unit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108134597B (en) | 2021-05-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108134597A (en) | A kind of completely immune latch of three internal nodes overturning | |
| US6326809B1 (en) | Apparatus for and method of eliminating single event upsets in combinational logic | |
| CN108011628B (en) | Latch capable of tolerating three-node turnover | |
| EP2107680B1 (en) | Single-event-effect tolerant SOI-based data latch device | |
| US8324951B1 (en) | Dual data rate flip-flop circuit | |
| CN109687850B (en) | Latch completely tolerating any three-node overturning | |
| CN109905117B (en) | Latch capable of completely self-recovering by overturning any three nodes | |
| CN104901676A (en) | Latch resistant to single-particle multi-node overturning | |
| CN102723109A (en) | Novel static random access memory (SRAM) storage unit preventing single particle from turning | |
| CN106849913A (en) | High-performance low-overhead double-node flip online self-recovery latch | |
| CN103326711A (en) | Anti-radiation hardening latch based on TMR and DICE | |
| CN102522114B (en) | Register having irradiation-resistant function | |
| Devarapalli et al. | SEU-hardened dual data rate flip-flop using C-elements | |
| CN110572146B (en) | Latch capable of tolerating any three-node turnover and filtering transient pulse | |
| US8581652B2 (en) | Flip-flop circuit, semiconductor device and electronic apparatus | |
| CN106936410B (en) | High-speed low-power-consumption reinforced latch | |
| CN106656149A (en) | Single event upset on-line self-recovery latch with high performance and low overhead | |
| Liu et al. | A power-delay-product efficient and SEU-tolerant latch design | |
| CN114337611A (en) | Three-node overturning self-recovery latch based on cyclic feedback C unit | |
| Casey et al. | Single-event tolerant latch using cascode-voltage switch logic gates | |
| Qi et al. | A 13T radiation-hardened memory cell for low-voltage operation and ultra-low power space applications | |
| CN110518904B (en) | N-1 level fault filtering voter | |
| CN110912551A (en) | Single-particle three-point upset reinforced latch based on DICE unit | |
| CN204068926U (en) | Apply the radioresistance latch of four input protection doors | |
| CN111865291B (en) | Latch capable of resisting double-node overturning |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |