CN104700889B - The memory cell of static random-access memory based on DICE structures - Google Patents
The memory cell of static random-access memory based on DICE structures Download PDFInfo
- Publication number
- CN104700889B CN104700889B CN201510142476.3A CN201510142476A CN104700889B CN 104700889 B CN104700889 B CN 104700889B CN 201510142476 A CN201510142476 A CN 201510142476A CN 104700889 B CN104700889 B CN 104700889B
- Authority
- CN
- China
- Prior art keywords
- drain electrode
- grid
- memory cell
- bit line
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000015654 memory Effects 0.000 title claims abstract description 63
- 230000003068 static effect Effects 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 238000003860 storage Methods 0.000 claims description 35
- 239000002245 particle Substances 0.000 abstract description 25
- 230000001052 transient effect Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 10
- 238000007667 floating Methods 0.000 description 7
- 230000014759 maintenance of location Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 230000005855 radiation Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000001235 sensitizing effect Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 230000002452 interceptive effect Effects 0.000 description 2
- 230000002441 reversible effect Effects 0.000 description 2
- 108010032595 Antibody Binding Sites Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013501 data transformation Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 239000011164 primary particle Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Landscapes
- Static Random-Access Memory (AREA)
Abstract
The present invention proposes a kind of memory cell of the static random-access memory based on DICE structures, including redundancy latch cicuit and redundant digit selection circuit, and redundancy latch cicuit is made up of 4 metal-oxide-semiconductors, including 4 dot data memories；Redundant digit selection circuit is also made up of 4 metal-oxide-semiconductors, and metal-oxide-semiconductor M0, M1, M2, M3 drain electrode are connected on 4 dot data memories X0, X1, X2, X3；Wherein M0, M2 source electrode link together, and are connected to bit line BL；M1, M3 source electrode link together, and are connected to bit line BLB；The grid of 4 metal-oxide-semiconductors links together, and is connected to wordline WL.The present invention is not increasing obvious complexity, and only increasing a small amount of area can ensure memory cell by generating state is not overturn during particle bombardment, it is ensured that data are correct.
Description
Technical field
The invention belongs to IC design and manufacturing technology, it is related to static random-access memory, more particularly to one
The memory cell of the static random-access memory based on DICE structures is planted, military field, civil area and business is can be applied to
With space field, be particularly suitable for use in high-performance, high-density radioresistance application.
Background technology
Single-particle inversion is the important parameter of radiation hardened.Single-particle inversion or soft error, refer to data storage
Once nondestructive data transformation on position.Charged particle (such as cosmic ray or trap proton) injects semiconductor devices, leads to
Cross and interacted with semi-conducting material, soon lose energy.The energy of loss makes electronics jump to conduction band up from valence band.In
It is to have electronics in conduction band, hole is left in valence band, form electron hole pair, introduces nonequilibrium carrier.Without electric field
When, nonequilibrium carrier will occur diffusion, be combined, and finally disappear.When having electric field, nonequilibrium carrier (electron hole pair) will divide
Collected from by electrode, form transient current.Transient current can make node potential change, cause device logic state to overturn；Or
Propagated along signal transmission path, so as to disturb circuit normal function.For CMOS SRAM memory cell, the leakage of blanking tube
The space-charge region of area's reverse biased pn junction constitutes device single-particle inversion sensitive volume, and its electric field is enough to separate electron hole pair, and
Collected by electrode.
Typical memory cell has 6T structures now.Intersect as shown in figure 1,6T sram cells include two identicals
The phase inverter of connection, the output for forming the phase inverter of latch cicuit, i.e., one is connected to the input of another phase inverter.Latch cicuit
It is connected between power supply and ground potential.Each phase inverter respectively includes crystal pulling on NMOS pull-down transistor N1 or N2 and PMOS
Pipe P1 or P2.Phase inverter is output as two memory nodes Q and QB.It is another when one of memory node is pulled down to low-voltage
Individual memory node is pulled to high voltage, forms complementary pair.Paratope line is to BL and BLB respectively via a pair of transmission gate transistor N3
Memory node Q and QB are connected to N4.Transmission gate transistor N3 and N4 grid are connected to wordline WL.
Assuming that it is high voltage that the state of the memory cell, which is " 1 ", i.e. Q, QB is low-voltage, the conducting of P1 and N2 pipes, N1 and P2
Pipe cut-off, the reverse biased pn junction space-charge region in N1 and P2 pipes drain region is exactly the single-particle inversion sensitive volume of device.For N1 pipes, wink
State electric current makes drain electrode (i.e. Q stores point) voltage reduction, is coupled to P2 and N2 grid, makes the cut-off of N2 pipes, the conducting of P2 pipes, the leakage of N2 pipes
Pole (i.e. QB stores point) voltage rise, feeds back to the grid of P1, N1 pipe, ends P1 pipes, N1 pipes conducting, state of memory cells is thorough
Bottom is changed into " 0 " from " 1 ".That is under radiation environment, single-particle inversion easily occurs for 6T structure Storage Units.Make storage content
It is interfered, the wrong value will remain to the memory cell and be written over next time.
Hit to solve high energy particle (high energy proton, heavy ion) after memory node, the list for causing memory cell to occur
Particle flop phenomenon, is generally reinforced using technique and circuit design reinforces two kinds of means.Circuit design, which is reinforced, generally has three kinds of solutions
Certainly method.Method one is the memory node power-up perhaps resistance delay cell in memory cell, as shown in Figures 2 and 3.Powered
Particle is incident, N1 pipe drain potentials is dropped to low-voltage, but P1 is managed when still turning on, unstable during state of memory cells, deposits
In the competition of two processes.On the one hand, power supply is charged by P1 to the gate capacitance of N2 pipes, N1 pipes drain voltage is increased, and is recovered
To original state；On the other hand, N1 pipes drain voltage is reduced, and is coupled to another inverter gate, then feed back so that N1
Pipe is turned on, the cut-off of P1 pipes, state of memory cells upset.By increasing RC delays, transient current makes the time that logic circuit is overturn
It is delayed by, and then causes have the time to make this spike transient current cause node voltage change to return to initial value.This method
Shortcoming be on chip needed for resistance capacitance value it is larger, resistance capacitance area is excessive, and the write time greatly increases.Method two
It is between two memory nodes plus coupled capacitor, as shown in Figure 4.The principle of this method is when one of node is by high energy
After particle is hit, produce transient current and cause the voltage of one of node to occur saltus step, the voltage of another node is coupled
Unidirectional saltus step also occurs for the influence of electric capacity, so that memory cell can not be overturn.This method is similarly subjected to system
Make electric capacity difficulty and area limitation, and the write time limitation.Method three is that storage information is carried out using many pipe units
Redundancy is preserved, 12T DICE structures as shown in Figure 5.By the way that 4 phase inverters are end to end, wherein memory node respectively with it is preceding
One-level NMOS is connected with the PMOS of rear stage so that positive and negative data storage is all preserved by redundancy, once some memory node is sent out
Raw single-particle inversion, its node voltage connected can only influence the memory node of previous stage or rear stage, be not affected that
One-level is recovered to the information of the memory node of saltus step.The shortcoming of this method is that transistor number is too many, and area is excessive.
The content of the invention
The purpose of the present invention is to propose to a kind of memory cell of the static random-access memory based on DICE structures, do not increase
Plus obvious complexity, only increasing a small amount of area can ensure that memory cell, by generating state is not overturn during particle bombardment, is protected
Demonstrate,prove data correct.
The memory cell of static random-access memory proposed by the present invention based on DICE structures, based on use multitube list
Member carries out the thought of redundancy preservation to memory cell, and basic unit of storage is carried out into redundancy backup, realized primary particle inversion resistant
Purpose.Optimize elementary cell simultaneously, its transistor size is reduced, so as to reduce the area overhead of radiation hardened memory cell.This
The memory cell of the static random-access memory based on DICE structures proposed is invented as shown in fig. 6, including redundancy lock
Deposit circuit and redundant digit selection circuit；Redundancy latch cicuit is made up of 4 metal-oxide-semiconductors M4, M5, M6, M7, M4 drain electrode and M7
Grid be connected, M5 drain electrode is connected with M4 grid, and M6 drain electrode is connected with M5 grid, M7 drain and M6 grid phase
Even；M4, M5, M6, M7 drain electrode connect dot data memory X0, X1, X2, X3 respectively；Redundant digit selection circuit by 4 metal-oxide-semiconductor M0,
M1, M2, M3 are constituted, and metal-oxide-semiconductor M0, M1, M2, M3 drain electrode is connected on 4 dot data memories X0, X1, X2, X3；Its
In, M0, M2 source electrode link together, and are connected to bit line BL；M1, M3 source electrode link together, and are connected to bit line BLB；4 MOS
Pipe M0, M1, M2, M3 grid link together, and are connected to wordline WL.
The present invention is carried out by reducing the transistor size of basic unit of storage to the storage point of basic unit of storage
" bimodulus " forms interlocking design afterwards, while realizing radiation hardened, and area overhead is small.
Brief description of the drawings
Fig. 1 is traditional 6TSRAM memory cell；
Fig. 2 is the memory cell of memory node plus resistance capacitance；
Fig. 3 is the memory cell that resistance capacitance is replaced with mos electric capacity；
Fig. 4 is the memory cell of memory node plus coupled capacitor；
Fig. 5 is DICE structure Storage Units；
Fig. 6 is present invention design circuit diagram；
Fig. 7 is first embodiment of the present invention circuit diagram；
Fig. 8 is second embodiment of the present invention circuit diagram.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in more detail.
Fig. 6 is present invention design circuit diagram, and Fig. 7, Fig. 8 are respectively two embodiments of the present invention, below with reference to
The two embodiments are specifically described.
Embodiment one
As shown in fig. 7, the embodiment includes redundancy latch cicuit and redundant digit selection circuit.Redundancy latches electricity
It route the end to end composition of NMOS tube N0, N1, N2, N3；N0 grid is connected with N1 drain electrode, is connected to storage point X1；N1's
Grid is connected with N2 drain electrode, is connected to storage point X2；N2 grid is connected with N3 drain electrode, is connected to storage point X3；N3's
Grid is connected with N0 drain electrode, is connected to storage point X0；N0, N1, N2, N3 source grounding.Redundant digit selection circuit by
PMOS P0, P1, P2, P3 are constituted；P0 drain electrode connection X0, P1 drain electrode connection X1, P2 drain electrode connection X2, P3 drain electrode connect
Meet X3；P0 and P2 source electrode links together, and is connected to bit line BL；P1 and P3 source electrode links together, and is connected to bit line BLB；P0、
P1, P2, P3 grid link together, and are connected with wordline WL.
Bit line is charged to high level to BL and BLB in advance, and wordline WL is pulled low, and starts read operation, until wordline WL is changed into high
Level, read operation terminates；Write driving and BL (or BLB) be pulled down to low level, wordline WL is set to low level, start to write " 0 " (or
Person's one writing) operation, until wordline WL is changed into high level, write operation terminates.During hold mode, bit line is all high electricity to BL and BLB
Flat, wordline WL is also high level.The high level of the memory cell be in floating, the present embodiment by using different threshold values,
So that electric leakage of the electric leakage more than nmos device of PMOS device, it is ensured that the high level of unit is able to maintain that.Due to high level floating,
The storage state of the unit is referred to alternatively as weak H and strong L.
Charge-trapping sensitizing range is the reverse-biased region for causing to have highfield of PN junction in metal-oxide-semiconductor, when these regions of particle bombardment
When, the electron hole pair ionized out is separated under electric field action, is collected by electrode, forms transient current.Under hold mode, institute
It is charge-trapping sensitizing range to have the drain region of PMOS and the drain region of the NMOS tube of shut-off.When single-particle beats sensitive in charge-trapping
When area causes the level to overturn, level upset will not spread all over 4 storage points, cause state thoroughly to overturn.It is false as shown in Fig. 7 structures
If memory cell stores high level, i.e. X0=" weak H ", X1=" strong L ", X2=" weak H ", X3=" strong L ".Divide situation discussion below
The anti-single particle rollover characteristics of the unit.
Situation one：Particle bombardment is to P1 pipes drain region.X1 storages point produces transient current, and it is weak H by strong L upsets to cause X2；
And then open N0 pipes so that X0 points are L by weak H drop-downs, cause N3 pipes to turn off；N3 pipes are turned off so that the L level floating of X3 points,
It is changed into weak L；X3 dotted states are not overturn, therefore X2 points are unaffected.A period of time after upset, because N1 pipes are unaffected, one
Direct-open, the X1 points of upset return to original state, i.e., strong L；So as to turn off N0 so that X0 points turn into weak L.In summary, pass through
Cross after single event, unit is by original state, i.e. " " " " strong L " is changed into new to X0=by weak H ", X3=by strong L ", X2=by weak H ", X1=
State X0=" weak L ", X1=" strong L ", X2=" weak H ", X3=" weak L ".New state does not influence read operation, during reading, according to
It is so that BLB declines soon, when BL-BLB reaches certain pressure difference, SA, which is opened, reads data, is high level.I.e. read operation is arrived
When, the data of reading are identical with former data；Bit line is to storage point charging during due to read operation, and storage point can revert to starting shape
State X0=" weak H ",
X1=" strong L ", X2=" weak H ", X3=" strong L ".
Situation two：Particle bombardment is to N0 pipes drain region.X0 storages point produces transient current, causes X0 to be changed into weak L from weak H；Enter
And N3 pipes are turned off, X3 is changed into weak L from strong L.X1 and X2 storages point is unaffected.After single event, unit is by initial shape
State is that " " " " strong L " is changed into new state X0=" weak L ", X1=" strong L ", X2 to X0=by weak H ", X3=by strong L ", X2=by weak H ", X1=
=" weak H ", X3=" weak L ".It is identical with the first situation, the read operation after not interfering with, while read operation can also make storage
Unit reverts to original state.
Embodiment two
As shown in figure 8, equally including redundancy latch cicuit and redundant digit selection circuit.Redundancy latch cicuit by
PMOS P0, P1, P2, P3 are end to end to be constituted；P0 grid is connected with P3 drain electrode, is connected to storage point X3；P1 grid
It is connected with P0 drain electrode, is connected to storage point X0；P2 grid is connected with P1 drain electrode, is connected to storage point X1；P3 grid
It is connected with P2 drain electrode, is connected to storage point X2；P0, P1, P2, P3 source electrode link together, and connect power supply.Redundant digit selection electricity
NMOS tube N0, N1, N2, N3 is route to constitute.N0 drain electrode connection X0, N1 drain electrode connection X1, N2 drain electrode connection X2, N3 leakage
Pole connects X3；N0 and N2 source electrode links together, and is connected to bit line BL；N1 and N3 source electrode links together, and is connected to bit line
BLB；N0, N1, N2, N3 grid link together, and are connected with wordline WL.
Bit line is set to low level to BL and BLB, and wordline WL is set to high level, starts read operation, until wordline WL is changed into
Low level, read operation terminates；Write driving and BL (or BLB) is pulled down to low level, wordline WL is set to high level, starts to write " 0 "
(or one writing) is operated, and until wordline WL is changed into low level, write operation terminates.During hold mode, bit line to BL and BLB and
Wordline WL is low level.The low level of the memory cell is by using different threshold values in floating, the present embodiment so that
Electric leakage of the electric leakage more than PMOS device of nmos device, it is ensured that the low level of unit is able to maintain that.Due to low level floating, the list
The storage state of member is referred to alternatively as weak L and strong H.
Charge-trapping sensitizing range is the reverse-biased region for causing to have highfield of PN junction in metal-oxide-semiconductor, when these regions of particle bombardment
When, the electron hole pair ionized out is separated under electric field action, is collected by electrode, forms transient current.Under hold mode, institute
It is charge-trapping sensitizing range to have the drain region of NMOS tube and the drain region of the PMOS of shut-off.When single-particle beats sensitive in charge-trapping
When area causes the level to overturn, level upset will not spread all over 4 storage points, cause state thoroughly to overturn.It is false as shown in Fig. 8 structures
If memory cell stores high level, i.e. X0=" strong H ", X1=" weak L ", X2=" strong H ", X3=" weak L ".Divide situation discussion below
The anti-single particle rollover characteristics of the unit.
Situation one：Particle bombardment is to N0 pipes drain region.X0 storages point produces transient current, causes X0 to be changed into weak L from strong H；Enter
And opening P1 pipes so that X1 is pulled up as H by weak L, causes P2 pipes to turn off；P2 pipes are turned off so that X2 H level floating, are changed into
Weak H；X2 dotted states are not overturn, therefore X3 dotted states are unaffected.Overturn after a period of time, because P0 pipes are always on, turn over
The X0 points turned can be electrically charged, and return to reset condition, i.e., strong H；So as to turn off P1 so that X1 floatings, become weak H.In summary,
After single event, unit is by original state, i.e. " " " " weak L " is changed into X0=by strong H ", X3=by weak L ", X2=by strong H ", X1=
New state X0=" strong H ", X1=" weak H ", X2=" weak H ", X3=" weak L ".During reading, bit line is set to low level, opens word
Line, opens read operation.Therefore, new state does not influence read operation, is still BLB and declines soon, when BL-BLB reaches a level pressure
When poor, SA, which is opened, reads data, is high level.I.e. read operation comes interim, and the data of reading are identical with former data；Due to read operation
When bit line will store point X1 and X3 states with being pulled low to, P2 pipes are opened, therefore after read operation terminates, X1 is from " weak H " is changed into " weak
L ", X2 are from " weak H " is changed into " strong H ".That is storage point reverts to initial state X0=" strong H ", X1=" weak L ", X2=" strong H ", X3
=" weak L ".
Situation two：Particle bombardment is to P1 pipes drain region.X1 storages point produces transient current, and it is weak H by weak L upsets to cause X1；
And then turning off P2 pipes so that X2 points are changed into weak H from strong H.X3 and X0 storages point is unaffected.After particle bombardment, unit is by first
" " " " weak L " is changed into new state X0=" strong H ", X1=" weak H ", X2 to beginning state X0=by strong H ", X3=by weak L ", X2=by strong H ", X1=
=" weak H ", X3=" weak L ".It is identical with the first situation, the read operation after not interfering with, while read operation can also make storage
Unit reverts to original state.
Both examples above only needs 8 transistors, and area overhead is small, it can be seen that the embodiment of the present invention can not increase
Plus substantially the memory cell of SRAM is not sent out under radiation environment in the case of complexity, a small amount of area of increase
Raw single-particle inversion, its compatible universal CMOS technology is easily realized.
Particular embodiments described above, has been carried out further in detail to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail it is bright, should be understood that the foregoing is only the present invention specific embodiment, be not intended to limit the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvements done etc., should be included in the guarantor of the present invention
Within the scope of shield.
Claims (3)
1. the memory cell of the static random-access memory based on DICE structures, it is characterised in that redundancy latch cicuit
With redundant digit selection circuit；Redundancy latch cicuit is made up of 4 metal-oxide-semiconductors M4, M5, M6, M7, M4 drain electrode and M7 grid
It is connected, M5 drain electrode is connected with M4 grid, and M6 drain electrode is connected with M5 grid, and M7 drain electrode is connected with M6 grid；M4、
M5, M6, M7 drain electrode connect dot data memory X0, X1, X2, X3 respectively；Redundant digit selection circuit by 4 metal-oxide-semiconductor M0, M1, M2,
M3 is constituted, and metal-oxide-semiconductor M0, M1, M2, M3 drain electrode is connected on 4 dot data memories X0, X1, X2, X3；Wherein, M0,
M2 source electrode links together, and is connected to bit line BL；M1, M3 source electrode link together, and are connected to bit line BLB；4 metal-oxide-semiconductor M0,
M1, M2, M3 grid link together, and are connected to wordline WL.
2. the memory cell of the static random-access memory as claimed in claim 1 based on DICE structures, it is characterised in that
Redundancy latch cicuit is constituted by NMOS tube N0, N1, N2, N3 are end to end；N0 grid is connected with N1 drain electrode, is connected to
Store point X1；N1 grid is connected with N2 drain electrode, is connected to storage point X2；N2 grid is connected with N3 drain electrode, is connected to
Store point X3；N3 grid is connected with N0 drain electrode, is connected to storage point X0；N0, N1, N2, N3 source grounding；
Redundant digit selection circuit is made up of PMOS P0, P1, P2, P3；P0 drain electrode connection X0, P1 drain electrode connection X1, P2's
Drain electrode connection X2, P3 drain electrode connection X3；P0 and P2 source electrode links together, and is connected to bit line BL；P1 and P3 source electrode connection
Together, it is connected to bit line BLB；P0, P1, P2, P3 grid link together, and are connected with wordline WL.
3. the memory cell of the static random-access memory as claimed in claim 1 based on DICE structures, it is characterised in that
Redundancy latch cicuit is constituted by PMOS P0, P1, P2, P3 are end to end；P0 grid is connected with P3 drain electrode, is connected to
Store point X3；P1 grid is connected with P0 drain electrode, is connected to storage point X0；P2 grid is connected with P1 drain electrode, is connected to
Store point X1；P3 grid is connected with P2 drain electrode, is connected to storage point X2；P0, P1, P2, P3 source electrode connect power supply；
Redundant digit selection circuit is made up of NMOS tube N0, N1, N2, N3；N0 drain electrode connection X0, N1 drain electrode connection X1, N2's
Drain electrode connection X2, N3 drain electrode connection X3；N0 and N2 source electrode links together, and is connected to bit line BL；N1 and N3 source electrode connection
Together, it is connected to bit line BLB；N0, N1, N2, N3 grid link together, and are connected with wordline WL.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510142476.3A CN104700889B (en) | 2015-03-27 | 2015-03-27 | The memory cell of static random-access memory based on DICE structures |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510142476.3A CN104700889B (en) | 2015-03-27 | 2015-03-27 | The memory cell of static random-access memory based on DICE structures |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104700889A CN104700889A (en) | 2015-06-10 |
| CN104700889B true CN104700889B (en) | 2017-08-25 |
Family
ID=53347929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510142476.3A Active CN104700889B (en) | 2015-03-27 | 2015-03-27 | The memory cell of static random-access memory based on DICE structures |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104700889B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105049031A (en) * | 2015-07-29 | 2015-11-11 | 西北工业大学 | DICE structure latch unit resisting single-particle irradiation effect |
| CN109917269B (en) * | 2019-01-25 | 2021-10-01 | 中国科学院微电子研究所 | Single high-energy particle ionization charge test circuit |
| CN111161785A (en) * | 2019-12-31 | 2020-05-15 | 展讯通信（上海）有限公司 | Static random access memory and fault detection circuit thereof |
| CN113593621A (en) * | 2021-07-19 | 2021-11-02 | 上海华虹宏力半导体制造有限公司 | SRAM memory cell capable of double-node inversion |
| CN113593620A (en) * | 2021-07-19 | 2021-11-02 | 上海华虹宏力半导体制造有限公司 | Soft error resistant SRAM memory cell |
| CN113724754A (en) * | 2021-08-27 | 2021-11-30 | 上海华虹宏力半导体制造有限公司 | SRAM memory cell with improved read reliability |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102176322A (en) * | 2011-01-28 | 2011-09-07 | 中国航天科技集团公司第九研究院第七七一研究所 | Single-event-proximity-effect-resistant static storage unit of physical space interleaving type |
| CN103021456A (en) * | 2012-12-19 | 2013-04-03 | 电子科技大学 | Nonvolatile high-resistance single-particle configuration memory unit |
| CN103366802A (en) * | 2013-06-26 | 2013-10-23 | 清华大学 | Static random storage unit |
| CN103903645A (en) * | 2012-12-28 | 2014-07-02 | 中国科学院微电子研究所 | Static random access memory unit with radiation reinforcement design |
| CN103956184A (en) * | 2014-05-16 | 2014-07-30 | 中国科学院微电子研究所 | Improved SRAM (static random Access memory) storage unit based on DICE (digital imaging and instrumentation) structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8363455B2 (en) * | 2008-12-04 | 2013-01-29 | David Rennie | Eight transistor soft error robust storage cell |
-
2015
- 2015-03-27 CN CN201510142476.3A patent/CN104700889B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102176322A (en) * | 2011-01-28 | 2011-09-07 | 中国航天科技集团公司第九研究院第七七一研究所 | Single-event-proximity-effect-resistant static storage unit of physical space interleaving type |
| CN103021456A (en) * | 2012-12-19 | 2013-04-03 | 电子科技大学 | Nonvolatile high-resistance single-particle configuration memory unit |
| CN103903645A (en) * | 2012-12-28 | 2014-07-02 | 中国科学院微电子研究所 | Static random access memory unit with radiation reinforcement design |
| CN103366802A (en) * | 2013-06-26 | 2013-10-23 | 清华大学 | Static random storage unit |
| CN103956184A (en) * | 2014-05-16 | 2014-07-30 | 中国科学院微电子研究所 | Improved SRAM (static random Access memory) storage unit based on DICE (digital imaging and instrumentation) structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104700889A (en) | 2015-06-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104700889B (en) | The memory cell of static random-access memory based on DICE structures | |
| US5111429A (en) | Single event upset hardening CMOS memory circuit | |
| CN103956184B (en) | Improved SRAM (static random Access memory) storage unit based on DICE (digital imaging and instrumentation) structure | |
| CN103778954B (en) | The memorizer of anti-multiple node upset | |
| CN108766492B (en) | SEU (single event unit) resistant memory cell circuit with low single event sensitivity | |
| CN102723109B (en) | Novel static random access memory (SRAM) storage unit preventing single particle from turning | |
| CN105336362B (en) | The static random access memory of radiation hardening | |
| CN103474092A (en) | Anti-radiation hardened storage cell circuit | |
| CN105897223A (en) | D trigger resistant to single event upset | |
| CN104022773A (en) | DICE (dual interlocked storage cell)-based novel SEU (single event upset)-resistant reinforced SR latch | |
| CN103337252A (en) | Static random access memory (SRAM) with redundant structure | |
| CN104637530A (en) | Random access memory with redundant structure | |
| US10192612B2 (en) | Memory cell of static random access memory based on resistance hardening | |
| CN103366802B (en) | A kind of static ram cell | |
| CN104851450A (en) | Resistor-capacitor reinforcement based memory cell of static random access memory | |
| WO2016154825A1 (en) | Dice structure-based storage unit of static random access memory | |
| CN104409093A (en) | Differential ten-tube storage cell resistant to single-event upset | |
| CN111128271A (en) | RHPD-12T radiation-resistant SRAM memory cell circuit | |
| Zhang et al. | A novel single event upset hardened CMOS SRAM cell | |
| CN116386694A (en) | Circuit structure, chip and module of anti-radiation latch based on polarity reinforcement | |
| CN116318056A (en) | Radiation-resistant Latch circuit and module utilizing source isolation reinforcement and polarity reinforcement | |
| WO2016154824A1 (en) | Resistor-capacitor reinforcement-based memory cell of static random access memory | |
| US9564208B2 (en) | Low power radiation hardened memory cell | |
| CN114999545A (en) | NRHC-14T radiation-resistant SRAM memory cell, chip and module | |
| CN104851451B (en) | The memory cell for the static random-access memory reinforced based on resistance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |