CN105895635A - 互补式金氧半场效晶体管结构及制作其的方法 - Google Patents

互补式金氧半场效晶体管结构及制作其的方法 Download PDF

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CN105895635A
CN105895635A CN201510843117.0A CN201510843117A CN105895635A CN 105895635 A CN105895635 A CN 105895635A CN 201510843117 A CN201510843117 A CN 201510843117A CN 105895635 A CN105895635 A CN 105895635A
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effect transistor
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CN105895635B (zh
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理查·肯尼斯·奥克兰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明揭露一种互补式金氧半场效晶体管结构及制作其的方法。堆叠的互补式晶体管使用选择性沉积技术来形成一个直立柱体，下部包含一半导体的类型(例如锗)，上部包含另一种类型的半导体(例如砷化铟)。垂直柱体下部提供一类型晶体管的通道区，上部提供另一类型晶体管的通道区。这提供一种占据最小集成电路表面积的互补对。这种互补式晶体管可以使用于各种电路图。以上叙述为互补式晶体管，下方晶体管为p型晶体管，上方晶体管为n型晶体管。本发明的实施例的优点是提供互补式晶体管，其中该晶体管使用一最小的集成电路表面积。

Description

互补式金氧半场效晶体管结构及制作其的方法
技术领域
本发明主要和半导体装置结构相关，在特定的实施例中，提供了直立式互补式晶体管和堆叠结构的方法。
背景技术
为了在集成电路上放进更多的装置，这在发明集成电路中的半导体制造上已经成为一重要目标。更高的电路密度可以制造更高效能的装置并大幅降低基础晶体管的费用。电路元件的传统配置是水平分布于半导体基板的表面。这提供了制造上的简易度和降低复杂度。然而，现今半导体设计工程师正在水平式装置的众多限制上挣扎。
最大的挑战是光学微影的极限。我们通过光学微影中，一层称为光阻的感光材料涂覆在装置上，然后光阻根据特定分层设计的样式曝露在一光学图案中。然而，集成电路中的组成已经小到尺寸和光阻曝光的光波长为同一级。尽管在各种合理的期待中使用各种技术来推展这个极限，从某一点来看，这个物理上的限制是无法克服的。
为了正视这项挑战，工程师设计直立方向的装置。这些装置在制造上很复杂，然而，它们掌握了提供小型化功能性装置的前景，使用更多的半导体表面积却不需使用光学微影中更小的样式。其中一项直立式装置就是环绕式栅极(VGAA)或纳米线(NW)装置。
值得注意的是，先前的环绕式栅极或纳米线技术提供特定传导类型的晶体管。在互补式金属氧化半导体(CMOS)技术中，倾向于将每个n型金属氧化物半导体连接到p型金属氧化物半导体。这使互补式金属样化物半导体电路中的关闭状态漏流降到最低。为了达成，使用先前的环绕式栅极技术必须提供分开的n型通道和p型通道区域，所以会占据更多的集成电路表面积。
发明内容
依据本发明其中一实施例，提供一种互补式晶体管结构。一柱体下部包含一半导电材料，例如锗，形成于一基板上，该基板包含另一种半导电材料，例如硅。一第一栅极环绕柱体下部并与其绝缘。一柱体上部包含另一种半导电材料，例如砷化铟。一第二栅极环绕柱体上部并与其绝缘。一第一电性接点连接柱体上部，该第一电性接点在第二栅极上；一第二电性接点连接柱体上部和柱体下部，该第二电性接点在第一栅极和第二栅极中间。
依据本发明另一实施例，提供形成互补式晶体管的方法。一第二半导电材料在一半导电性基板上形成柱体下部，该半导电性基板包含一第一半导电材料。该第一半导电材料可以使用一选择性化学气相沉积制程形成。形成一第一栅极环绕柱体下部并与其绝缘。形成一柱体上部，其包含一第三半导电材料。第三半导电材料使用一选择性化学气相沉积制程形成，以第一半导体材料为成核位置。形成一第二栅极环绕柱体上部并与其绝缘。再形成电性接点连接柱体上部，其中该接点在第二栅极上；以及形成电性接点连接柱体上部和下部，其中该接点在第一栅极和第二栅极中间。
本发明的实施例的优点是提供互补式晶体管，其中该晶体管使用一最小的集成电路表面积。
附图说明
为了更完整的了解本发明以及其优点，请搭配以下的文字和图片当作参考，其中：
图1绘示根据本发明一实施例的一对堆叠的互补式晶体管的侧面示意图。
图2绘示根据图1的实施例的等效电路图；
图3绘示根据图1的实施例的平面示意图；
图4A至图4V绘示一制程的平面示意图，该制程包括本发明另一实施例以形成图1所示的实施例；
图5A至图5E绘示图4A至图4V的替代制程步骤，其中替代步骤包含本发明另一实施例；
图6A至图6W绘示根据本发明再一实施例的制程，该制程形成一对堆叠的互补式晶体管，其中包含本发明又一实施例。
具体实施方式
以下将详细讨论本实施例的制造与使用，然而，应了解到，本发明提供实务的创新概念，其中可以用广泛的各种特定内容呈现。底下讨论的特定实施例仅为说明，并不能限制本发明的范围。
以下将以特定的内容描述本发明的实施例，就是使用堆叠直立环绕式(VGAA)或纳米线(NW)晶体管当结构。尽管如此，本发明的创新概念并不局限于特定结构的形成。事实上，本发明的创新概念也可用于其他结构形成。此外，即便本发明指向直立环绕式或纳米线电路的实施例，本发明的创新概念可用于其他类型的集成电路、电子结构以及其他相关。以下请参照附图简单说明的文字做调整：
图1绘示根据本发明一实施例的侧面示意图。基板10是一硅晶体基板，其中掺杂是为提供导电性。锗纳米线12形成于基板10的表面上并提供通道区给p型晶体管20。砷化铟纳米线14形成于纳米线12上，提供通道区给n型晶体管30。经由接点16提供一低参考电压Vss至纳米线14的上方。经由接点18提供一高参考电压Vdd至基板10。需要注意的是，不应该将Vdd分开于每个晶体管对。一接点如接点18可以提供Vdd至许多晶体管对。
栅极22和24分别作为晶体管20和30的栅极。栅极绝缘体26隔开栅极22和纳米线12。栅极绝缘体28隔开栅极24和纳米线14。在此实施方式中，接点32将栅极22和24相互连接。然而，在其他型态里，为了允许不同的电路型态，栅极22和24可能有分开的接点。输出接点34与纳米线14相连，靠近于纳米线12和14中间的接点。这提供一输出至反相器，该反向器由晶体管20和30形成。
图2绘示图1装置的等效电路图，其中相对标注各组件。图3绘示图1装置的平面示意图。
图4A至图4V绘示制程步骤的侧面示意图，该制程形成图1的实施例。一底部间隔层42设置于基板10上。基板10可由许多晶体半导电材料之一，例如硅晶体所形成。在基板10上植入掺杂物以提供导电性。间隔层42可以是氧化硅、氮化硅、类似材料或其组合。然后栅极接点金属22沉积于间隔层42之上。栅极接点金属22可以是多晶硅、氮化钛、氮化钽、钨、铝或类似材料或其组合。这提供了如图4A所示的结构。然后使用标准微影蚀刻技术图案化栅极接点金属22以提供如图4B所示的结构。
接着使用化学气相沉积或类似的技术将一介电填充层加到间隔层42的外露部分。再使用一般的化学机械研磨(CMP)技术将复合层42平坦化，以提供如图4C所示的结构。介电填充层可以是氧化硅、氮化硅、类似材料或其组合。一额外的介电填充层再形成于复合层42之上，以提供如图4D所示的结构。此介电填充层使用标准沉积技术沉积后并使用标准化学机械研磨(CMP)平坦化，介电填充层可包含氧化硅、氮化硅或类似材料或其组合。形成此介电填充层的步骤可以是沉积后再化学机械研磨，或是沉积后化学机械研磨，并再次沉积。
图4E绘示下一步骤，其中使用标准金属沉积技术沉积漏极接点金属44。漏极接点金属44可以是钛、氮化钛、氮化钽、钨、铝或类似材料或其组合。如图4F所示，然后使用标准微影与蚀刻技术图案化漏极接点金属44。如图4F所示，使用标准沉积和化学机械研磨技术扩充复合层42，以形成第二层纳米线晶体管30的底部间隔(见图1)。形成此介电层的步骤可以是沉积后再化学机械研磨，或是沉积后化学机械研磨，并再次沉积。此介电填充层可以是氧化硅、氮化硅、类似材料或其组合。
如图4H所示，蚀刻出一开口46，穿过介电层42、漏极接点金属44和栅极接点金属22直到基板10。可以使用反应式离子蚀刻或干式蚀刻来蚀刻出开口46，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气、氩或其他已知蚀刻气体或其组合。如图4I所示，使用标准共形沉积技术来沉积一栅极介电层48。栅极介电层48可以是二氧化硅、二氧化铪、三氧化二铝、二氧化锆或类似材料或其组合。栅极介电层48可能包含一高介电系数介电材料。此介电层厚度介于1～10nm。再使用非等向性蚀刻将栅极介电层48蚀刻出如图4J所示的型态。此非等向性蚀刻制程可以是反应式离子蚀刻或干式蚀刻，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气、氩或其他已知蚀刻气体或其组合。
如图4K所示，接着使用一选择性磊晶技术，例如有机金属化学气相沉积(MOCVD)，以硅基板当成核位置沉积第一纳米线12。在一实施例中，纳米线12包含锗晶体。如图4L所示，栅极介电层48再额外蚀刻直到该栅极介电层48的顶端低于纳米线12的顶端约5～15nm。此蚀刻制程可以是反应式离子蚀刻或干式蚀刻，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气、氩或其他已知蚀刻气体或其组合；或使用湿式蚀刻，蚀刻液使用氟化氢、氯化氢或其他类似化学品或其组合。
如图4M所示，使用选择性磊晶技术，例如有机金属化学气相沉积，将第一纳米线区域12当作成核位置，沉积出第二纳米线通道区14。再一实施例中，第二纳米线14包含砷化铟晶体(一种III-V族化合物半导体)。
如图4N所示，接着使用原子层沉积(ALD)或化学气相沉积(CVD)形成一光学虚拟栅极介电层50。虚拟栅极介电层可以是二氧化硅、氮化硅、二氧化铪、二氧化锆、三氧化二铝或类似材料或其组合。此虚拟栅极介电层厚度介于1～10nm。如图4O所示，再沉积栅极金属24。栅极金属24可以是多晶硅、氮化钛、氮化钽、钨、铝、类似材料或其组合。栅极金属24的厚度被蚀刻到如图4P所示，过程使用蚀刻或蚀刻搭配化学机械研磨。蚀刻步骤可以是反应式离子蚀刻，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气或其他已知蚀刻气体或其组合；或使用湿式蚀刻，其中蚀刻液使用氟化氢、氯化氢、四甲基氢氧化铵或其他类似化学品或其组合。接着使用标准微影蚀刻技术将栅极金属24形成如图4Q所示的图案。如图4R所示，再使用标准沉积和化学机械研磨技术形成一介电层52。介电层52可以是二氧化硅或氮化硅或类似材料或其组合。
如图4S所示，接着使用标准微影蚀刻技术形成一栅极接点孔洞54，再延伸孔洞深度如图4T所示。在此使用一种含两个步骤的制程，其中使用高控制性的蚀刻来形成图4T所示的孔洞，再使用可蚀刻栅极金属层22和24的更具侵蚀性的蚀刻。此蚀刻制程可以使用反应式离子蚀刻或干式蚀刻，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气、氩或其他已知蚀刻气体或其组合。
如图4U所示，使用标准选择性沉积技术来沉积一栅极金属接点层56。这栅极接点层提供导电性接点至栅极层22和24。栅极接点层56可以是氮化钛、氮化钽、钨、铝或类似材料或其组合。使用标准蚀刻制程将虚拟栅极材料50从纳米线通道上部的顶端移除。此蚀刻制程可以是反应式离子蚀刻或干式蚀刻，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气或其他已知蚀刻气体或其组合；或使用湿式蚀刻，蚀刻液使用氟化氢、氯化氢或其他类似化学品或其组合。
如图4V所示，沉积金属接点58并使用标准微影蚀刻技术图案化，这提供接点至栅极(输入)、上部晶体管30的源极(Vss)、输出接点到漏极接点金属44以及接点到基板。如图1所示，通过控制锗纳米线12的掺杂浓度和纳米线14中相对应的铟和砷的浓度，n型通道晶体管30及p型通道晶体管20形成一反相器。使用不同的掺杂物和/或相对浓度，晶体管30可以是p型通道，以及晶体管20可以n型通道。
在一替代性实施例中，从如图4S所示的结构开始，使用蚀刻制程移除栅极层24以及部分栅极层50，该部分栅极层50位于栅极层24和纳米线14中间。该蚀刻制程可以使用反应式离子蚀刻，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气或其他已知蚀刻气体或其组合；或使用湿式蚀刻，蚀刻液使用氟化氢、氯化氢、四甲基氢氧化铵或其他类似化学品或其组合。如图5A所示，使用一原子层沉积(ALD)技术形成一取代栅极介电层60。栅极介电层可以是二氧化硅、二氧化铪、三氧化二铝、二氧化锆或类似材料或其组合，以及该栅极介电层厚度介于1～10nm。栅极介电层60包含一高介电系数介电材料。
如图5B所示，接着蚀刻开口54，将其延伸至栅极层22。该蚀刻制程可以使用反应式离子蚀刻或干式蚀刻，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气、氩或其他已知蚀刻气体或其组合。如图5C所示，使用如选择性化学气相沉积填满开口54，以提供接点70并重新形成栅极层24。如图5D所示，利用蚀刻移除位于纳米线14上的部分虚拟栅极层50。该蚀刻制程可以使用反应式离子蚀刻，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气或其他已知蚀刻气体或其组合；或使用湿式蚀刻，蚀刻液使用氟化氢、氯化氢、四甲基氢氧化铵或其他类似化学品或其组合。
如图5E所示，沉积金属接点58并使用标准微影蚀刻技术图案化，提供接点至栅极(输入)、上部晶体管30的源极(Vss)、输出接点到漏极接点金属44以及接点至基板。如图1所示，通过控制锗纳米线12的掺杂浓度和纳米线14中相对应的铟和砷的浓度，n型通道晶体管30及p型通道晶体管20形成一反相器。使用不同的掺杂物和/或相对浓度，晶体管30可以是p型通道，以及晶体管20可以n型通道。
图6A至图6W绘示本发明另一实施例。在图6A中，形成一介电层142并图案化于硅晶体基板110上。基板110可以是硅、砷化镓、磷化铟、砷化铟或类似材料或任何其组合，其基板任意掺杂n型或p型(浓度为1x1016to 5x1020cm-3)或半绝缘或任何其掺杂物组合。介电层可以是二氧化硅或氮化硅或类似材料或其组合。
如图6B所示，使用一磊晶技术例如MOCVD形成一纳米线层112。纳米线112可能包含锗晶体。如图6C所示，一虚拟栅极层116形成于纳米线112和介电层142上，再形成一牺牲栅极层122于该虚拟栅极层116上。如图6D所示，使用蚀刻或蚀刻加上CMP将牺牲栅极层122回蚀。牺牲栅极层可能包含非晶硅、多晶硅、二氧化硅、氮化硅或类似材料或其组合。该蚀刻制程可以是反应式离子蚀刻，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气或其他已知蚀刻气体或其组合；或使用湿式蚀刻，其中蚀刻液使用氟化氢、氯化氢、四甲基氢氧化铵或其他类似化学品或其组合。如图6E所示，用标准光学微影技术在牺牲栅极层122上图案化。
如图6F所示，使用标准沉积技术沉积一介电层143，再用CMP往下磨平。介电层143可以是二氧化硅、氮化硅或类似材料或其组合。如图6G所示，接着使用标准微影蚀刻技术形成一开口145使牺牲栅极层122外露。使用蚀刻制程移除牺牲栅极层122以及邻近该牺牲栅极层122的部分虚拟栅极层116，形成一开口118。该道蚀刻制程可以使用如反应式离子蚀刻技术，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气或其他已知蚀刻气体或其组合；或湿式蚀刻，使用氟化氢、氯化氢、四甲基氢氧化铵或其他类似化学品或其组合。最后形成的结构如图6H所示。
如图6I所示，使用ALD形成一栅极介电层117于开口118的表面上。栅极介电层117可包含二氧化硅、二氧化铪、三氧化二铝、二氧化锆或类似材料或其组合，其厚度介于1～10nm。如图6J所示，使用标准共形沉积技术将开口118填满，形成栅极120。栅极120金属可为氮化钛、氮化钽、钨、铝或类似材料或其组合。
如图6K所示，使用标准微影技术沉积一介电层145并图案化。形成介电层145的步骤可包含沉积后再CMP，或可包含沉积后使用CMP并再次沉积。介电层145可包含二氧化硅或氮化硅或类似材料或其组合。如图6L所示，沉积一共用接点层144，使用标准微影蚀刻技术，其中可能包含CMP技术在该接触层图案化，形成一共用漏极接点144。该共用漏极接点144可能包含氮化钛、氮化钽、钨、铝或类似材料或其组合。如图6M所示，再沉积一介电层147。形成该介电层147的步骤可包含沉积后再CMP，或可包含沉积后使用CMP并再次沉积。介电层147可包含二氧化硅或氮化硅或类似材料或其组合。
如图6N所示，使用蚀刻图案化形成一开口146，穿过介电层147和共用接点层144。如同形成开口146的部分步骤，从纳米线112的顶端和部分边缘移除虚拟栅极层116。该蚀刻制程可包含反应式离子蚀刻或干式蚀刻，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气、氩或其他已知蚀刻气体或其组合。
如图6O所示，使用如MOVCD技术形成一纳米线114。在一实施例中，第二纳米线114包含一三五族晶体结构的砷化铟。如图6P所示，接着使用ALD或CVD形成一虚拟栅极介电层150，该虚拟栅极介电层可为二氧化硅、氮化硅、二氧化铪、二氧化锆、三氧化二铝或类似材料或其组合。该虚拟栅极介电层的厚度介于1～10nm。如图6P所示，再沉积一虚拟栅极层152。该虚拟栅极层152可以是非晶硅、多晶硅或其他类似材料。再使用蚀刻或蚀刻加上CMP将虚拟层152回蚀到如图6Q所示的厚度。该蚀刻步骤可以是反应式离子蚀刻，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气、其他已知蚀刻气体或其组合；或湿式蚀刻，使用氟化氢、氯化氢、四甲基氢氧化铵或其他类似化学品或其组合。使用标准微影蚀刻技术于虚拟栅极层152形成图案，以提供如图6R所示的结构。
如图6S所示，介电层154使用标准沉积技术沉积以及使用CMP技术平坦化。介电层154可以是二氧化硅或氮化硅或类似材料或其组合。接着，如图6T所示，使用标准微影蚀刻技术形成一开口156。再移除虚拟栅极152，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气或其他已知蚀刻气体或其组合；或使用湿式蚀刻，蚀刻液使用氟化氢、氯化氢、四甲基氢氧化铵或其他类似化学品或其组合。所以部分虚拟栅极介电层150会外露，该外露部分会一起在这道制程里被移除。再使用ALD技术沉积栅极介电层158，以提供如图6U所示的结构。栅极介电层158可以是二氧化硅、二氧化铪、三氧化二铝、二氧化锆或类似材料或其组合，该栅极介电层158厚度可为1～10nm。如图6U所示，蚀刻至栅极120上部外露形成开口156，该开口156垂直延伸穿过栅极介电层158、介电层147和介电层145。该蚀刻制程可以是反应式离子蚀刻或干式蚀刻，其中蚀刻气体使用六氟化硫、四氯化硅、八氟环丁烷、甲烷、氢气、氩或其他已知蚀刻气体或其组合。
接着，使用标准选择性CVD制程填满开口156形成一栅极124，该开口区域是虚拟栅极152被移除时空出来的。栅极124可能包含氮化钛、氮化钽、钨、铝或类似材料或其组合。最后的结构如图6V所示。再使用标准蚀刻技术移除虚拟栅极层150上部。再使用标准技术沉积接点160和162并图案化，以提供如图6W所示最后的结构。未显示的接点也会提供接点至共用接点144和基板110(Vdd)。
依据本发明其中一实施例，提供一种互补式晶体管结构。一柱体下部包含一半导电材料，例如锗，形成于一基板上，该基板包含另一种半导体材料，例如硅。一第一栅极环绕柱体下部并与其绝缘。一柱体上部包含另一种半导电性材料，例如砷化铟。一第二栅极环绕柱体上部并与其绝缘。一电性接点连接柱体上部，该接点在第二栅极上；一第二电性接点连接上部和下部柱体，该接点在第一和第二栅极中间。
依据本发明另一实施例，提供形成互补式晶体管的方法。一第二半导体材料在一半导电性基板上形成柱体下部，该半导电性基板包含一第一半导体材料。该第一半导电材料可以使用一选择性化学气相沉积制程形成。形成一第一栅极环绕柱体下部并与其绝缘。形成一柱体上部，其包含一第三半导电材料。第三半导电材料使用一选择性化学气相沉积制程形成，以第一半导体材料为成核位置。形成一第二栅极环绕柱体上部并与其绝缘。再形成第一电性接点连接柱体上部，其中该第一电性接点在第二栅极上；以及形成第二电性接点连接柱体上部和下部，其中该第二电性接点在第一栅极和第二栅极中间。
本发明的实施例的优点是提供互补式晶体管，其中该晶体管使用一最小的集成电路表面积。
尽管本发明使用图文参照来详述实施例，但这些叙述不应解释为限制意义。对于熟习此技艺的人可以透过参考本说明，明确地了解各种绘示实施例的改良和结合，以及了解本发明中其他的实施例。因此要附加说明专利范围包含任何改良或实施例。

Claims (10)

1.一种互补式金氧半场效晶体管结构，其特征在于，包含：
一柱体下部包含一第二半导电材料，该柱体下部形成于一基板上，其中该基板包含第一半导电材料；
一第一栅极环绕及绝缘于该柱体下部；
一柱体上部包含一第三半导电材料；
一第二栅极环绕及绝缘于该柱体上部；
一第一电性接点与该柱体上部连接，其中该第一电性接点位于该第二栅极上；
以及一第二电性接点与该柱体上部及该柱体下部连接，其中该第二电性接点在该第一栅极与该第二栅极的中间。
2.根据权利要求1所述的互补式金氧半场效晶体管结构，其特征在于，该柱体下部使用选择性沉积形成。
3.根据权利要求1所述的互补式金氧半场效晶体管结构，其特征在于，该柱体上部使用选择性沉积形成。
4.一种互补式金氧半场效晶体管结构，其特征在于，包含：
一柱体下部包含锗晶体，该柱体下部形成于硅基板上；
一第一栅极环绕并绝缘于该柱体下部；
一柱体上部含砷化铟，该柱体上部形成于该柱体下部上；
一第二栅极环绕并绝缘于该柱体上部；
一第一电性接点与该柱体上部连接，其中该第一电性接点位于该第二栅极上；
以及一第二电性接点与该柱体上部及该柱体下部连接，其中该第二电性接点在该第一栅极与该第二栅极的中间。
5.根据权利要求4所述的互补式金氧半场效晶体管结构，其特征在于，该柱体下部提供p型场效晶体管一通道区，以及该柱体上部提供n型场效晶体管一通道区。
6.根据权利要求4所述的互补式金氧半场效晶体管结构，其特征在于，该柱体下部提供n型场效晶体管一通道区，以及该柱体上部提供p型场效晶体管一通道区。
7.根据权利要求4所述的互补式金氧半场效晶体管结构，其特征在于，该第一栅极通过高介电系数介电层与该柱体下部绝缘。
8.根据权利要求4所述的互补式金氧半场效晶体管结构，其特征在于，该第二栅极通过高介电系数介电层与该柱体上部绝缘。
9.一种制作互补式金氧半场效晶体管的方法，其特征在于，包含：
一柱体下部包含一第二半导电材料，该柱体下部形成于一基板上，其中该基板包含一第一半导电材料；
一第一栅极环绕并绝缘于该柱体下部；
一柱体上部，其中包含一第三半导电材料；
一第二栅极环绕并绝缘于该柱体上部；
一第一电性接点与该柱体上部相连，其中该第一电性接点在该第二栅极上；
以及一第二电性接点与该柱体上部及该柱体下部连接，其中该第二电性接点在该第一栅极和该第二栅极中间。
10.根据权利要求9所述的制作互补式金氧半场效晶体管的方法，其特征在于，该柱体上部使用选择性化学气相沉积形成。
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