CN105895590B - 晶片尺寸等级的感测晶片封装模组及其制造方法 - Google Patents

晶片尺寸等级的感测晶片封装模组及其制造方法 Download PDF

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CN105895590B
CN105895590B CN201510993044.3A CN201510993044A CN105895590B CN 105895590 B CN105895590 B CN 105895590B CN 201510993044 A CN201510993044 A CN 201510993044A CN 105895590 B CN105895590 B CN 105895590B
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wafer
sensing
sensing wafer
size grade
touch panel
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CN105895590A (zh
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张恕铭
刘沧宇
何彦仕
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XinTec Inc
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XinTec Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
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Abstract

一种晶片尺寸等级的感测晶片封装模组及其制造方法，该模组包括感测晶片封装体及电路板，该封装体包括感测晶片、具有着色层的触板及粘着层。感测晶片具有上表面与下表面，且邻近上表面处包括感测元件及导电垫，邻近下表面处包括导电结构，导电结构通过重布线层电性连接导电垫。触板包括基部及间隔部，间隔部具有包括底墙及侧墙的凹穴。粘着层位于感测晶片与触板之间，感测晶片通过上表面粘贴到凹穴的底墙，且被凹穴的侧墙环绕。电路板设置于感测晶片封装体下方，且感测晶片封装体通过导电结构电性结合至电路板。本发明使薄触板精确地放置在感测晶片上，且使得触板与感测晶片之间的粘着胶厚度降低，从而可改用具中、低介质电容系数的材料。

Description

晶片尺寸等级的感测晶片封装模组及其制造方法
技术领域
本发明关于一种感测晶片封装模组及其制造方法，且特别有关于一种晶片尺寸等级的感测晶片封装模组及其制造方法。
背景技术
具有感测功能的晶片封装体的感测装置在传统的制作过程中容易受到污染或破坏，造成感测装置的效能降低，进而降低晶片封装体的可靠度或品质。此外，为符合电子产品朝向微型化的发展趋势，有关电子产品封装构造中，用以承载半导体晶片的封装基板如何降低厚度，亦为电子产品研发中一项重要的课题。有关封装基板的制作过程中，其于薄形晶片层上制作线路。若封装基板为符合微型化的要求，而选用厚度过薄的封装基板时，不但封装基板的生产作业性不佳，封装基板也易因厚度过薄，而于封装制程受到环境因素影响会产生变形翘曲或损坏，造成产品不良等问题。
此外，触控面板或具感测功能(例如生物特征辨识)的面板是目前流行的科技趋势，但在使用者长期频繁地按压面板的情况下，将使位在面板底下的触控元件故障失效。故，具有硬度9以上的材料，例如蓝宝石基板，乃脱颖而出被选作触控面板表面的触板，通过其仅耐刮的优点，保护面板底下的半导体元件。不过，目前市面上用以保护触控元件或生物特征感测元件的蓝宝石基板，其厚度均大于200μm，由于电容式触控面板或具生物特征辨识感测功能的面板均通过触板的电容变化来传递信号，且众所周知平形板电容器的电容方程式如下：
C＝ε*A/d
C：平形板电容器电容
ε：介质电容系数
A：平形板重叠的面积
d：两平形板间的距离
如上述平形板电容器电容方程式所示，在介质电容系数与平形板重叠的面积不变的情况下，电容的大小与两平形板间的距离成反比，故当平形板的厚度越大时，意味两平形板间的距离越大，导致电容变小。
发明内容
有鉴于此，为了改善如上所述的缺点，增加电容式触控面板或具感测功能的面板的灵敏度，本发明提出一种新的晶片尺寸等级的(chip scale)感测晶片封装模组以及其制造方法，通过使用硬度大于7的材料作为触板，且降低其厚度，使得电容式触控面板或具感测功能的面板的电容值可以提高，增加其灵敏度。
此外，本发明乃通过晶圆级封装制程达成，不仅可以使本发明的薄触板可以精确地放置在感测晶片上，且在搭配旋涂制程情况下，使得触板晶圆与具感测元件的晶圆之间的粘着胶厚度降低，故可以不需要再选择提高电容值所需要的高介质系数材料，而改用具中、低介质电容系数的材料即可，不仅降低生产成本，也进而可提供一效率更高的晶片等级的感测晶片封装模组。此外，由于触板是在感测晶片的半导体制程中同时结合，因此同时具有晶片尺寸等级，可避免现有技术中感测晶片与触板不匹配的问题。
本发明的一目的是提供一种晶片尺寸等级的感测晶片封装模组，包括：一感测晶片，具有相对的一第一上表面与一第一下表面，且邻近该第一上表面处包括有一感测元件以及多个导电垫，而邻近该第一下表面处则包括有一导电结构，且该导电结构通过一重布线层与所述导电垫电性连接；一具有着色层的触板，包括一基部及一位在该基部表面的间隔部，该间隔部具有一凹穴，且该凹穴具有一裸露出部分该基部的底墙及环绕该底墙的侧墙；及一第一粘着层，位于该感测晶片与触板之间，使得该感测晶片通过该第一上表面粘贴到该凹穴的该底墙，且该感测晶片被该凹穴的该侧墙所环绕；以及；一电路板，设置于该晶片尺寸等级的感测晶片封装体下方，且该晶片尺寸等级的感测晶片封装体通过该导电结构电性结合至该电路板上。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组，其中该触板的尺寸大于该感测晶片的尺寸。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组，其中该凹穴的俯视轮廓为矩形，而该触板的俯视轮廓为圆形。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组，其中该间隔部的厚度为该基部的厚度的十倍以上。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组，其中该着色层是涂布于该凹穴的该底墙及该侧墙。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组，其中构成该基部与该间隔部的材料包括玻璃。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组，其中该基部包括一触板、一着色层及一夹于该触板与该着色层间的第二粘着层，且该间隔部是形成于该着色层上。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组，其中构成该基部的该触板的材料包括玻璃，而构成该间隔部的材料包括玻璃或硅。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组，其中构成该第一粘着层的材料包括中、低电容系数的介质材料。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组，其中该导电结构包括焊球及/或焊接凸块及/或导电柱。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组，其中该感测元件包括触控元件、生物特征辨识元件或环境因子感测元件。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组，其中该生物特征辨识元件包括指纹辨识元件。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组，还包括一缓冲装置，设置于该电路板的背面。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组，其中该缓冲装置包括一弹簧或一弹力钮。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组，且还包括一触发元件，设置于该晶片尺寸等级的感测晶片封装体的该凹穴内，且该触发元件与该晶片尺寸等级的感测晶片电性连接。
本发明的另一目的是提供一种晶片尺寸等级的感测晶片封装模组的制造方法，其步骤包括：提供多个晶片尺寸等级的感测晶片，每一所述晶片尺寸等级的感测晶片均具有相对的一第一上表面与一第一下表面，且邻近该第一上表面处包括有一感测元件以及多个导电垫，而邻近该第一下表面处则包括有一导电结构，且该导电结构通过一重布线层与所述导电垫电性连接；提供一具有一着色层的触板晶圆，该触板晶圆包括有多个固晶区，且每一所述固晶区外均具有一预定的切割道，其中每一所述固晶区包括一基部及一位在该基部上的间隔部，该间隔部具有一凹穴，且该凹穴具有一裸露出部分该基部的底墙及环绕该底墙的侧墙；提供一第一粘着层，使得每一所述感测晶片通过该第一上表面分别粘贴到各该凹穴的该底墙，且每一所述感测晶片均被该凹穴的该侧墙所环绕沿所述固晶区之间的切割道，进行一切割程序以获得多个晶片尺寸等级的感测晶片封装体，其中每一所述晶片尺寸等级的感测晶片封装体，包括：一所述感测晶片；一具有着色层的触板，包括一基部及一位在该基部上的间隔部，该间隔部具有一凹穴，且该凹穴具有一裸露出部分该基部的底墙及环绕该底墙的侧墙；及一第一粘着层，位于该感测晶片与触板之间，使得该感测晶片通过该第一上表面粘贴到该凹穴的该底墙，且该感测晶片被该凹穴的该侧墙所环绕；以及提供一电路板，使其中一所述晶片尺寸等级的感测晶片封装体通过所述导电结构电性结合至该电路板上。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组的制造方法，其中该触板的尺寸大于该感测晶片的尺寸。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组的制造方法，其中该凹穴的俯视轮廓为矩形，而该基部的俯视轮廓为圆形。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组的制造方法，其中该间隔部的厚度为该基部的厚度的十倍以上。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组的制造方法，其中该着色层是涂布于该凹穴的底墙及侧墙。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组的制造方法，其中构成该基部与该间隔部的材料包括玻璃。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组的制造方法，其中该具有一着色层的触板晶圆的制造步骤包括：提供一触板晶圆，触板晶圆具有相对的正面及反面；涂布一着色层于该触板晶圆的正面上；涂布一第二粘着层于该着色层上；使一触板结合至该第二粘着层上；薄化该触板晶圆的反面；以及图案化该薄化的触板晶圆的反面，形成多个彼此互相间隔的固晶区，且每一所述固晶区包括一基部及一位在基部上的间隔部，其中该基部包括一触板、一着色层及一夹于该触板与该着色层间的第二粘着层，该间隔部是形成于该着色层上，且该间隔部具有一裸露出该着色层表面的凹穴。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组的制造方法，其中构成该基部的该触板的材料包括玻璃，而构成该间隔部的材料包括玻璃或硅。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组的制造方法，其中该第一粘着层的材料包括中、低电容系数的介质材料。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组的制造方法，其中该导电结构包括焊球及/或焊接凸块及/或导电柱。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组的制造方法，其中该感测元件包括触控元件、生物特征辨识元件或环境因子感测元件。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组的制造方法，其中该生物特征辨识元件包括指纹辨识元件。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组的制造方法，还包括一缓冲装置，设置于该电路板的背面。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组的制造方法，其中该缓冲装置包括一弹簧或一弹力钮(spring button)。
本发明的另一目的是提供一种如上所述的晶片尺寸等级的感测晶片封装模组的制造方法，还包括一触发元件，设置于该晶片尺寸等级的感测晶片封装体的该凹穴内，且该触发元件与该晶片尺寸等级的感测晶片电性连接。
附图说明
图1A～图1E及图1C’～图1E’显示根据本发明实施例一的晶片尺寸等级的感测晶片封装模组的剖面制程。
图2A～图2C及图2B’～图2C’的显示根据本发明实施例二的晶片尺寸等级的感测晶片封装模组的剖面制程。
图3A～图3D的显示根据本发明实施例二的图2A的固晶区剖面制程。
其中，附图中符号的简单说明如下：
10、10’ 晶片尺寸等级的感测晶片
100 基板
100a 第一上表面
100b 第一下表面
115 导电垫
150 感测元件
210 绝缘层
220 重布线层(RDL)
230 钝化保护层
240 孔洞
245 铸胶层
250 导电结构
250A 导电柱
250B 焊球
30 固晶区
300 触板晶圆
300’ 触板
310 基部
320 间隔部
330 凹穴
330a 底墙
330b 侧墙
350 着色层
400 第一粘着层
445 导电接触垫
450 电路板
460 缓冲装置
50 固晶区
500、500’ 触板晶圆
510 基部
520 着色层
530 第二粘着层
540 触板
545 间隔层
550 凹穴
SC 切割道
A、A’、B、B’ 晶片尺寸等级的感测晶片封装体
1000、1000’、2000、2000’ 晶片尺寸等级的感测晶片封装模组。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。
<实施例一>
以下将配合图1A～图1E及图1C’～图1E’，说明根据本发明的实施例一的晶片尺寸等级的感测晶片封装模组以及其制造方法。
请先参照图1A，先提供一触板晶圆300，其表面包括多个固晶区30，且在各固晶区30***有一预定的圆形切割道SC。在本实施例中，触板晶圆300可选自透明且硬度大于7的材料，例如玻璃。
接着，请参照图1B，其显示的是沿图1A的剖面线I-I’所呈现的固晶区30的剖面图。如图1B所示，固晶区30包括一基部310以及一个位在基部上的间隔部320，该间隔部320具有一露出基部310表面的凹穴330，其具有一底墙330a，以及环绕该底墙的侧墙330b。在本实施例中，凹穴330可通过微影蚀刻、铣削(milling)或铸模等技术达成。其中，间隔部320的厚度为基部310的厚度的十倍以上，在本实施例之间隔部320的厚度约为500μm，而基部310的厚度约为50μm。此外，还包括一着色层350，覆盖于各固晶区30的间隔层30表面及凹穴330的底墙330a及侧墙330b。
其次，请参照图1C及图1C’，提供多个如图1C所示的晶片尺寸等级的感测晶片10，或多个如图1C’所示的晶片尺寸等级的感测晶片10’。其中，每一个晶片尺寸等级的感测晶片10、10’均包括一基板100，其具有相对的一第一上表面100a与一第一下表面100b，且邻近该第一上表面100a处包括有一感测元件150以及多个导电垫115，而邻近该第一下表面100b处则包括有一介电层210、重布线层(RDL)220、钝化保护层230以及导电结构250。其中，导电结构250乃通过一重布线层(RDL)220与导电垫115电性连接。其中，图1C所示的晶片尺寸等级的感测晶片10，其导电结构250在本实施例为焊球，在根据本发明的其他实施例，其导电结构250也可为焊接凸块或导电柱。此外，图1C’所示的晶片尺寸等级的感测晶片10’，其导电结构250由导电柱250A和焊球250B所构成，且导电柱250A沟填于一个贯穿钝化保护层230及钝化保护层230表面的铸胶层245且裸露出部分重布线层220的贯穿孔内，而焊球250B则位在铸胶层245表面且与导电柱250A连接。其中，铸胶层的厚度约100μm，且其材料可选自例如环氧树脂等。
接着，请参照图1D及图1D’，在图1C所示的晶片尺寸等级的感测晶片10的第一上表面100a上或图1C’所示的晶片尺寸等级的感测晶片10’的第一上表面100a上涂布一第一粘着层400，或者在凹穴300的底墙330a涂布一第一粘着层400，使得晶片尺寸等级的感测晶片10或10’分别被粘贴固定于如图1B所示各固晶区30内的凹穴330的底墙330a表面的着色层350上。此外，其他可触发感测晶片10、10’启动的电子元件，例如触发元件(未显示)，也可通过第一粘着层400被固定于各固晶区30内的凹穴330的底墙330a表面的着色层350上，并与感测晶片10、10’电性连接。
然后，沿着各固晶区30外的切割道SC，切割触板晶圆300，进而形成多个独立的晶片尺寸等级的感测晶片封装体A、A’。其中，每一晶片尺寸等级的感测晶片封装体A、A’分别包括一俯视轮廓为矩形的晶片尺寸等级的感测晶片10、10’，其表面具有一感测元件150以及多个环绕感测元件150的导电垫115，以及一个由基部310和间隔部320所形成的触板300’，其俯视轮廓为圆形，且触板300’的尺寸大于晶片尺寸等级的感测晶片10、10’。
最后，请参照图1E及图1E’，提供一表面具有多个导电接触垫445的电路板450，使得上述制程所获得的晶片尺寸等级的感测晶片封装体A、A’可分别通过其导电结构250与电路板450上的导电接触垫445电性结合，并分别形成一晶片尺寸等级的感测晶片封装体模组1000、1000’。此外，还可在电路板450的背面装配一缓冲装置460，例如弹簧、或弹力钮，使得触板300’被使用者按压时，提供晶片尺寸等级的感测晶片封装体A、A’与电路板450间一缓冲力，避免晶片尺寸等级的感测晶片封装体A、A’与电路板450间的接合处被按压的力量所破坏。
<实施例二>
以下将配合图2A至图2C及图2B’至图2C’，说明根据本发明的实施例二的晶片尺寸等级的感测晶片封装模组以及其制造方法。
请参照图2A，其所显示的是一固晶区50的剖面示意图。如图2A所示，固晶区50包括一基部510以及一位在该基部510上且环绕该基部510周围的间隔部545，其中间隔部545还包括一裸露出基部510表面的凹穴550。此外，本实施例的基部510包括一触板540、一着色层520及一夹于该触板540与该着色层520间的第二粘着层530，且该间隔部545形成于着色层520上。
接着，请参照图2B及图2B’，通过第一粘着层400，使如图1C或图1C’所示的晶片尺寸等级的感测晶片10或10’被固定于图2A所示的固晶区50的凹穴550底部所裸露的着色层520上。然后，沿着各固晶区50外的切割道SC切割触板晶圆500’，进而获得如图2B及图2B’所示的多个独立的晶片尺寸等级的感测晶片封装体B、B’。
然后，请参照图2C及图2C’，提供一如图1E所示的电路板450，使得上述制程所获得的晶片尺寸等级的感测晶片封装体B、B’，可分别通过其导电结构250与电路板450上的导电接触垫445电性结合，并分别形成一晶片尺寸等级的感测晶片封装体模组2000、2000’。
此外，其他可触发感测晶片10、10’启动的电子元件，例如触发元件(未显示)，也可固定于各固晶区50内的凹穴550底部的着色层520上，并与感测晶片10、10’电性连接。
上述的固晶区50，其制程乃描述于图3A～图3D。如图3A所示，先提供一触板晶圆500，其材质可选自硅或玻璃。其次如图3B所示般，在触板晶圆500正面依序形成一着色层520、一第二粘着层以及一触板540于触板晶圆500上。其中，在本实施例中，触板晶圆500的材料可选自透明玻璃或硅晶圆，而触板540则可选自透明且硬度大于7的材料，例如玻璃、蓝宝石或氮化硅。
然后，利用蚀刻制程、铣削(milling)制程、磨削(grinding)制程或研磨(polishing)制程，薄化触板晶圆500的背面，形成如图3C所示般的较薄的触板晶圆500’。
最后，请参照图3D，利用蚀刻、铣削等技术，自触板晶圆500’的背面进行图案化，形成多个彼此互相间隔的固晶区50，且每一个固晶区50包括一基部510及一位在基部上的间隔部545，其中该基部510包括一触板540、一着色层520及一夹于该触板540与该着色层520间的第二粘着层530，且该间隔部545形成于着色层520上，且该间隔部545具有一裸露出该着色层520表面的凹穴550。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (30)

1.一种晶片尺寸等级的感测晶片封装模组，其特征在于，包括：
一晶片尺寸等级的感测晶片封装体，包括：
一感测晶片，具有相对的一第一上表面与一第一下表面，且邻近该第一上表面处包括有一感测元件以及多个导电垫，而邻近该第一下表面处则包括有一导电结构，且该导电结构通过一重布线层与所述导电垫电性连接；
一具有着色层的触板，包括一基部及一位在该基部上的间隔部，该间隔部具有一凹穴，且该凹穴具有一裸露出部分该基部的底墙及环绕该底墙的侧墙；及
一第一粘着层，位于该感测晶片与触板之间，使得该感测晶片通过该第一上表面粘贴到该凹穴的该底墙，且该感测晶片被该凹穴的该侧墙所环绕；以及
一电路板，设置于该晶片尺寸等级的感测晶片封装体下方，且该晶片尺寸等级的感测晶片封装体通过该导电结构电性结合至该电路板上。
2.根据权利要求1所述的晶片尺寸等级的感测晶片封装模组，其特征在于，该触板的尺寸大于该感测晶片的尺寸。
3.根据权利要求1所述的晶片尺寸等级的感测晶片封装模组，其特征在于，该凹穴的俯视轮廓为矩形，而该触板的俯视轮廓为圆形。
4.根据权利要求1所述的晶片尺寸等级的感测晶片封装模组，其特征在于，该间隔部的厚度为该基部的厚度的十倍以上。
5.根据权利要求1所述的晶片尺寸等级的感测晶片封装模组，其特征在于，该着色层涂布于该凹穴的该底墙及该侧墙。
6.根据权利要求1所述的晶片尺寸等级的感测晶片封装模组，其特征在于，构成该基部与该间隔部的材料包括玻璃。
7.根据权利要求1所述的晶片尺寸等级的感测晶片封装模组，其特征在于，该基部包括一触板、一着色层及一夹于该触板与该着色层间的第二粘着层，且该间隔部形成于该着色层上。
8.根据权利要求7所述的晶片尺寸等级的感测晶片封装模组，其特征在于，构成该触板的材料包括玻璃，而构成该间隔部的材料包括玻璃或硅。
9.根据权利要求1所述的晶片尺寸等级的感测晶片封装模组，其特征在于，构成该第一粘着层的材料包括中、低电容系数的介质材料。
10.根据权利要求1所述的晶片尺寸等级的感测晶片封装模组，其特征在于，该导电结构包括焊球及/或焊接凸块及/或导电柱。
11.根据权利要求1所述的晶片尺寸等级的感测晶片封装模组，其特征在于，该感测元件包括触控元件、生物特征辨识元件或环境因子感测元件。
12.根据权利要求11所述的晶片尺寸等级的感测晶片封装模组，其特征在于，该生物特征辨识元件包括指纹辨识元件。
13.根据权利要求1所述的晶片尺寸等级的感测晶片封装模组，其特征在于，还包括一缓冲装置，设置于该电路板的背面。
14.根据权利要求13所述的晶片尺寸等级的感测晶片封装模组，其特征在于，该缓冲装置包括一弹簧或一弹力钮。
15.根据权利要求1～14中任一项所述的晶片尺寸等级的感测晶片封装模组，其特征在于，还包括一触发元件，设置于该晶片尺寸等级的感测晶片封装体的该凹穴内，且该触发元件与该晶片尺寸等级的感测晶片电性连接。
16.一种晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，包括：
提供多个晶片尺寸等级的感测晶片，每一所述晶片尺寸等级的感测晶片具有相对的一第一上表面与一第一下表面，且邻近该第一上表面处包括有一感测元件以及多个导电垫，而邻近该第一下表面处则包括有一导电结构，且该导电结构通过一重布线层与所述导电垫电性连接；
提供一具有一着色层的触板晶圆，该触板晶圆包括有多个固晶区，且每一所述固晶区外均具有一预定的切割道，其中每一所述固晶区包括一基部及一位在该基部上的间隔部，该间隔部具有一凹穴，且该凹穴具有一裸露出部分该基部的底墙及环绕该底墙的侧墙；
提供一第一粘着层，使得每一所述感测晶片通过该第一上表面分别粘贴到各该凹穴的该底墙，且每一所述感测晶片均被该凹穴的该侧墙所环绕；
沿该切割道，进行一切割程序以获得多个晶片尺寸等级的感测晶片封装体，其中每一所述晶片尺寸等级的感测晶片封装体包括：
一所述感测晶片；
一具有着色层的触板，包括一基部及一位在该基部上的间隔部，该间隔部具有一凹穴，且该凹穴具有一裸露出部分该基部的底墙及环绕该底墙的侧墙；及
一第一粘着层，位于该感测晶片与触板之间，使得该感测晶片通过该第一上表面粘贴到该凹穴的该底墙，且该感测晶片被该凹穴的该侧墙所环绕；以及
提供一电路板，使其中一所述晶片尺寸等级的感测晶片封装体通过所述导电结构电性结合至该电路板上。
17.根据权利要求16所述的晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，该触板的尺寸大于该感测晶片的尺寸。
18.根据权利要求16所述的晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，各该固晶区内的该凹穴的俯视轮廓为矩形，而该基部的俯视轮廓为圆形。
19.根据权利要求16所述的晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，该间隔部的厚度为该基部的厚度的十倍以上。
20.根据权利要求16所述的晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，该着色层涂布于该凹穴的该底墙及该侧墙。
21.根据权利要求16所述的晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，构成该基部与该间隔部的材料包括玻璃。
22.根据权利要求16所述的晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，制造该具有一着色层的触板晶圆的步骤包括：
提供一触板晶圆，该触板晶圆具有相对的正面及反面；
涂布一着色层于该触板晶圆的正面上；
涂布一第二粘着层于该着色层上；
使一触板结合至该第二粘着层上；
薄化该触板晶圆的反面；以及
图案化该薄化的触板晶圆的反面，形成多个彼此互相间隔的固晶区，且每一所述固晶区包括一基部及一位在基部上的间隔部，其中该基部包括一触板、一着色层及一夹于该触板与该着色层间的第二粘着层，该间隔部形成于该着色层上，且该间隔部具有一裸露出该着色层表面的凹穴。
23.根据权利要求22所述的晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，构成该触板的材料包括玻璃，而构成该间隔部的材料包括玻璃或硅。
24.根据权利要求16所述的晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，构成该第一粘着层的材料包括中、低电容系数的介质材料。
25.根据权利要求16所述的晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，该导电结构包括焊球及/或焊接凸块及/或导电柱。
26.根据权利要求16所述的晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，该感测元件包括触控元件、生物特征辨识元件或环境因子感测元件。
27.根据权利要求26所述的晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，该生物特征辨识元件包括指纹辨识元件。
28.根据权利要求16所述的晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，还包括一缓冲装置，设置于该电路板的背面。
29.根据权利要求28所述的晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，该缓冲装置包括一弹簧或一弹力钮。
30.根据权利要求16～29中任一项所述的晶片尺寸等级的感测晶片封装模组的制造方法，其特征在于，还包括一触发元件，设置于该晶片尺寸等级的感测晶片封装体的该凹穴内，且该触发元件与该晶片尺寸等级的感测晶片电性连接。
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