CN105684156B - 齐纳二极管 - Google Patents
齐纳二极管 Download PDFInfo
- Publication number
- CN105684156B CN105684156B CN201480058416.7A CN201480058416A CN105684156B CN 105684156 B CN105684156 B CN 105684156B CN 201480058416 A CN201480058416 A CN 201480058416A CN 105684156 B CN105684156 B CN 105684156B
- Authority
- CN
- China
- Prior art keywords
- region
- zener diode
- current path
- drift region
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000012535 impurity Substances 0.000 claims abstract description 47
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000015556 catabolic process Effects 0.000 claims description 39
- 238000009826 distribution Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000011031 large-scale manufacturing process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
齐纳二极管(10)包括:半导体基板(12)、阳极电极(40)和阴极电极(42)。半导体基板(12)包括p型阳极区(20)、n型电流路径区(22)和漂移区(24)。p型阳极区(20)连接到所述阳极电极(40)。n型电流路径区(22)与所述阳极区(20)接触。漂移区(24)与所述阳极区(20)和所述电流路径区(22)接触。漂移区(24)是n型的。漂移区(24)具有比所述电流路径区(22)低的n型杂质浓度。漂移区(24)直接地或经由另一个n型区(26)连接到所述阴极电极(42)。
Description
发明领域
本发明涉及齐纳二极管。
背景技术
日本专利申请公开第7-321347号(JP 7-321347 A)描述了齐纳二极管。构成齐纳二极管的pn结的n区的n型杂质浓度低,在齐纳二极管击穿时主要发生雪崩击穿。在这种情况下,雪崩击穿具有正温度系数,所以齐纳二极管的特性根据温度而变化。与此相反,在JP7-321347 A中所述的齐纳二极管中,pn结由高浓度p区和高浓度n区形成。因此,在齐纳二极管击穿时,雪崩击穿和齐纳击穿两者以平衡的方式发生。齐纳击穿具有与雪崩击穿相反的温度系数。因此,通过使雪崩击穿和齐纳击穿两者发生,能够提高齐纳二极管的温度特性。
发明内容
在JP 7-321347 A中所述的齐纳二极管中,构成pn结的n型区的n型杂质浓度高。因此,当反向电压施加到齐纳二极管时,耗尽层难以延伸入n型区。因此,齐纳二极管具有这样的不便:反向击穿电压低。因此,本发明提供了一种具有所希望的温度特性和高的反向击穿电压的齐纳二极管。
本发明的方案提供了齐纳二极管。齐纳二极管包括:半导体基板、阳极电极和阴极电极。所述半导体基板包括p型阳极区、n型电流路径区和漂移区。所述p型阳极区连接到所述阳极电极,所述n型电流路径区与所述阳极区接触。所述漂移区与所述阳极区和所述电流路径区接触。所述漂移区是n型。所述漂移区具有比所述电流路径区低的n型杂质浓度。所述漂移区连接到所述阴极电极。漂移区可以直接地连接到所述阴极电极。可替代地,漂移区可以经由另一个n型区连接到阴极电极。
在该齐纳二极管中,第一pn结形成在阳极区和电流路径区之间,第二pn结形成在阳极区和漂移区之间。当低的反向电压施加到齐纳二极管时,耗尽层从所述第一和第二pn结延伸。此时,由于漂移区的n型杂质浓度低,耗尽层从第二pn结更广泛地延伸入漂移区。因此,高反向电压难以施加到pn结。因此,齐纳二极管具有高的反向击穿电压。
构成第一pn结的电流路径区具有比构成第二pn结的漂移区高的n型杂质浓度。因此,在当反向电压施加到齐纳二极管时,第一pn结的击穿比第二pn结的击穿更容易发生。因此,当施加到所述齐纳二极管的反向电压增大时,发生第一pn结的击穿。由于构成第一pn结的电流路径区的n型杂质浓度高,雪崩击穿和齐纳击穿两者以平衡的方式发生在第一pn结处。因此,齐纳二极管具有所希望的温度特性。
在上述齐纳二极管中,半导体基板可以是SOI基板。所述SOI基板可以包括第一半导体层、绝缘层和第二半导体层。所述绝缘层可以层压在所述第一半导体层上。所述第二半导体层可以层压在所述绝缘层上。在这种情况下,所述阳极区、所述电流路径区和所述漂移区可以形成在所述第二半导体层中。所述第一半导体层可以连接到所述阴极电极。
通过这样的配置,在齐纳二极管关断的状态下,在漂移区中等势线沿第一半导体层延伸。因此,第一pn结的击穿更易发生。
在上述的齐纳二极管中,所述电流路径区可以形成在阳极区的下侧。
通过这样的配置,能够精确地形成电流路径区。因此,在大规模生产中齐纳二极管的特性变得稳定。
在上述齐纳二极管中,所述半导体基板可以包括阴极区和中间浓度区。所述阴极区可以连接到所述阴极电极。所述阴极区可以是n型。所述阴极区可以具有比所述漂移区高的n型杂质浓度。所述中间浓度区可以与所述阴极区和所述漂移区接触。所述中间浓度区可以使所述阴极区与所述漂移区隔离。所述中间浓度区可以是n型。所述中间浓度区可以具有比所述阴极区低的n型杂质浓度。所述中间浓度区可以具有比所述漂移区高的n型杂质浓度。
通过这样的配置,在齐纳二极管关断的状态下,高电场很难在半导体基板中产生。因而,能够进一步增大齐纳二极管的击穿电压。
附图说明
下面将参考附图描述本发明的示例性实施例的特征、优点、以及技术和工业意义,其中相同标记指代相同的元件,并且其中:
图1是根据第一实施例的齐纳二极管的纵剖图。
图2是根据第二实施例的齐纳二极管的纵剖图。
图3是示出了在根据第一实施例的齐纳二极管中的电势分布的图。
图4是根据第二实施例的齐纳二极管中的电势分布图。
图5是根据第三实施例的齐纳二极管的纵剖图。
图6是根据第四实施例的齐纳二极管的纵剖图。
图7是示出了在根据第一实施例的齐纳二极管中的电场分布的曲线图。
图8是示出了在根据第四实施例的齐纳二极管中的电场分布的曲线图。以及
图9是根据第一实施例的变型例的齐纳二极管的纵剖图。
具体实施方式
图1所示的齐纳二极管10包括SOI基板12、阳极电极40和阴极电极42。SOI基板12包括背面层14、绝缘层16和表面层18。背面层14由硅制成。绝缘层16由氧化硅构成。绝缘层16层压在背面层14上。表面层18由硅制成。表面层18层压在绝缘层16上。表面层18通过绝缘层16与背面层14绝缘。阳极电极40和阴极电极42形成在表面层18上。
阳极区20、电流路径区22、漂移区24和阴极区26形成在表面层18中。阳极区20是p型区,并形成在暴露于表面层18的上表面的区中。阳极区20连接到阳极电极40。电流路径区22是n型区,并形成在阳极区20的下侧。电流路径区22与阳极区20接触。漂移区24为具有比电流路径区22低的n型杂质浓度的n型区。漂移区24与阳极区20和电流路径区22接触。阴极区26是具有比电流路径区22和漂移区24高的n型杂质浓度的n型区。阴极区26与漂移区24接触。阴极区26利用漂移区24与阳极区20和电流路径区22隔离。阴极区26连接到阴极电极42。在以下的说明中,由阳极区20和电流路径区22形成的pn结称为pn结50,由阳极区20和漂移区24形成的pn结称为pn结52。如图9所示,漂移区24可以连接到阴极电极42。
N型杂质以基本上恒定的浓度分布在漂移区24中。电流路径区22是通过将n型20杂质注入漂移区24而形成的区。因此,电流路径区22的n型杂质浓度比漂移区24的基本上均匀的n型杂质浓度高。阴极区26是通过将n型杂质注入漂移区24而形成的区。因此,阴极区26的n型杂质浓度比漂移区24的基本上均匀的n型杂质浓度高。也就是说,与阳极区20接触并且具有均匀的n型杂质浓度的区是漂移区24。与阳极区20接触并具有比漂移区24高的n型杂质浓度的区是电流路径区22。具有比漂移区24高的n型杂质浓度并且利用漂移区24与阳极区20和电流路径区22隔离的区是阴极区26。在本实施例中,漂移区24的n型杂质浓度低于1×1015个原子/cm3。电流路径区22的n型杂质浓度高于或等于4×l017个原子/cm3。电流路径区22的n型杂质浓度优选低于6×1017个原子/cm3。阴极区26的n型杂质浓度高于或等于1×1020个原子/cm3。
在齐纳二极管10的使用期间,阴极电极42的电压为正的电压(即,反向电压)可以施加在阳极电极40和阴极电极42之间。当施加反向电压时,耗尽层从pn结50延伸入电流路径区22,并从pn结52延伸入漂移区24。此时,由于漂移区24的n型杂质浓度比电流路径区22的低,耗尽层更广泛地延伸入漂移区24。结果,基本上整个漂移区24耗尽。因为相对高的电压施加到耗尽的漂移区24,电压难以施加到pn结50、52。因此,很难发生pn结50、52的击穿,所以,齐纳二极管10的反向击穿电压高。
电流路径区22具有高的n型杂质浓度,所以pn结50具有高的内建电势。与此相反,漂移区24具有低的n型杂质浓度,所以pn结52具有低的内建电势。因此,pn结50的击穿比pn结52的击穿更容易发生。因此,当上述反向电压进一步增大时,pn结50的击穿在pn结52的之前发生。由此,如由图1中的箭头60指示的,击穿电流从阴极区26经由漂移区24和电流路径区22流向阳极区20。此时,由于电流路径区22具有高的n型杂质浓度,雪崩击穿和齐纳击穿以大致相同的比率发生在pn结50处。雪崩击穿具有正温度系数,而齐纳击穿具有负温度系数,所以这些温度系数彼此抵消。因此,齐纳二极管10具有极好的温度特性。即,即使当温度变化时,齐纳二极管10的特性也不易变化。
如上所述,通过根据第一实施例的配置,能够实现具有高的反向击穿电压和极好的温度特性的齐纳二极管10。
将描述第二实施例。在图2所示的齐纳二极管210中,在阴极区26的下侧的绝缘层16中形成开口220。背面层14经由开口220连接到表面层18。背面层14由具有高浓度n型杂质的n型半导体形成。阴极区26通过开口220到达背面层14。因此,在齐纳二极管210中,背面层14经由阴极区26连接到阴极电极42。齐纳二极管210的其它配置与根据第一实施例的齐纳二极管10的相同。
图3示出在施加具有不发生pn结50、52的击穿的水平的反向电压的情况下,根据第一实施例的齐纳二极管10中的等势线的分布。图4示出在施加与图3相同的反向电压的情况下,根据第二实施例的齐纳二极管210中的等势线的分布。从图3和图4很明显的是,与施加到根据第一实施例的齐纳二极管10中的pn结50的电压相比,更高的电压施加到根据第二实施例的齐纳二极管210中的pn结50。因此,当施加更高的反向电压时,能够进一步可靠地引起pn结50的击穿发生。因此,改善了大规模生产齐纳二极管时的鲁棒性。即,即使当由于制造误差而导致各区的布置的错位,也能够制造pn结50的击穿可靠地发生的齐纳二极管。
将描述第三实施例。在根据图5中所示的第三实施例的齐纳二极管310中,在阴极区26旁形成孔70。孔70延伸通过表面层18和绝缘层16,并到达背面层14。孔70的侧面覆盖有绝缘膜72。导电层74形成在孔70中。导电层74利用绝缘膜72与表面层18的半导体层绝缘。导电层74连接到阴极电极42。背面层14由具有高浓度n型杂质的n型半导体形成。背面层14与导电层74接触。即,背面层14经由导电层74连接到阴极电极42。齐纳二极管310的其它配置与根据第一实施例的齐纳二极管10的相同。
在根据第三实施例的齐纳二极管310中,与根据第二实施例的齐纳二极管210相同,背面层14连接到阴极电极42。因此,同样地,在齐纳二极管310中,容易发生pn结50的击穿。
将描述第四实施例。在根据图6所示的第四实施例的齐纳二极管410中,四个中间浓度区401至404形成在漂移区24和阴极区26之间。中间浓度区401的n型杂质浓度n1、中间浓度区402的n型杂质浓度n2、中间浓度区403的n型杂质浓度n3和中间浓度区404的n型杂质浓度n4中的每个都比阴极区26的n型杂质浓度低,并且比漂移区24的n型杂质浓度高。n型杂质浓度n1到n4满足关系n1>n2>n3>n4。即,中间浓度区401至404之中更靠近阴极区26的区具有更高的n型杂质浓度。在第四实施例中,中间浓度区401至404中的每个的n型杂质浓度低于1×1020个原子/cm3且高于或等于1×1015个原子/cm3。齐纳二极管410的其它配置与根据第一实施例的齐纳二极管10的相同。
在齐纳二极管410中,当施加具有不发生pn结50、52的击穿的水平的反向电压时,基本上整个漂移区24和整个中间浓度区401至404都耗尽。图7示出在根据第一实施例的齐纳二极管10中漂移区24耗尽的情况下,沿着图1中的线VII-VII的电场分布。图8示出在根据第四实施例的齐纳二极管410中漂移区24和中间浓度区401至404都耗尽的情况下,沿着图6中的线VIII-VIII的电场分布。如图7所示,在根据第一实施例的齐纳二极管10中,电场在pn结52处变成峰值。与此相反,在根据第四实施例的齐纳二极管410中,电场基本上均匀地分布在漂移区24和中间浓度区401至404中。这是因为中间浓度区401至404的每个都具有比漂移区24高的n型杂质浓度。另外,由于中间浓度区401至404之中更靠近阴极区26的区具有更高的n-型杂质浓度,电场分布是均匀的。图7和图8中所示的曲线图中的每个的面积(积分值)指的是阳极区20和阴极区26之间的耐受电压。即,随着面积增大,齐纳二极管的反向击穿电压增大。从图7和图8很明显的是,根据第四实施例的齐纳二极管410具有比根据第一实施例的齐纳二极管10高的反向击穿电压。换言之,利用根据第四实施例的结构,即使当阳极区20和阴极区26之间的距离减小时,也能够得到等于根据第一实施例的齐纳二极管10的反向击穿电压。因此,利用根据第四实施例的结构,能够减少齐纳二极管的尺寸。
根据第四实施例的齐纳二极管410包括四个中间浓度区401至404。然而,只需要形成至少一个中间浓度区。
根据第一至第四实施例的齐纳二极管通过使用SOI基板而形成。然而,这些齐纳二极管可通过使用另一种基板,诸如体硅(silicon bulk)基板来形成。
在上述第一至第四实施例中,电流路径区22形成在阳极区20的下侧。然而,只要电流路径区22与阳极区20接触,电流路径区22可以形成在任何位置。例如,电流路径区22可以形成在暴露于SOI基板12的上表面并且邻近阳极区20的区内。然而,电流路径区22优选形成在阳极区20的下侧。如上所述,电流路径区22通过注入杂质而形成。杂质注入的深度方向(基板的厚度方向)的精度高,而杂质注入的横向方向(沿基板的表面的方向)的精度不那么高。这是因为在杂质注入时使用的掩模中发生位置偏离等。当电流路径区22布置在阳极区20的下侧,离子注入很难受制造误差影响,从而能够容易地将阳极区20和电流路径区22彼此邻近布置。通过这个配置,能够容易地制造齐纳二极管。
在根据第一至第四实施例的齐纳二极管中,反向击穿电压依赖于阳极区20和阴极区26之间的距离而变化。因此,在制造过程中,仅通过改变阳极区20和阴极区26之间的距离,就能够改变反向击穿电压而不需要附加过程。
上面详细描述了本发明的具体实施例。然而,这些仅是示例性的,并不限制所附权利要求的范围。所附权利要求中叙述的技术包括上面示出的具体实施例的各种修改和改变。在说明书或附图中描述的技术要素单独地或以各种组合行使技术有用性,并且不限于在提交时的权利要求中描述的组合。在说明书或附图中所描述的技术同时实现多个目的,并通过实现其中一个目的而具有技术有用性。
Claims (2)
1.一种齐纳二极管,其特征在于包括:
半导体基板;
阳极电极;以及
阴极电极,
所述半导体基板包括p型的阳极区、n型的电流路径区、n型的漂移区以及n型的阴极区,所述阳极区连接到所述阳极电极,所述电流路径区与所述阳极区接触,所述漂移区与所述阳极区和所述电流路径区接触,所述漂移区具有比所述电流路径区低的n型杂质浓度,所述阴极区连接到所述阴极电极,所述阴极区与所述漂移区接触,所述漂移区将所述阴极区与所述阳极区和所述电流路径区隔离,所述阴极区具有比所述漂移区高的n型杂质浓度,所述漂移区通过施加的反向电压被整个耗尽,所述反向电压比所述齐纳二极管的反向击穿电压低,并且
所述半导体基板是SOI基板,所述SOI基板包括第一半导体层、绝缘层和第二半导体层,所述绝缘层层压在所述第一半导体层上,所述第二半导体层层压在所述绝缘层上,
所述阳极区、所述电流路径区、所述漂移区和所述阴极区形成在所述第二半导体层中,
所述电流路径区形成在所述阳极区的下侧,
所述绝缘层形成在所述电流路径区的下侧,
所述第一半导体层形成在所述绝缘层的下侧,并且
所述第一半导体层连接到所述阴极电极。
2.根据权利要求1所述的齐纳二极管,其特征在于
所述漂移区的n型杂质浓度低于1×1015个原子/cm3。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013227332A JP5924328B2 (ja) | 2013-10-31 | 2013-10-31 | ツェナーダイオード |
JP2013-227332 | 2013-10-31 | ||
PCT/IB2014/002269 WO2015063574A1 (en) | 2013-10-31 | 2014-10-30 | Zener diode |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105684156A CN105684156A (zh) | 2016-06-15 |
CN105684156B true CN105684156B (zh) | 2018-12-04 |
Family
ID=51999458
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201480058416.7A Active CN105684156B (zh) | 2013-10-31 | 2014-10-30 | 齐纳二极管 |
Country Status (7)
Country | Link |
---|---|
US (1) | US10002974B2 (zh) |
JP (1) | JP5924328B2 (zh) |
KR (1) | KR101797882B1 (zh) |
CN (1) | CN105684156B (zh) |
DE (1) | DE112014005020B4 (zh) |
TW (1) | TWI545782B (zh) |
WO (1) | WO2015063574A1 (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6946783B2 (ja) * | 2017-06-30 | 2021-10-06 | 富士電機株式会社 | 半導体装置および半導体モジュール |
US10845395B2 (en) | 2018-02-08 | 2020-11-24 | Honeywell International Inc. | Intrinsically safe Zener diode barrier with indication |
KR102535796B1 (ko) | 2018-11-02 | 2023-05-25 | 삼성디스플레이 주식회사 | 화소, 이를 포함한 표시 장치, 및 표시 장치의 제조 방법 |
CN116995102B (zh) * | 2023-09-26 | 2023-12-08 | 成都翌创微电子有限公司 | 一种低温漂齐纳器件及其制造方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3144527B2 (ja) | 1994-05-25 | 2001-03-12 | ローム株式会社 | 高濃度pn接合面を有する半導体装置の製造方法 |
US5578506A (en) * | 1995-02-27 | 1996-11-26 | Alliedsignal Inc. | Method of fabricating improved lateral Silicon-On-Insulator (SOI) power device |
JPH10242159A (ja) | 1997-02-25 | 1998-09-11 | Mitsubishi Electric Corp | 定電圧ダイオード内蔵トランジスタ |
JP3843570B2 (ja) * | 1997-12-25 | 2006-11-08 | 富士電機デバイステクノロジー株式会社 | 横型ダイオード |
US7465964B2 (en) * | 2005-12-30 | 2008-12-16 | Cambridge Semiconductor Limited | Semiconductor device in which an injector region is isolated from a substrate |
SE532625C2 (sv) * | 2007-04-11 | 2010-03-09 | Transic Ab | Halvledarkomponent i kiselkarbid |
JP2009141019A (ja) * | 2007-12-04 | 2009-06-25 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2009158643A (ja) * | 2007-12-26 | 2009-07-16 | Toshiba Corp | 半導体装置 |
US7638857B2 (en) * | 2008-05-07 | 2009-12-29 | United Microelectronics Corp. | Structure of silicon controlled rectifier |
US8198703B2 (en) * | 2010-01-18 | 2012-06-12 | Freescale Semiconductor, Inc. | Zener diode with reduced substrate current |
US9184255B2 (en) * | 2011-09-30 | 2015-11-10 | Infineon Technologies Austria Ag | Diode with controllable breakdown voltage |
JP2013149768A (ja) * | 2012-01-19 | 2013-08-01 | Tokai Rika Co Ltd | サージ保護用半導体装置 |
JP2013183039A (ja) * | 2012-03-02 | 2013-09-12 | Renesas Electronics Corp | 半導体装置および半導体装置の製造方法 |
-
2013
- 2013-10-31 JP JP2013227332A patent/JP5924328B2/ja not_active Expired - Fee Related
-
2014
- 2014-10-30 KR KR1020167010934A patent/KR101797882B1/ko active IP Right Grant
- 2014-10-30 TW TW103137608A patent/TWI545782B/zh active
- 2014-10-30 US US15/030,735 patent/US10002974B2/en active Active
- 2014-10-30 CN CN201480058416.7A patent/CN105684156B/zh active Active
- 2014-10-30 WO PCT/IB2014/002269 patent/WO2015063574A1/en active Application Filing
- 2014-10-30 DE DE112014005020.2T patent/DE112014005020B4/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
TW201526250A (zh) | 2015-07-01 |
WO2015063574A1 (en) | 2015-05-07 |
DE112014005020B4 (de) | 2021-06-17 |
KR101797882B1 (ko) | 2017-11-15 |
TWI545782B (zh) | 2016-08-11 |
KR20160063370A (ko) | 2016-06-03 |
US10002974B2 (en) | 2018-06-19 |
JP5924328B2 (ja) | 2016-05-25 |
CN105684156A (zh) | 2016-06-15 |
JP2015088670A (ja) | 2015-05-07 |
DE112014005020T5 (de) | 2016-08-04 |
US20160254390A1 (en) | 2016-09-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5787853B2 (ja) | 電力用半導体装置 | |
CN102456716B (zh) | 半导体器件 | |
CN102468337B (zh) | 半导体器件 | |
JP6242633B2 (ja) | 半導体装置 | |
TW200739750A (en) | Lateral power devices with self-biasing electrodes | |
CN105684156B (zh) | 齐纳二极管 | |
TWI569457B (zh) | 蕭特基二極體結構 | |
US9472614B2 (en) | Super junction semiconductor device | |
US20130248882A1 (en) | Semiconductor device | |
JP2014120685A (ja) | 半導体装置 | |
CN104882474A (zh) | 半导体装置 | |
CN102569298A (zh) | 包括二极管的半导体器件 | |
CN103477437A (zh) | 功率半导体装置 | |
WO2014140000A3 (en) | Lateral single-photon avalanche diode and their manufacturing method | |
JP5737021B2 (ja) | 半導体装置 | |
JP2011142339A (ja) | 半導体素子 | |
JP6588774B2 (ja) | 半導体装置 | |
JP2015170654A (ja) | 半導体装置 | |
JP6658955B2 (ja) | 半導体装置 | |
US9018640B1 (en) | Silicon carbide power device equipped with termination structure | |
JP2016149429A (ja) | 逆導通igbt | |
US9184247B2 (en) | Power semiconductor device capable of maintaining a withstand voltage | |
CN103426909B (zh) | 包括第一和第二半导体材料的半导体器件 | |
CN104733508B (zh) | 带静电保护结构的mosfet及其制备方法 | |
CN107946350A (zh) | 一种带有衬底埋层的半导体装置及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20200414 Address after: Aichi Prefecture, Japan Patentee after: DENSO Corp. Address before: Aichi Prefecture, Japan Patentee before: Toyota Motor Corp. |
|
TR01 | Transfer of patent right |