CN105575959A - 集成电路装置 - Google Patents
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- CN105575959A CN105575959A CN201510588853.6A CN201510588853A CN105575959A CN 105575959 A CN105575959 A CN 105575959A CN 201510588853 A CN201510588853 A CN 201510588853A CN 105575959 A CN105575959 A CN 105575959A
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Abstract
本发明公开一种集成电路装置。一种集成电路装置,上述集成电路装置包括一基板;一第一电容,设置于上述基板上;一第一金属图案,耦接至上述第一电容的第一电极;一第二金属图案,耦接至上述第一电容的第二电极;一第三金属图案,设置于上述第一金属图案和上述第二金属图案上方,且覆盖上述第一电容、上述第一金属图案和上述第二金属图案,其中上述第三金属图案为电性接地;一电感,设置于上述第三金属图案上方。
Description
技术领域
本发明涉及一种集成电路装置,特别是涉及一种具有芯片上电感元件的集成电路装置的电容配置方式。
背景技术
螺旋电感已广泛应用于射频/高速集成电路设计中。通常为了避免影响电感效能和产生不想要的串音(crosstalk),在电感的占据区域不允许设置电子元件,以降低涡电流损耗(eddycurrentloss)和耦合(coupling)等现象。然而,由于电感占据相当大的硅基板面积,会造成芯片制造成本的瓶颈。
因此,在此技术领域中,需要一种改良式的集成电路装置。
发明内容
为解决上述问题,本发明的一实施例提供一种集成电路装置,上述集成电路装置包括一基板;一第一电容,设置于上述基板上;一第一金属图案,耦接至上述第一电容的第一电极;一第二金属图案,耦接至上述第一电容的第二电极;一第三金属图案,设置于上述第一金属图案和上述第二金属图案上方,且覆盖上述第一电容、上述第一金属图案和上述第二金属图案,其中上述第三金属图案为电性接地;一电感,设置于上述第三金属图案上方。
附图说明
图1为本发明一些实施例的一集成电路装置的俯视示意图;
图2为图1的局部放大示意图,其显示设置于电感元件下方的接地遮蔽金属图案,和设置于接地遮蔽金属图案下方的用以耦接电容的电极的金属图案的布局示意图;
图3为沿图2的C-C’切线的剖面示意图,其显示本发明一实施例的设置于不同接地遮蔽金属图案下方的数个金属-氧化物-半导体电容的剖面示意图;
图4为沿图2的D-D’切线的剖面示意图,其显示本发明另一实施例的设置于相同接地遮蔽金属图案下方的数个金属-氧化物-半导体电容的剖面示意图;
图5为沿图2的C-C’切线的剖面示意图,其显示本发明另一实施例的设置于不同接地遮蔽金属图案下方的数个金属-氧化物-金属电容的剖面示意图;
图6为沿图2的C-C’切线的剖面示意图,其显示本发明又一实施例的设置于不同接地遮蔽金属图案下方的数个金属-氧化物-金属电容的剖面示意图;
图7为沿图2的C-C’切线的剖面示意图,其显示本发明其他实施例的设置于不同接地遮蔽金属图案下方的数个金属-氧化物-半导体电容和金属-氧化物-金属电容的剖面示意图。
符号说明
200~基板;201~表面;
202~阱区;204~栅极氧化层;
206~栅极;208~栅极结构;
210~源极;212~漏极;
214、216、218~氧化层;250~电感;
252~内圈部分;254~外圈部分;
256~连接部分;300~金属图案;
300-1、300-2~金属连接部分;
302-1、302-2、304-1、304-2~金属图案;
310、312、314~金属层;350~内连线结构;
400a~金属-氧化物-半导体电容;400b~400d~金属-氧化物-金属电容;
500、500a~500d~集成电路装置;600~局部;
C1~C8~等效电容;S~间距;
M1~第一层金属层;M2~第二层金属层;
M3~第三层金属层;M4~第四层金属层;
M5~第五层金属层;M6~第六层金属层;
M7~第七层金属层。
具体实施方式
为了让本发明的目的、特征、及优点能更明显易懂,下文特举实施例,并配合所附的附图,做详细的说明。本发明说明书提供不同的实施例来说明本发明不同实施方式的技术特征。其中,实施例中的各元件的配置为说明之用,并非用以限制本发明。且实施例中附图标号的部分重复,是为了简化说明,并非意指不同实施例之间的关联性。
本发明实施例提供一种集成电路装置,其有关于一电容的配置方式。上述集成电路装置于一芯片上电感元件(on-chipinductor)和基板之间的区域中设置一电容元件,且上述电容元件设置接地遮蔽金属图案(groundshieldmetalpattern)用以屏蔽芯片上电感元件的接地遮蔽金属图案的正下方。在本发明一些其他实施例中,上述电容可做为电源网络(powernet)的去耦合电容(de-couplingcapacitor)。
图1为本发明一些实施例的一集成电路装置500的俯视示意图。在本发明一些实施例中,集成电路装置500的主要元件包括一基板200、一电感250、多个金属图案300以及至少一电容(图1未显示),上述电容会利用图3~图7加以说明。如图1所示,电感250和金属图案300为位于基板200上方的内连线结构(包括交互堆叠的多层金属层和多层介电层)的部分元件。另外,为清楚显示基板200、电感250和金属图案300彼此之间的位置关系,内连线结构中设置于电感250和金属图案300之间的不同层别的金属层和介电层在此不予显示。
在本发明一实施例中,基板200可为硅基板、锗化硅(SiGe)基板、块状半导体(bulksemiconductor)基板、应变半导体(strainedsemiconductor)基板、化合物半导体(compoundsemiconductor)基板、绝缘层上覆硅(SOI)基板或其他常用的半导体基板。另外,在本发明实施例中,可将p型或n型不纯物注入基板200中,以针对设计需要改变其导电类型。在本发明一些实施例中,基板200可包括一个或多个隔绝物,从基板200的一顶面延伸进入部分基板200中。上述隔绝物可包括硅局部氧化物(LOCOS)或浅沟槽隔离物(STI),其用以定义出基板200的主动区(activeregion)。
在本发明一实施例中,电感250设置于基板200上方。电感250是利用内连线结构的最顶层金属层(Mtop)形成,或利用最顶层金属层(Mtop)和顶层下一层金属层(Mtop-1)形成。如图1所示,电感250可包括实质上彼此平行且同中心设置的一内圈部分252和一外圈部分254。电感250的内圈部分252和外圈部分254可通过一连接部分256彼此连接,且内圈部分252和外圈部分254的形状可包括圆形、四边形或多边形。当电感250的内圈部分252和外圈部分254利用内连线结构的最顶层金属层(Mtop)形成时,上述连接部分256可由内连线结构的连接最顶层金属层的介层孔插塞和顶层下一层金属层(Mtop-1)形成。当电感250的内圈部分252和外圈部分254分别利用内连线结构的最顶层金属层(Mtop)和顶层下一层金属层(Mtop-1)形成时,上述连接部分256可由内连线结构的连接最顶层金属层和和顶层下一层金属层的介层孔插塞形成。
在本发明一实施例中,金属图案300设置于电感250的正下方,且金属图案300与电感250分别属于内连线结构的不同的金属层别,意即占据内连线结构的不同层金属层。在本发明一些其他实施例中,金属图案300与电感250至少相隔两层以上的金属层。举例来说,当内连线结构使用七层金属层形成时,电感250可利用第七层金属层(M7)及/或第六层金属层(M6)形成,而金属图案300可利用第二层金属层(M2)、第三层金属层(M3)或第四层金属层(M4)形成。在本发明一些实施例中,金属图案300做为电感250的接地遮蔽金属图案(groundshieldmetalpattern)。且如图1所示,上述多个金属图案300所占据区域的面积大于电感250所占据区域的面积,因而会使电感250的占据区域的边界会位于上述多个金属图案300所占据区域的边界内。
图2为图1的局部600的放大示意图,其显示设置于电感元件下方的接地遮蔽金属图案300,和设置于接地遮蔽金属图案下方的用以耦接电容的电极的金属图案的布局示意图。如图2所示,上述多个金属图案300为多个形状实质相同的金属条组成。请同时参考图1、图2,沿通过电感250的相对转角部分的对角线A1-A1’和A2-A2’可将金属图案300划分为四个区域,各个区域内的金属图案300彼此隔开,以降低金属图案300与电感250的转角部分之间的耦合效应。并且,各个区域内的金属图案300以相同间距S平行设置。另外,分别位于相邻区域的两个相邻的金属图案300彼此垂直设置,且彼此以相同间距S隔开。因此,位于两个彼此相对区域的金属图案300并不相连。在本发明一实施例中,上述金属图案300可通过位于相同金属层别的金属连接部分300-1、300-2彼此相连,并耦接至独立接地节点(groundnode)或一电源网络的一接地节点。换句话说,金属图案300为电性接地。金属连接部分300-1、300-2可具有实质上沿着上述多个金属图案300的外侧边界延伸的环状部分以与上述多个金属图案300连接。上述金属图案300可将电感250与基板200电性隔离,以避免涡电流损耗(eddycurrentloss),且降低电感250与设置于基板200的其他电子元件之间产生不想要的串音(crosstalk)和耦合(coupling)等现象。
对本领域技术人员而言,基于本发明的实施例所教示的内容对接地遮蔽金属图案300略加变化,使接地遮蔽金属图案对因电感250的磁场感应而生成涡电流的垂直方向切割,而达到有效降低涡电流的影响,提高电感250的品质因子。
接着,利用图3~图4说明本发明一实施例的集成电路装置500a的剖面示意图。集成电路装置500a包括设置于电感及接地遮蔽金属图案(金属图案300)的正下方的金属-氧化物-半导体电容(以下简称MOS电容)400a。图3为沿图2的C-C’切线的剖面示意图,图4为沿图2的D-D’切线的剖面示意图。并且,如图3的剖面示意图显示设置于不同接地遮蔽金属图案下方的数个MOS电容400a的剖面示意图,图4显示本发明另一实施例的设置于相同接地遮蔽金属图案下方的数个MOS电容400a的剖面示意图。为了清楚显示集成电路装置500a的位于内连线结构中的电感、接地遮蔽金属图案、MOS电容电极接线的层别关系,以及MOS电容400a和基板200的层别关系,在图3~图4中增加金属图案300(接地遮蔽金属图案)上方的不同层别金属层(包括电感250),并标示内连线结构350的位置。
如图3、图4所示,在本发明一实施例中,MOS电容400a设置于p型(p-type)基板200上,且位于金属图案300的正下方。MOS电容400a包括一阱区202、一栅极结构208、一源极210和一漏极212。阱区202从基板200的一表面201延伸至部分基板200中,且阱区202掺杂p型(p-type)材料。在本发明一些实施例中,阱区202可为电性浮接(electricallyfloating)。MOS电容400a的栅极结构208设置于阱区202上,其包括一栅极氧化层204和位于栅极氧化层204上的一栅极206。源极210和漏极212分别形成于阱区202上,且从基板200的一表面201延伸至部分基板200中。源极210和漏极212位于栅极结构208的二个相对侧。源极210和漏极212掺杂n型(n-type)材料。在本发明一些实施例中,栅极结构208做为MOS电容400a的一电极,且源极210和漏极212一起做为MOS电容400a的另一电极。
配合以上实施例的说明,在本发明的另一实施例以金属氧化物半导体变容器(MOSVaractor)或是以p型(p-type)MOS电容设置于基板200上,且位于金属图案300的正下方,也可达到相同的技术效果。
在现有的半导体制作工艺技术中,不同类的阱区中间经由STI(shallowtrenchisolation)制作工艺配置绝缘区,避免相临却不同类的阱区之间的漏电电流。另一方面,现有的半导体制作工艺技术是经由离子注入方式与扩散制作工艺形成阱区,然而受限半导体制作工艺技术,在阱区的离子注入浓度均匀度控制不易,特别是在阱区的边缘处离子注入浓度较阱区其它地区的离子注入浓度为高,使得阱区边缘处上形成的晶体管特性与阱区内其它地区上形成的晶体管特性产生差异,这又被称为是阱邻近效应(wellproximityeffect)。为降低阱邻近效应的影响并且对布局空间利用最佳化,现有技术会将多个相同类型的晶体管配置同一阱区。
请再参考图3,设置于不同接地遮蔽金属图案(金属图案300)下方的不同MOS电容400a的阱区202的边界可分别对齐金属图案300的边界或位于金属图案300的边界的外侧。值得注意的是,不同接地遮蔽金属图案(金属图案300)下方的不同MOS电容400a的阱区202彼此隔开而不互连,以确保金属图案300对MOS电容400a的接地遮蔽效果不受影响。另外,如图3所示,位于每一条金属图案300的正下方的MOS电容400a的栅极206、源极210和漏极212的延伸方向可实质上平行金属图案300的延伸方向。值得注意的是,电感250在对基板投影方向所视,p-type阱区202被金属图案300所覆盖,而基板200则位于未被金属图案300所覆盖的区域。
请再参考图4,在本发明的另一实施例中各个MOS电容400a的栅极206、源极210和漏极212的延伸方向可实质上垂直金属图案300的延伸方向。设置于相同接地遮蔽金属图案(金属图案300)下方的不同MOS电容400a的阱区202可彼此隔开而不互连,或者可彼此相连。或者,可于同一条金属图案300的正下方设置数个不同的MOS电容400a。
请再参考图2~图4,金属图案300与电感250之间可相隔至少两层以上的金属层。如图3、图4所示,举例来说,金属图案300形成于第二层金属层M2,电感250形成于第六层金属层M6与第七层金属层M7,金属图案300与电感250之间可通过位于第三层金属层M3的金属层310、位于第四层金属层M4的金属层312和位于第五层金属层M5的金属层314的三层金属层彼此隔开,且金属图案300与电感250之间垂直投影在金属层310(第三层金属层M3)、312(第四层金属层M4)、314(第五层金属层M5)的区域未有线路布置。另外,金属图案300的正下方可设置至少两条彼此平行的金属图案302-1、302-2。上述金属图案302-1、302-2分别耦接至MOS电容400a的两个电极,举例来说,金属图案302-1耦接至至MOS电容400a的源极210和漏极212,而金属图案302-2耦接至至MOS电容400a的栅极206。上述金属图案302-1、302-2可视为MOS电容400a的电极导线,金属图案302-1耦接至一电源网络的一接地节点(groundnode)或者耦接至金属图案300,且金属图案302-2耦接至一电源网络的一电源节点(powernode)。换句话说,金属图案302-1为电性接地。如图3所示,MOS电容400a的等效电容以C1标示。
配合以上实施例的说明,在本发明的另一实施例中,电感250还可形成于第六层金属层M6,第七层金属层M7以及位于第三层金属层M3的金属层310、位于第四层金属层M4的金属层312和位于第五层金属层M5的金属层314,用于形成三圈或更多闸圈的电感。
请再参考图2~图4,在本发明一些实施例中,金属图案302-1、302-2属于相同的金属层别,且分别与金属图案300属于不同的金属层别。换句话说,金属图案302-1、302-2分别与金属图案300占据内连线结构350的不同层金属层。金属图案300、金属图案302-1、302-2可通过上述内连线结构350的介电层(图未显示)彼此隔开且彼此平行。举例来说,当金属图案300利用第二层金属层M2形成时,金属图案302-1、302-2可利用第一层金属层M1形成。并且,MOS电容400a位于金属图案302-1、302-2的正下方。金属图案302-1、302-2可具有与金属图案300相同或相似的形状(轮廓),举例来说,金属图案302-1、302-2可为与金属图案300形状相同或相似的金属条。并且,金属图案302-1、302-2的宽度可设计小于金属图案300的宽度的二分之一。因此,在一俯视图(图2)中,金属图案302-1的一边界和金属图案302-2的一边界分别位于金属图案300的一边界内。意即金属图案302-1和金属图案302-2分别被金属图案300完全覆盖,以确保金属图案300对金属图案302-1、302-2和MOS电容400a的接地遮蔽效果不受影响。
图5为沿图2的C-C’切线的剖面示意图,其显示本发明另一实施例的集成电路装置500b的剖面示意图。集成电路装置500b包括设置于不同接地遮蔽金属图案下方的数个金属-氧化物-金属电容(MOMcapacitor)400b。上述附图中的各元件如有与图1~图4所示相同或相似的部分,则可参考前面的相关叙述,在此不做重复说明。
如图5所示,在本发明一实施例中,金属-氧化物-金属电容(以下简称MOM电容)400b设置于基板200上。MOM电容400b的主要元件包括金属图案300、金属图案302-1、302-2,以及设置于金属图案300与金属图案302-1、302-2的一氧化层214。氧化层214可为内连线结构350中的一介电层。另外,金属图案302-1、302-2可为内连线结构350中相同层别的金属层,且分别与金属图案300为内连线结构350中相邻层别的金属层。举例来说,当金属图案300利用第二层金属层M2形成时,金属图案302-1、302-2可利用第一层金属层M1形成。在本发明其他实施例中,金属图案302-1、302-2可通过两层以上垂直堆叠的氧化层与金属图案300相隔,仅需注意上述氧化层中不包括任何金属图案内嵌于其中。在本实施例中,上述金属图案302-1、302-2可视为MOM电容400b的电极,金属图案302-1耦接至一电源网络的一接地节点(groundnode)或者耦接至金属图案300,且金属图案302-2耦接至一电源网络的一电源节点(powernode)。换句话说,金属图案302-1为电性接地。如图5所示,MOM电容400b的等效电容为金属图案302-1、302-2之间的等效电容C2和金属图案302-2与金属图案300之间的等效电容C3的总合。
图6为沿图2的C-C’切线的剖面示意图,其显示本发明又一实施例的集成电路装置500c的剖面示意图。集成电路装置500c包括设置于不同接地遮蔽金属图案下方的数个金属-氧化物-金属电容(MOMcapacitor)400c。上述附图中的各元件如有与图1~图5所示相同或相似的部分,则可参考前面的相关叙述,在此不做重复说明。图6所示的集成电路装置500c与图5所示的集成电路装置500b的不同处为,集成电路装置500c包括设置于金属图案300与金属图案302-1、302-2之间的金属图案304-1、304-2,设置于金属图案304-1、304-2与金属图案302-1、302-2之间的氧化层216,以及设置于金属图案300与金属图案304-1、304-2之间的氧化层218。氧化层216、218可属于内连线结构350中的一介电层。另外,金属图案302-1、302-2可属于内连线结构350中相同层别的金属层。金属图案304-1、304-2可属于内连线结构350中相同层别的金属层。金属图案302-1、302-2分别与金属图案304-1、304-2、金属图案300属于内连线结构350中不同层别的金属层。举例来说,当金属图案300利用第三层金属层M3形成时,金属图案304-1、304-2可利用第二层金属层M2形成,且金属图案302-1、302-2可利用第一层金属层M1形成。在本发明其他实施例中,金属图案304-1、304-2可通过两层以上垂直堆叠的氧化层与金属图案300及/或金属图案302-1、302-2相隔,仅需注意上述氧化层中不包括任何金属图案内嵌于其中。
在本实施例中,上述金属图案302-1、302-2、304-1、304-2可视为MOM电容400c的电极。并且,上述金属图案302-1、302-2、304-1、304-2中彼此相邻的金属图案分别耦接至不同的节点。举例来说,金属图案302-1耦接至接地节点,相邻于金属图案302-1的金属图案302-2、304-1耦接至电源节点,且相邻于金属图案302-2、304-1的金属图案304-2耦接至接地节点。换句话说,金属图案302-1、304-2为电性接地。如图6所示,MOM电容400c的等效电容为金属图案302-1、302-2之间的等效电容C4、金属图案302-1与金属图案304-1之间的等效电容C5、金属图案302-2与金属图案304-2之间的等效电容C6、金属图案304-1与金属图案300之间的等效电容C7和金属图案304-2与金属图案304-1、304-2之间的等效电容C8的总合。
图7为沿图2的C-C’切线的剖面示意图,其显示本发明其他实施例的集成电路装置500d的剖面示意图。图7所示的集成电路装置500d与图6所示的集成电路装置500c的不同处为,集成电路装置500d包括设置于不同接地遮蔽金属图案下方的数个MOM电容400c和设置于MOM电容400c下方的MOS电容400a。上述附图中的各元件如有与图1~图6所示相同或相似的部分,则可参考前面的相关叙述,在此不做重复说明。在本实施例中,上述金属图案302-1、302-2、304-1、304-2可视为MOM电容400c的电极,且金属图案302-1、302-2可视为MOS电容400a的电极。并且,上述金属图案302-1、302-2、304-1、304-2中彼此相邻的金属图案分别耦接至不同的节点。举例来说,金属图案302-1耦接至接地节点,相邻于金属图案302-1的金属图案302-2、304-1耦接至电源节点,且相邻于金属图案302-2、304-1的金属图案304-2耦接至接地节点。如图7所示,集成电路装置500d的等效电容为MOM电容400c和MOS电容400a的总合。
本发明实施例提供一种集成电路装置,其将一MOS电容及/或一MOM电容设置于芯片上电感元件的正下方,且位于用以屏蔽芯片上电感元件的接地遮蔽金属图案和基板之间的区域中。上述MOS电容利用设置于接地遮蔽金属图案的正下方,且利用位于MOS电容和接地遮蔽金属图案之间的两条彼此平行的金属图案做为电极导线,分别耦接至MOS电容的两个电极,且分别耦接至一电源网络的一接地节点和一电源节点。上述MOM电容可利用内连线结构中的至少两个金属图案和位于上述金属图案之间的氧化层形成,上述至少两个金属图案可分别做为MOM电容的两个电极,且分别耦接至一电源网络的一接地节点(或接地遮蔽金属图案)和一电源节点。上述MOM电容的等效电容包括两个金属图案与氧化层形成的电容值,以及两个金属图案分别与接地遮蔽金属图案和氧化层形成的电容值。在本发明一些实施例中,位于芯片上电感元件的正下方的电容配置可节省电路布局的面积,且可与现行半导体制作工艺相容且不会增加额外的制作工艺步骤及成本。另外,本发明实施例的设置于芯片上电感元件的正下方的电容可做为电源网络的去耦合电容,由于去耦合电容的操作频率远小于芯片上电感元件的操作频率,因而可避免对其他集成电路元件的干扰。
虽然结合以上实施例公开了本发明,然而其并非用以限定本发明,任何熟悉此项技术者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围应当以附上的权利要求所界定的为准。
Claims (25)
1.一种集成电路装置,包括:
基板;
第一电容,设置于该基板上;
第一金属图案,耦接至该第一电容的第一电极;
第二金属图案,耦接至该第一电容的第二电极;
第三金属图案,设置于该第一金属图案和该第二金属图案上方,且覆盖该第一电容、该第一金属图案和该第二金属图案,其中该第三金属图案为电性接地;以及
电感,设置于该第三金属图案上方。
2.如权利要求1所述的集成电路装置,还包括多个金属层,设置于该基板上,其中该第三金属图案与该第一金属图案分别占据该些金属层的不同层金属层,其中该第三金属图案与该第二金属图案分别占据该些金属层的不同层金属层。
3.如权利要求1所述的集成电路装置,其中在一俯视图中,该第三金属图案位于该电感的正下方,该第一金属图案和该第二金属图案位于该第三金属图案的正下方,该第一电容位于该第一金属图案和该第二金属图案的正下方,该第一金属图案的一边界和该第二金属图案的一边界分别位于该第三金属图案的一边界内。
4.如权利要求1所述的集成电路装置,其中该第一金属图案、该第二金属图案和该第三金属图案彼此隔开且彼此平行。
5.如权利要求1所述的集成电路装置,其中该第一电容为第一金属-氧化物-半导体变容器。
6.如权利要求1所述的集成电路装置,其中该第一电容为第一金属-氧化物-半导体电容,该第一金属-氧化物-半导体电容包括:
第一阱区,从在该基板的一表面延伸至部分该基板中;
第一栅极结构,设置于该第一阱区上;以及
源极和一漏极,分别位于该栅极结构的二个相对侧,其中该第一栅极结构为该第一电极,且该源极和该漏极为该第二电极。
7.如权利要求6所述的集成电路装置,其中该第一金属图案和该第二金属图案属于一第一金属层别,且该第三金属图案属于一第二金属层别,且该第二金属层别不同于该第一金属层别。
8.如权利要求6所述的集成电路装置,其中该第一金属图案耦接至一电源节点,且该第二金属图案为电性接地。
9.如权利要求6所述的集成电路装置,其中该集成电路装置还包括第四金属图案,设置该第一金属-氧化物-半导体电容的正上方,其中该第四金属图案属于该第二金属层别且与第三金属图案彼此隔开,其中该第四金属图案为电性接地。
10.如权利要求6所述的集成电路装置,还包括:
第二电容,设置于该基板和该第三金属图案之间。
11.如权利要求10所述的集成电路装置,其中该第二电容为第二金属-氧化物-半导体电容,与该第一金属-氧化物-半导体电容并排设置,其中该第二金属-氧化物-半导体电容的一第二阱区与该第一阱区彼此隔开。
12.如权利要求10所述的集成电路装置,其中该第二电容为第二金属-氧化物-金属电容,设置于该第一金属-氧化物-半导体电容的上方,包括:
第五金属图案和第六金属图案,设置于该第三金属图案的正下方;以及
氧化物层,设置于该第三金属图案、该第四金属图案和该第五金属图案之间。
13.如权利要求12所述的集成电路装置,其中该第五金属图案耦接至一电源节点,且该第六金属图案为电性接地。
14.如权利要求12所述的集成电路装置,其中该第一金属图案、该第二金属图案属于一第一金属层别,该第五金属图案和该第六金属图案属于一第二金属层别,且该第三金属图案属于一第三金属层别,且第一金属层别、该第二金属层别和该第三金属层别彼此不同。
15.如权利要求1所述的集成电路装置,其中该第一电容为第一金属-氧化物-金属电容,该第一金属-氧化物-金属电容包括:
第一氧化物层,设置于该第一金属图案、该第二金属图案和该第三金属图案之间,其中该第一金属图案为该第一金属-氧化物-金属电容的该第一电极,该第二金属图案为该第一金属-氧化物-金属电容的该第二电极。
16.如权利要求15所述的集成电路装置,其中该第一金属图案和该第二金属图案属于一第一金属层别,且该第三金属图案属于一第二金属层别,且该第二金属层别不同于该第一金属层别。
17.如权利要求15所述的集成电路装置,其中该第一金属图案属于一第一金属层别,该第二金属图案属于一第二金属层别,且该第三金属图案属于一第三金属层别,且第一金属层别、该第二金属层别和该第三金属层别彼此不同。
18.一种集成电路装置,包括:
基板,其中该基板上设有第一阱区及第二阱区;
第一电容,设置于该基板的该第一阱区上;
第二电容,设置于该基板的该第二阱区上;
第一金属图案,其中该第一金属图案包含第一金属线及第二金属线,该第一金属线及该第二金属线为电性接地且彼此相邻;以及
电感,设置于该第一金属图案上方,
其中,该第一金属线配置于该基板的该第一阱区与该电感之间,且该第二金属线配置于该基板的该第二阱区与该电感之间。
19.如权利要求18所述的集成电路装置,其中该第一阱区与该第二阱区经注入一不纯物于该基板所形成。
20.如权利要求19所述的集成电路装置,其中该不纯物为p型不纯物或为n型不纯物。
21.如权利要求18所述的集成电路装置,其中在一俯视图中,该第一金属线完全覆盖该第一阱区,且该第二金属线完全覆盖该第二阱区。
22.如权利要求21所述的集成电路装置,其中该基板暴露于该第一金属线与该第二金属线之间。
23.如权利要求18所述的集成电路装置,其中该第一电容为第一金属-氧化物-半导体变容器。
24.如权利要求18所述的集成电路装置,其中该第一电容为第一金属-氧化物-半导体电容,该第一金属-氧化物-半导体电容包括:
第一栅极结构,设置于该第一阱区上;以及
源极和一漏极,分别位于该栅极结构的二个相对侧,其中该第一栅极结构为该第一电极,且该源极和该漏极为该第二电极。
25.如权利要求18所述的集成电路装置,其中该第一电容与该第二电容并联。
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Also Published As
Publication number | Publication date |
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CN105575959B (zh) | 2018-06-15 |
CN107658288A (zh) | 2018-02-02 |
US9443842B2 (en) | 2016-09-13 |
US20160148926A1 (en) | 2016-05-26 |
US20160148929A1 (en) | 2016-05-26 |
US9443843B2 (en) | 2016-09-13 |
CN107658288B (zh) | 2020-02-07 |
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