US20010020875A1 - Method and apparatus for calibrating a frequency adjustable oscillator in an integrated circuit device - Google Patents
Method and apparatus for calibrating a frequency adjustable oscillator in an integrated circuit device Download PDFInfo
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- US20010020875A1 US20010020875A1 US09/824,277 US82427701A US2001020875A1 US 20010020875 A1 US20010020875 A1 US 20010020875A1 US 82427701 A US82427701 A US 82427701A US 2001020875 A1 US2001020875 A1 US 2001020875A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
- H03F3/45085—Long tailed pairs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
- H03B5/1212—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
- H03B5/1215—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1231—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more bipolar transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
- H03B5/124—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
- H03B5/1262—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising switched elements
- H03B5/1265—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising switched elements switched capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B2201/00—Aspects of oscillators relating to varying the frequency of the oscillations
- H03B2201/02—Varying the frequency of the oscillations by electronic means
- H03B2201/025—Varying the frequency of the oscillations by electronic means the means being an electronic switch for switching in or out oscillator elements
- H03B2201/0266—Varying the frequency of the oscillations by electronic means the means being an electronic switch for switching in or out oscillator elements the means comprising a transistor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B2201/00—Aspects of oscillators relating to varying the frequency of the oscillations
- H03B2201/02—Varying the frequency of the oscillations by electronic means
- H03B2201/0275—Varying the frequency of the oscillations by electronic means the means delivering several selected voltages or currents
- H03B2201/0283—Varying the frequency of the oscillations by electronic means the means delivering several selected voltages or currents the means functioning digitally
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45631—Indexing scheme relating to differential amplifiers the LC comprising one or more capacitors, e.g. coupling capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45638—Indexing scheme relating to differential amplifiers the LC comprising one or more coils
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J2200/00—Indexing scheme relating to tuning resonant circuits and selecting resonant circuits
- H03J2200/10—Tuning of a resonator by means of digitally controlled capacitor bank
Definitions
- This invention relates to integrated circuit devices, and more particularly to a method and apparatus for digitally controlling the capacitance of integrated circuit components using MOS field effect transistors.
- VCO voltage-controlled oscillator
- One well-known solution to this tolerance problem is to “trim” the integrated circuit until it operates within a set of pre-defined post-fabrication parameters.
- post-fabrication trimming techniques are performed after manufacturing and testing the integrated circuit and are designed to physically alter the integrated circuit using a variety of methods including “Zener-zapping”, laser trimming and fuse trimming.
- fuseable links in an integrated circuit can be blown until the integrated circuit performs adequately under selected nominal conditions.
- passive electrical devices can be “fine-tuned” until they have acceptable tolerance values under nominal conditions.
- the trimming techniques produce only static solutions. For example, in fuse trimming, although the devices may perform adequately under nominal conditions, they may not perform adequately under all of the operating conditions of the integrated circuit.
- the integrated circuit is permanently configured once the fuses are blown.
- an improved method for improving the tolerances of passive electrical devices in an integrated circuit is needed which does not require the use of post-fabrication trimming techniques. Further, an improved method and apparatus is needed which dynamically monitors and corrects the performance characteristics of integrated circuits under all operating conditions. The improved method and apparatus should monitor and correct the performance characteristics of tuned networks especially as these performance characteristics are adversely affected by poor tolerances of on-chip passive electrical devices.
- FIG. 1 shows a prior art attempt at solving the problem of implementing tuned circuits using on-chip passive electrical devices having poor or unacceptable tolerance values.
- two terminals of an integrated tuned circuit i.e., terminal A 101 and terminal B 103
- a bank of switchably connected capacitors C 1 through C n .
- Each of the capacitors is selectively coupled between the terminals 101 , 103 by closing an associated and respective coupling switch S n .
- capacitor C 1 102 is coupled between the terminals 101 , 103 by closing an associated switch S 1 110 .
- capacitor C 2 104 is coupled between the terminals 101 , 103 by closing an associated switch S 2 112 .
- capacitor C n 108 is coupled between the terminals 101 , 103 by closing an associated switch S n 116 . Because the individual capacitors are connected in a parallel configuration, the total capacitance between the terminals 101 , 103 is equal to the sum of the individual capacitors that are switched into the circuit (assuming that the switches do not also introduce capacitance to the circuit).
- the capacitors can be selectively switched in and out of the tuned circuit, thereby changing the capacitance between the terminals 101 , 103 to a desired value.
- the tuned circuit can be adjusted to operate within desired parameters by simply changing the capacitance between terminals A 101 and B 103 .
- this prior art approach is undesirable when the tuned circuit operates at relatively high frequencies.
- the bank of switches e.g., 110 , 112 , 114 , and 116
- the prior art solution shown in FIG. 1 also disadvantageously increases both the amount of space (i.e., integrated circuit real estate) and the amount of power required to accommodate and operate the switches. Power requirements are increased due to the D.C. current required to operate the bank of switches.
- the present invention provides such a method and apparatus.
- the present method and apparatus uses a one-bit or “binary” capacitor formed from a MOSFET transistor that can be switched from a first pre-determined capacitance value to a second pre-determined capacitance value by varying an applied control voltage between first and second pre-determined voltage values.
- a multi-bit digital capacitor can be implemented by connecting a bank of the binary capacitors in parallel, and by weighting the individual capacitors as desired. The multi-bit digital capacitor allows capacitance values to be customized to any desired and convenient value.
- the present invention is a novel apparatus comprising a one-bit or “binary” capacitor formed from a MOSFET integrated device that can be switched from a first pre-determined capacitance value C 1 to a second predetermined capacitance value C 2 by varying an applied control voltage between a first and a second pre-determined voltage value.
- An inventive multi-bit digital capacitor is implemented by connecting a bank of the binary capacitors in parallel, and by weighting the individual capacitors in a desired fashion.
- the multi-bit digital capacitor allows capacitance values within an integrated circuit device to be customized to any desired and convenient value.
- the gate-to-bulk capacitance of the binary capacitor is dependent upon the D.C. voltage applied between the gate of the device and electrically coupled well contact implant regions.
- the capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region where there is little or no voltage dependency and where the capacitance equals a first low capacitance of C 1 ; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C 2 .
- Simply changing the polarity of the applied D.C. voltage from a first value to a second value abruptly changes the capacitance of the binary capacitor from C 1 to C 2 .
- a plurality of binary capacitors is arranged in a parallel configuration to produce a digitally controlled capacitor.
- the digitally controlled capacitor can be used in any integrated circuit that requires a tightly controlled tuned network.
- One such application is a voltage-controlled oscillator (VCO).
- VCO voltage-controlled oscillator
- the inventive digitally controlled capacitor is used in implementing a LC-resonator circuit, which is part of a fully integrated VCO device.
- the LC resonance frequency of the LC-resonator is varied by digitally modifying the capacitance of the LC tank circuit.
- the LC tank circuit is tuned with respect to an applied D.C. control voltage.
- the center output frequency of the VCO is calibrated by digitally modifying the capacitance of the VCO's digitally controlled capacitor.
- a means for determining whether the VCO requires calibration and a means for calibrating the center output frequency of the VCO is also presented.
- the inventive VCO can be implemented in an integrated circuit design despite poor tolerance values typically associated with process variations in integrated circuit fabrication.
- the present invention advantageously increases the effectiveness of integrated circuit VCO designs, tuning networks, and the like.
- the present invention improves the performance of wireless communication devices without requiring the use of expensive and large discrete components.
- the present invention is particularly useful in broadband wireless digital communication systems such as CDMA cellular systems, however it can also find utility in other communication systems such as those made in accordance with the proposed Bluetooth standard.
- FIG. 1 is a prior art attempt at solving the problem of implementing tuned circuits using on-chip passive electrical devices having poor or unacceptable tolerance values.
- FIG. 2 shows a simplified cross-sectional view of a MOSFET structure configured for use as a “binary” capacitor in accordance with the present invention.
- FIG. 3 is a capacitance-voltage (CV) plot showing the dependency of the gate-to-bulk capacitance C gate-bulk versus the D.C. bias voltage applied between the gate and the well of the binary capacitor shown in FIG. 2.
- FIG. 4 a is a simplified schematic showing the binary capacitor of FIG. 2 configured for use as a digitally controlled multi-bit digital capacitor having a digitally selectable and variable capacitance.
- FIG. 4 b is a simplified schematic representation of the digital capacitor of FIG. 4 a.
- FIG. 5 is a plot showing how the capacitance of the multi-bit digital capacitor of FIG. 4 a varies depending upon the digital control word CAL word applied to the terminals of the plurality of binary capacitors shown in FIG. 4 a.
- FIG. 6 shows a differential mode implementation of the digital capacitor of FIG. 4 a.
- FIG. 7 is a schematic of a simple differential LC-oscillator circuit.
- FIG. 8 shows a modified version of the LC-resonator circuit of FIG. 7 wherein the digital capacitor of FIG. 4 a is connected in a parallel arrangement with an analog tuning varactor and a fixed LC-tank circuit capacitor.
- FIG. 9 is a schematic of a calibrating voltage-controlled oscillator (VCO) made in accordance with the present invention.
- FIG. 10 is a simplified schematic of the calibrating VCO of FIG. 9 using a simplified schematic representation of the digital capacitor of the present invention.
- FIG. 11 is a simplified block diagram of a phase locked loop (PLL) circuit 600 using the VCO of FIGS. 9 and 10.
- PLL phase locked loop
- FIG. 12 is a simplified block diagram demonstrating the principles of auto-calibration of the output center frequency of the inventive VCO of FIGS. 9 and 10.
- FIG. 13 shows a flowchart of one embodiment of a VCO center frequency auto-calibration method in accordance with the present invention.
- FIG. 2 shows a simplified cross-sectional view of a MOSFET structure configured for use as a “binary” capacitor in accordance with the present invention.
- a binary capacitor 200 made in accordance with the present invention preferably comprises an N-well (or “bulk”) 120 , N + well contact implant regions 122 , 124 , metal well contacts 126 , 128 , and a poly-silicon P-gate 130 .
- the binary capacitor 200 of the present invention is preferably formed by lightly doping the N-well implant layer 120 (for a p-channel MOSFET device) with appropriate n-type dopant materials.
- the N + well contact implant regions 122 , 124 preferably comprise highly doped N + regions diffused into the N-well implant layer 120 .
- the metal area of the P-gate 130 in conjunction with the insulating dielectric oxide layer and the semiconductor channel formed between the N + well contact implant regions 122 , 124 , create a parallel-plate capacitor.
- the capacitor is formed between the P-gate 134 and the electrically coupled metal well contacts 126 and 128 .
- the capacitance between the P-gate 130 and the well 120 (the “gate-to-bulk” capacitance C gate-bulk ) of the binary capacitor 200 varies depending upon the D.C. bias voltage applied between the P-gate terminal 134 and the well contact implant terminals 132 , 136 .
- FIG. 3 shows the dependency of the gate-to-bulk capacitance C gate-bulk upon the D.C. bias voltage that is applied between the P-gate terminal 134 and the well contact implant terminals 132 , 136 of the binary capacitor 200 of FIG. 2.
- the gate-to-bulk capacitance C gate-bulk varies between a first capacitance value C LOW and a second capacitance value C HIGH as the applied D.C. bias voltage is varied between a first threshold voltage V 1 and a second voltage threshold V 2 .
- V 1 and V 2 are applied to the P-gate terminal 134 with positive polarities with respect to the well contact terminals 132 , 136 . That is, V 1 and V 2 are applied as positive polarity voltages with respect to the N + well contact implant regions 122 , 124 .
- the binary capacitor 200 is said to be operating in an “accumulation” mode in this embodiment.
- C gate-bulk (V) C LOW .
- C gate-bulk (V) C HIGH .
- the D.C. bias voltage varies between the threshold voltages V 1 and V 2
- C gate-bulk (V) follows the slope as shown in FIG. 3 and varies between the first capacitance value C LOW and the second capacitance value C HIGH (i.e., the binary capacitor 200 behaves as a varactor in this relatively narrow voltage range).
- first lower capacitance C LOW that is flat over a relatively wide voltage range less than or equal to V 1
- second higher capacitance C HIGH that is flat over a relatively wide voltage range greater than or equal to V 2
- variable capacitance variable between C LOW and C HIGH in the relatively narrow range of voltages between V 1 and V 2 .
- the second capacitance value C HIGH is approximately two to three times greater than the first capacitance value C LOW . That is, C HIGH /C LOW is approximately equal to 2 or 3 in one preferred embodiment.
- Simply varying the device geometry and thereby making the physical size of the capacitor larger or smaller can vary the specific values of C LOW and C HIGH for any specific binary capacitor.
- the capacitance value is varied between C LOW and C HIGH .
- V 1 represents a Boolean logic value of “zero”
- V 2 represents a logical “one”
- the capacitance C gate-bulk (V) can be digitally controlled using one control bit to be equal to either C LOW (when a logical zero is applied) or C HIGH (when a logical one is applied).
- the device shown in FIG. 2 is referred to as a “binary” capacitor because the capacitance of the device 200 can be digitally controlled to be equal to one of two states.
- the digital control signal controls the difference or differential between C HIGH and C LOW (referred to hereinafter as the “differential capacitance”). That is C LSB (the differential capacitance of the binary capacitor 200 as controlled by a least significant bit of a digital control word) is equal to C HIGH minus C LOW .
- the binary capacitor 200 may be implemented using a bulk CMOS process.
- the binary capacitor may be implemented as an integrated circuit varactor structure that includes a P-gate/N-well layer structure preferably formed on a Silicon-on-Insulator (“SOI”) substrate.
- SOI Silicon-on-Insulator
- the varactor structure is completely isolated from the substrate of the integrated circuit by an oxide layer of the SOI substrate, and by oxide-filled trenches formed on both sides of the varactor structure. The trenches preferably extend to the oxide layer of the SOI substrate.
- This alternative embodiment of the binary capacitor 200 is described more fully in commonly assigned U.S. Pat. No. 6,172,378, entitled “Integrated Circuit Varactor having a Wide Capacitance Range,” issued on Jan. 9, 2001. This issued patent is incorporated by reference herein for its teachings of P-gate/N-well varactor structures.
- the binary capacitor 200 may be implemented as an integrated circuit varactor structure that includes an N-gate/P-well structure formed on either an N-substrate bulk CMOS substrate or an SOI CMOS substrate.
- the N-gate/P-well embodiment of the binary capacitor is identical to the P-gate/N-well structure of FIG. 2, with the exception that the N-gate/P-well structure uses p-type dopant materials in the place of the n-type dopant materials used in the N-well device.
- the well implant layer 120 is preferably lightly doped with appropriate p-type dopant materials.
- the contact implant regions 122 , 124 preferably comprise highly-doped P+ regions diffused into the P-well implant layer 120 in the preferred P-well implementation of the binary capacitor 200 of FIG. 2.
- the capacitance of the P-well binary capacitor 200 is controlled by applying a D.C. bias voltage between the N-gate terminal 134 and the electrically coupled well contact terminals 132 , 136 as described above with reference to the N-well device.
- V 1 and V 2 are applied to the N-gate terminal 134 as negative polarity voltages with respect to the P-well contact terminals 132 , 136 . That is, V 1 and V 2 are applied as negative voltages with respect to the P + well contact implant regions 122 and 124 .
- the binary capacitor is said to be operating in a “depletion” mode.
- C gate-bulk (V) varies between the first capacitance value C LOW and the second capacitance value C HIGH (i.e., the binary capacitor 200 behaves as a varactor in this relatively narrow voltage range).
- the applied voltage V applied is increased to become more and more negative (e.g., from ⁇ 0.5V to ⁇ 1.5V) as it changes from the “low” threshold voltage of V 1 to the “high” threshold voltage V 2 .
- N-gate/P-well integrated circuit varactor structure formed on an SOI substrate is described more fully in the incorporated U.S. Pat. No. 6,172,378. This issued patent is incorporated by reference herein for its teachings of N-gate/P-well varactor structures.
- the present binary capacitor 200 of FIG. 2 can be used as an integral building block in any integrated circuit that requires the use of passive components having improved tolerances.
- the binary capacitor 200 can be used to improve the performance of integrated circuit implementations of tuned capacitor networks such as voltage-controlled oscillators (VCO).
- VCO voltage-controlled oscillators
- the binary capacitor 200 of the present invention can be used to implement a means of calibrating (both manually and automatically) a tuned capacitor network such as a VCO.
- the present binary capacitor 200 is described below with reference to its use in an integrated circuit implementation of a VCO, this specific use is exemplary only and should not be interpreted as limiting the scope or application of the present invention.
- the binary capacitor 200 can be used to improve the performance of any integrated circuit requiring the use of passive electrical components.
- FIG. 4 a shows how the binary capacitor 200 described above with reference to FIGS. 2 and 3 is used to create a digitally controlled or multi-bit digital capacitor 300 having a digitally selectable and variable capacitance.
- a plurality of binary capacitors are preferably connected in parallel between two terminals (i.e., between terminal A 301 and terminal B 303 ) within an integrated circuit (not shown).
- the terminals A 301 and B 303 are analogous to the terminals A 101 and B 103 of FIG. 1 and, as described in more detail below, may be connected to a tuned circuit such as a VCO.
- the capacitance values of the binary capacitors are preferably weighted in a convenient and desirable manner.
- the binary capacitors of the multi-bit digital capacitor 106 are given binary weighting.
- the least-significant binary capacitor C 1 302 is manufactured to have a desired least significant (or lowest) differential capacitance of C LSB (defined as the difference between C 1 's highest capacitance C 1 HIGH and C 1 's lowest capacitance C 1 LOW ).
- the next significant binary capacitor C 2 304 is preferably manufactured to have a differential capacitance of twice C LSB , or 2*C LSB .
- the binary weighting is assigned in like fashion with each next significant capacitor having a differential capacitance that is a power of two greater than the previous significant capacitor.
- the most significant binary capacitor C n 306 is manufactured to have a differential capacitance of 2 n-1 *C LSB .
- the selected capacitor e.g., C 2
- the selected capacitor can be formed by placing two previous significant capacitors (in this example, C 1 ) in parallel.
- the next significant capacitor e.g., C 3
- the capacitors may be manufactured to different physical dimensions to have the desired differential capacitance characteristics.
- each binary capacitor can be manufactured to have a capacitance value that is ten times greater than its previous significant capacitor.
- binary capacitor C 2 304 can be manufactured to have a differential capacitance that is 10*C LSB , where C 1 302 is manufactured to have a differential capacitance of C LSB .
- C n is assigned a differential capacitance of 10 n-1 *C LSB .
- the differential capacitance of each binary capacitor of the digital capacitor 106 is individually controlled by an associated and respective digital control signal that is applied over the terminals of the associated binary capacitor (i.e., by an associated and respective digital bit of a digital control word applied between the respective gate and well contact terminals).
- the control bits are ordered from least significant bit (LSB) to most significant bit (MSB), and are assigned to control the least significant capacitor to the most significant capacitor. Accordingly, the binary capacitors are ordered from least significant to most significant. For example, as shown in FIG.
- the least significant bit LSB, B 1 of the digital control word is preferably applied over the terminals of the least significant binary capacitor C 1 302 and thereby controls the capacitance of the binary capacitor C 1 302 .
- the next most significant bit, B 2 is applied to the terminals of the binary capacitor C 2 and thereby controls its capacitance.
- the most significant bit, B n similarly controls the capacitance of binary capacitor C n .
- FIG. 4 b is a simplified schematic representation of the digital capacitor 106 shown in FIG. 4 a.
- FIG. 5 shows a plot of the capacitance of the digital capacitor 106 as it varies depending upon the digital control word CAL word 114 applied over the terminals of the plurality of binary capacitors.
- CAL word is assumed to be three bits wide and therefore, in this embodiment, the number of binary capacitors used to implement the digital capacitor 106 is three.
- C FLOOR C 1 LOW +C 2 LOW +C 3 LOW .
- the next higher capacitance value is produced using a control word CAL word of “001”.
- the capacitance of the digital capacitor 106 is equal to C 1 HIGH +C 2 LOW +C 3 LOW , or C FLOOR +C LSB .
- the capacitance of the digital capacitor 106 is increased to the next step to a value of C 1 LOW +C 2 HIGH +C 3 LOW , or C FLOOR +(2*C LSB ).
- the digital control word CAL word can be similarly incremented to produce the capacitance plot shown in FIG. 5.
- the capacitance of the digital capacitor 106 has its highest capacitance C MAX equal to C 1 HIGH +C 2 HIGH +C 3 HIGH when the digital control word CAL word is set equal to “111”. Stated in other terms, the highest capacitance C MAX of the digital capacitor is C FLOOR +(7*C LSB ).
- FIG. 6 shows a differential mode implementation of the digital capacitor 106 described above with reference to FIGS. 1 - 5 .
- the digital capacitor 106 is preferably implemented differentially because this provides a convenient third terminal for digitally controlling the capacitance values of the binary capacitors.
- the control signal B 1 is applied between the binary capacitors C 1 302 , 302 ′ at a control terminal 310 .
- the control signal B 2 is applied between the binary capacitors C 2 304 , 304 ′ at a control terminal 312 .
- the most significant control bit of the digital control word CAL word 114 , B n is applied between the binary capacitors C n , 306 , 306 ′ at a control terminal 314 .
- the control terminals are common mode AC grounds.
- the differential mode implementation of the digital capacitor 106 functions similarly to the digital capacitor 106 described above with reference to FIGS. 4 - 5 .
- the binary capacitors are preferably assigned a binary weighting, with the least significant capacitors C 1 302 , 302 ′ having the lowest differential capacitance (C LSB ).
- the differential capacitance of the binary capacitors 302 , 302 ′ is controlled at the control terminal 310 by the LSB of the digital control word CAL word , i.e., by B 1 .
- the differential capacitance of the next significant binary capacitors C 2 304 , 304 ′ is twice that of the least significant capacitors C 1 , or 2*C LSB .
- the capacitance of the binary capacitors C 2 304 , 304 ′ is similarly controlled at the control terminal 312 by the next most significant bit of the digital control word CAL word , i.e., by B 2 .
- the width of the control word CAL word corresponds to the number of binary capacitor pairs used in the differential mode implementation of the digital capacitor 106 .
- the differential capacitance of the most significant binary capacitors is equal to (2 n-1 *C LSB ).
- the MSB of the control word i.e., B n , controls the differential capacitance of the binary capacitors C n 306 , 306 ′.
- the total capacitance of the differential mode implementation of the digital capacitor 106 is as follows:
- C total C FLOOR +B 1 ′C LSB +B 2 ′(2 *C LSB )+ B 3 ′(4 *C LSB )+ . . . + B n ′* (2 n-1 C LSB );
- control word bits B n ′ determine whether the differential capacitance of the n th capacitor (C LSB or a multiple of C LSB in the case when n is higher than 2) is or is not added to C FLOOR . More specifically, if B n ′ is a logical zero, the differential capacitance of the n th capacitor is not added (i.e., C LSB , or its multiple, is not added to C FLOOR for the n th capacitor). If B n ′ is a logical one, then the differential capacitance of C LSB (or its multiple in the case of higher order bits) is added to C FLOOR for the n th capacitor.
- the capacitance of the digital capacitor 106 can be customized to any desired value.
- the step size shown in FIG. 5 i.e., the resolution of the capacitance of the digital capacitor 106 ) depends upon the C LSB of the capacitors.
- the digital capacitor 300 of FIG. 4 a and 300 ′ of FIG. 6 can be used in place of the switched-capacitor circuit 100 of FIG. 1 to provide a calibrated capacitor for use in virtually any integrated circuit implementation of a tuned capacitor network.
- the differential LC-oscillator 400 comprises an LC-resonator circuit 402 , an amplifier 404 , and a current source 405 .
- the oscillation frequency f o will be adversely affected. This is particularly disadvantageous when the oscillation frequency is relatively high, for example, when the oscillation frequency operates in the Gigahertz range. At such high frequencies, the tolerance variations of the passive electrical components will dramatically affect variations in the oscillation frequency. For example, with a desired oscillation frequency of 2 GHz, a ⁇ 10% tolerance will yield an oscillation frequency of 2 GHz ⁇ 200 MHz. This may be unacceptable in some applications.
- the components of the LC-oscillator 400 i.e., the L and C components
- should have low series losses i.e., the components should have high “Q” gain values
- FIG. 8 A modified version 402 ′ of the LC-resonator 402 of FIG. 7 is shown in FIG. 8.
- the digital capacitor C CAL 300 described above with reference to FIGS. 4 a and 4 b is connected in a parallel arrangement with an analog tuning varactor 406 and a fixed LC-tank circuit capacitor C L 408 as shown.
- C total C CAL +C tune +C L .
- the capacitance C L 408 is a fixed and known pre-determined value.
- the capacitance C tune is determined by applying a D.C. control voltage V tune 410 to the tuning varactor 406 .
- V tune 410 is applied to the tuning varactor 406 .
- C tune is tuned so that the oscillation frequency f o is nominally equal to a desired center frequency, for example, 2 GHz.
- the resonance or oscillation frequency f o may require calibration in order to re-center the LC-resonance frequency to a desired center frequency value.
- the digital capacitor C CAL 300 is used for this purpose.
- the capacitance of the digital capacitor is changed to a desired value, and the center frequency of the LC-resonator 402 ′ is thereby changed accordingly.
- the oscillation frequency f o is therefore calibrated and re-centered by appropriately adjusting the digital control word CAL word .
- Calibration of the LC-resonator 402 ′ oscillation frequency f o can be performed using either manual or automatic methods of calibration.
- the LC-resonator 402 ′ is manually calibrated by first measuring the oscillation frequency f o during a production testing phase of the integrated circuit fabrication process.
- the circuit is tuned to a desired oscillation frequency and the actual output frequency is measured. If the desired oscillation frequency differs from the measured output frequency the digital control word CAL word is modified until the output frequency equals the desired oscillation frequency.
- the calibration control word thereby determined for CAL word may then be stored in a non-volatile memory either within the same integrated circuit as the resonator or on a printed circuit board adjacent the integrated circuit.
- the oscillation frequency f o is automatically calibrated until a desired oscillation frequency is obtained.
- Such an automatic calibration method may be executed every time the circuit is powered on.
- the automatic calibration method is executed by a microprocessor or other data processing device located within the integrated circuit or on the same printed circuit board as the integrated circuit.
- the method can be implemented using any convenient or desirable sequencing device such as a state machine, present state-next state discrete logic, or field programmable gate array device.
- FIG. 9 shows a schematic of a voltage-controlled oscillator (VCO) made in accordance with the present invention.
- the VCO 500 shown in FIG. 9 uses both the differential mode implementation of the digital capacitor 300 ′ of FIG. 6 and a differential mode implementation of the LC-resonator 402 ′′ of FIG. 8 to produce a VCO that can be calibrated to generate a desired output frequency f o based upon a given control voltage and given digital control word.
- one preferred embodiment of the calibrating VCO 500 of the present invention comprises two inductors L 502 , 504 , the differential mode digital capacitor 300 ′ described in more detail above with reference to FIG. 6, an amplifier 404 ′, and a current source 405 .
- the amplifier 404 ′ functions similarly to the amplifier 404 of FIG. 7.
- the binary capacitors e.g., the LSB binary capacitor C 1 302 , 302 ′, next-significant binary capacitor C 2 304 , 304 ′, and MSB binary capacitor C 4 306 , 306 ′
- the binary capacitors function similarly to their respective and corresponding binary capacitors described above with reference to the differential mode digital capacitor of FIG. 6.
- FIG. 10 is a simplified schematic of the calibrating VCO 500 of FIG. 9 using the simplified schematic representation of the digital capacitor 300 ′. Similar to the operation of the LC-resonator 402 ′ of FIG. 8, the oscillation or output frequency f o of the VCO 500 is established by appropriately adjusting the analog tuning voltage V tune 410 to a desired D.C. voltage level.
- the inventive VCO 500 of FIGS. 9 and 10 allows circuit designers to accurately control the center frequency of the integrated circuit VCO. This is essential in some applications, especially when the VCO operates at relatively high frequencies.
- the present invention provides a VCO having much lower gain and sensitivity characteristics than prior art VCO designs. Owing to the calibration function provided by the digital capacitor 300 ′, the calibrating VCO 500 need be tunable only over a relatively narrow frequency range (i.e., the VCO only has to cover the frequency band of interest) as compared with the prior art VCO designs. Therefore, the present inventive VCO 500 is much less sensitive to noise than are the prior art VCO designs. The present VCO 500 performs better and is easier to implement that its prior art counterparts because it is less sensitive to low frequency noise and the deleterious effects of interfering RF signals.
- FIG. 11 is a simplified block diagram of a phase locked loop (PLL) circuit 600 that uses the VCO 500 described above with reference to FIGS. 9 and 10.
- the preferred embodiment of the PLL 600 comprises a multiplier or phase error detector 602 , a loop filter 604 , the VCO 500 , and a divide-by-M circuit 606 .
- the PLL 600 functions in a well-known manner to generate an output frequency f o that is locked in phase with a precision reference signal f r .
- the PLL 600 is a negative feedback system.
- the reference signal f r and the output of the divide-by-M circuit 606 are applied to the inputs of the multiplier 602 as shown in FIG. 11.
- the multiplier 602 produces both a high frequency and a low-frequency component.
- the high frequency component is eliminated by the combination of the loop filter 604 and the VCO 500 .
- the low frequency component output by the multiplier 602 contains information related to the phase error or difference in phase between the reference signal f r and the divided down output signal f o (i.e., the output of the VCO 500 as divided-down by the divide-by-M circuit 606 ).
- This phase error signal is filtered and used (as the tuning voltage V tune ) to control the frequency produced by the VCO 500 .
- the output signal generated by the VCO 500 is fed back to the divide-by-M circuit 606 thereby closing the PLL negative feedback loop.
- the PLL 600 When the phase error produced at the output of the multiplier 602 is zero, the PLL 600 is in a phase-lock condition.
- the reference frequency f r is maintained at a desirable base frequency, while the output center frequency f o is varied by varying the value of “M” in the divide-by-M circuit 606 (i.e., M can be assigned the values of M 1 , M 2 , M 3 , etc., with each M-value having an associated and corresponding output center frequency f o1 , f o2 , f o3 , etc.).
- the VCO 500 When the VCO 500 is used in a radio communication system designed in accordance with the proposed “Bluetooth” standard, the VCO 500 must be capable of generating output signals having a frequency range of at least 78 MHz (i.e., the tunable range of the VCO must be at least 78 MHz), starting at 2.402 GHz and stopping at 2.48 GHz. Spectrum spreading in Bluetooth is accomplished in 79 frequency channel hops displaced by 1 MHz per frequency channel. The VCO 500 must therefore be capable of generating output signals corresponding to the transmit and receive frequency channels used in Bluetooth. However, it is desirable to reduce the gain of the VCO in order to reduce sensitivity to low-frequency noise signals.
- the gain of the VCO 500 is approximately 50 MHz and the maximum tunable range of the VCO 500 is 300 MHz.
- f r is maintained at a base frequency of approximately 1 MHz.
- the VCO 500 generates multiple output channels separated by the 1 MHz reference frequency. More specifically, in an embodiment designed for use in a Bluetooth system, the output frequency varies between 2.402 GHz and 2.48 GHz at a 1 MHz channel spacing.
- the VCO 500 of the present invention can be modified for use in a wide variety of applications without departing from the scope of the claims.
- the tuning range and the output frequency channels generated by the inventive VCO 500 can be modified for use in a wideband communication system simply by changing the reference frequency, the value of M in the divide-by-M circuit 606 , and the value of CAL word .
- the VCO tuning range is approximately 300 MHz and the frequency channels are separated by approximately 16 MHz-wide steps.
- the inventive VCO 500 can also be used in applications such as use in implementing tunable filters.
- the output center frequency f o generated by the VCO 500 is automatically calibrated to fall approximately in the center of the VCO tuning range (i.e., centered between the minimum and maximum values of the tuning voltage V tune that is applied to the control input of the VCO 500 ).
- FIG. 12 shows a simplified block diagram that demonstrates the principles of auto-calibration of the VCO center frequency. As shown in FIG. 12, the VCO 500 generates an output frequency f o that is input to the phase locked loop circuit 600 described above with reference to FIG. 11. The PLL 600 performs a frequency-to-voltage conversion function whereby the output frequency f o is compared with a reference frequency f r to generate the tuning voltage V tune .
- the tuning voltage V tune is subsequently compared by a comparator 702 with a reference or threshold voltage V ref as shown in FIG. 12.
- the total capacitance of the LC-resonator circuit (FIG. 8) within the VCO 500 is modified based upon the comparison of the tuning voltage V tune with the reference or threshold voltage V ref .
- This voltage-to-capacitance function is performed by the digital capacitor circuit 300 , and specifically by updating the digital control word CAL word .
- FIG. 13 shows a flowchart of one embodiment of a VCO center frequency auto-calibration method 800 in accordance with the present invention.
- the method 800 shown in FIG. 13 is implemented in software instructions that are executed by a micro-processor, state machine, or other digital logic device operatively coupled to the inventive VCO 500 .
- the method 800 may also be implemented in hardware, or by use of discrete logic circuits.
- the VCO auto-calibration method 800 is initiated at STEP 801 when the VCO 500 is first powered on (i.e., after the VCO 500 enters a “powerup” state).
- the method 800 proceeds to a STEP 802 whereat the digital control word CAL word is initialized to a pre-determined value.
- CAL word is initialized to a value that is halfway between its maximum number (binary “1111”) and its minimum number (binary “0000”), that is, CAL word is set to a binary “ 1000”.
- the inventive VCO auto-calibration method 800 then proceeds to a waiting STEP 804 whereat the method waits for a pre-determined “settling” period of time.
- the method waits for the pre-determined “settling” period (shown as a scaling factor X 1 multiplied by a settling time T settle ) in order to allow the VCO 500 and the PLL 600 (FIG. 11) to settle after the powerup condition and to thereafter establish a nominal output frequency.
- the settling time can be determined experimentally and adjusted to meet the needs of specific VCO designs.
- the method 800 proceeds to a STEP 806 whereat a decision is made as to whether the radio system utilizing the VCO 500 is operating within a receive or transmit time slot.
- One preferred application for the present inventive VCO 500 is use in a frequency hop transceiver capable of generating receive and transmit frequencies in a wireless Time-Division Duplex scheme.
- One exemplary application of the inventive VCO 500 is in a radio system designed according to the proposed Bluetooth standard.
- the method 800 preferably prevents calibration of the VCO during the time slots that voice/data is being received or transmitted (i.e., during the Rx and Tx time slots). Accordingly, as shown in FIG. 13, if the VCO is currently operating in a receive/transmit time slot, the decision STEP 806 “yes” output will be followed and the VCO 500 will not be calibrated. The method 800 will continue to loop back to the decision STEP 806 until the VCO is no longer operating in a receive/transmit time slot.
- the method proceeds to a decision STEP 808 and determines whether a “channel jump” or “channel hop” condition exits.
- a decision STEP 808 determines whether a “channel jump” or “channel hop” condition exits.
- certain time slots are dedicated for frequency or channel “hopping.” Consequently, when the inventive auto-calibration method 800 determines that a channel hop has occurred in the STEP 808 , and that the channel frequency change or channel hop delta is greater than a pre-determined threshold, the method preferably proceeds to a STEP 810 and updates the digital control word CAL word to reflect the corresponding change in output frequency. More specifically, in the embodiment shown in FIG.
- one LSB of the digital control word CAL word changes the VCO 500 output frequency f o by 30 MHz.
- CAL word is updated accordingly at STEP 810 to change the center frequency of the VCO 500 .
- the CAL word is updated in STEP 810 to change the center frequency f o of the VCO by 60 MHz.
- the STEPS 806 , 808 and 810 can be eliminated when the VCO is not designed for use in a Time-Division Duplex wireless communication system having frequency or channel hopping.
- the method 800 of FIG. 13 proceeds directly from the waiting STEP 804 to a decision STEP 812 .
- the remainder of the inventive VCO auto-calibration method monitors the VCO analog tuning voltage V tune and determines whether the VCO output frequency f o requires calibration. For example, at the decision STEP 812 , the method determines whether the analog tuning voltage V tune is less than a pre-determined V out “low threshold” value “V out L.” In some situations, especially when the VCO 500 is first powered on, the PLL 600 can become locked into a condition wherein the output frequency f o is saturated to a given high frequency, and the analog tuning voltage becomes locked below a low threshold voltage of V out L. In this scenario, the method will modify the digital control word CAL word and thereby decrease the output frequency f o generated by the VCO 500 . The method will increase the digital control word CAL word to thereby decrease the output frequency, which, due to the negative feedback of the PLL 600 , will, in turn, increase the analog tuning voltage V tune .
- the method determines at STEP 812 that the analog tuning voltage V tune is greater than the low threshold value V out L, then the method proceeds to a decision STEP 822 whereat it determines whether the analog tuning voltage V tune is greater than a pre-determined V out “high threshold” value “V out H.”
- V out H a pre-determined V out “high threshold” value “V out H.”
- the method will modify the digital control word CAL word and thereby modify the output frequency f o generated by the VCO 500 .
- the method will decrease the digital control word CAL word and thereby increase the output frequency, which, due to the negative feedback of the PLL 600 , will decrease the analog tuning voltage V tune .
- the remainder of the method 800 is now described in more detail.
- the method proceeds to a waiting STEP 814 and waits for a pre-determined period of time for the output frequency of the VCO to settle. For example, as shown in FIG. 13, at the STEP 814 the method waits for a time period equal to a scaling factor “X 2 ” multiplied by a pre-defined settling time T settle to allow the VCO 500 to settle.
- the waiting time provided by STEP 814 is approximately 100 microseconds.
- both the scaling factor X 2 and the settling time T settle can be modified to accommodate various VCO designs without departing from the scope of the present invention.
- the method 800 waits during the waiting STEP 814 to determine whether the tuning voltage V tune is still less than the low threshold voltage V out L, and therefore whether the VCO still requires calibration.
- the method proceeds from the STEP 814 to a decision STEP 816 to determine whether the analog tuning voltage V tune is greater than the pre-defined high threshold V out H. If V tune is greater than V out H, the method returns to the STEP 806 and proceeds as described above. However, if V tune is less than V out H the method proceeds to decision STEP 818 to once again determine if the analog tuning voltage V tune is less than the low threshold V out L. If not, there is no reason to calibrate the VCO 500 , and the method returns to the STEP 806 and proceeds as described above.
- V tune is still less than the low threshold voltage V out L
- the method proceeds to the STEP 820 to calibrate the VCO 500 .
- calibration of the VCO 500 is preferably accomplished by modifying the digital control word CAL word .
- calibration is accomplished by increasing CAL word by one bit (i.e., CAL word ⁇ CAL word +1).
- Increasing CAL word by one bit causes the VCO output frequency to decrease, which, due to the negative-feedback operation of the PLL 600 , causes the tuning voltage V tune to increase.
- the method then returns to the STEP 806 to determine whether further calibration is required.
- the right side of the flowchart shown in FIG. 13 operates in a similar manner to decrease CAL word when the analog tuning voltage V tune is determined to be greater than a pre-defined high threshold voltage V out H.
- the method 800 waits during a STEP 824 to determine whether the tuning voltage V tune is still greater than the high threshold voltage V out H, and therefore whether the VCO still requires calibration.
- the method proceeds from the STEP 824 to a decision STEP 826 to determine whether the analog tuning voltage V tune is less than the pre-defined low threshold V out L. If V tune is less than V out L, the method returns to STEP 806 and proceeds as described above.
- V tune is greater than V out L
- the method proceeds to a decision STEP 828 to once again determine if the analog tuning voltage V tune is greater than the high threshold voltage V out H. If not, there is no reason to calibrate the VCO 500 , and the method returns to the STEP 806 and proceeds as described above. However, if V tune is still greater than the high threshold voltage V out H, the method proceeds to the STEP 830 to calibrate the VCO 500 .
- calibration of the VCO 500 is accomplished by modifying the digital control word CAL word . In this case, calibration is accomplished by decreasing CAL word by one bit (i.e., CAL word ⁇ CAL word ⁇ 1). Decreasing CAL word by one bit causes the VCO output frequency to increase, which, due to the negative-feedback operation of the PLL 600 , causes the tuning voltage V tune to decrease. The method then returns to the STEP 806 to determine whether further calibration is required.
- the invention includes a digital or binary capacitor comprised of a MOSFET device wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to the D.C. voltage applied between its gate and well implant regions.
- the capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region where there is little or no voltage dependency and where the capacitance equals a first low capacitance of C 1 ; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C 2 .
- the capacitance of the binary capacitor can be changed from C 1 to C 2 simply by changing the polarity of the applied D.C. voltage from a positive to a negative value.
- a plurality of binary capacitors are configured in a parallel arrangement to produce a digitally-controlled capacitor.
- the digitally-controlled capacitor can be used in any integrated circuit requiring a tightly controlled tuned network.
- One application is a voltage-controlled oscillator (VCO) wherein the center output frequency of the VCO is calibrated by digitally modifying the capacitance of the VCO's digitally controlled capacitor.
- VCO voltage-controlled oscillator
- a means for determining whether the VCO requires calibration and a means for calibrating the center output frequency of the VCO is presented. Consequently, the inventive VCO can be implemented in an integrated circuit design despite poor tolerance values typically associated with process variations in integrated circuit fabrication.
- the present invention advantageously increases the effectiveness of integrated circuit VCO designs, tuning networks, and the like.
- the present invention improves the performance of wireless communication devices without requiring the use of expensive and large discrete components.
- the present invention is particularly useful in broadband wireless digital communication systems such as CDMA cellular systems, however it can also find utility in other digital cellular communication systems such as those made in accordance with the proposed Bluetooth standard.
Abstract
Description
- This is application is a divisional application of U.S. application Ser. No. 09/304,443, filed May 3, 1999, entitled “Method and Apparatus for Digitally Controlling the Capacitance of an Integrated Circuit Device Using MOS-Field Effect Transistors”, to issue on Apr. 3rd, 2001 as U.S. Pat. No.: 6,211,745.
- 1. Field of the Invention
- This invention relates to integrated circuit devices, and more particularly to a method and apparatus for digitally controlling the capacitance of integrated circuit components using MOS field effect transistors.
- 2. Description of Related Art
- One well-known problem to those skilled in the art of the design and manufacture of integrated circuits is the poor tolerance values associated with integrated circuit components, especially the tolerance values of passive circuit components. Due to process variations, device parameter spread, variations in critical parameters such as conductive layer sheet resistance values, film thickness, process uniformity and manufacturing equipment cleanliness, and other factors, integrated circuit passive electrical components often have tolerances that are approximately an order of magnitude worse than their analogous discrete external passive electrical components. Consequently, it has proven difficult and costly in the past to implement tuned networks or circuits using on-chip passive electrical components. One such tuned circuit is a voltage-controlled oscillator (VCO) in which a number of passive electrical devices are typically utilized to establish both the operating frequency and frequency offset of the VCO.
- One well-known solution to this tolerance problem is to “trim” the integrated circuit until it operates within a set of pre-defined post-fabrication parameters. These “post-fabrication trimming” techniques are performed after manufacturing and testing the integrated circuit and are designed to physically alter the integrated circuit using a variety of methods including “Zener-zapping”, laser trimming and fuse trimming. For example, using well-known fuse trimming techniques, fuseable links in an integrated circuit can be blown until the integrated circuit performs adequately under selected nominal conditions. Using these post-fabrication trimming techniques, passive electrical devices can be “fine-tuned” until they have acceptable tolerance values under nominal conditions. Disadvantageously, the trimming techniques produce only static solutions. For example, in fuse trimming, although the devices may perform adequately under nominal conditions, they may not perform adequately under all of the operating conditions of the integrated circuit. However, disadvantageously, the integrated circuit is permanently configured once the fuses are blown.
- For example, as the voltage and temperature of the integrated circuit varies over time, offsets can be introduced despite the static settings created during the fuse trimming process. Devices that were once usable under the nominal conditions at which the fuses were blown may become unusable under some operating conditions, thus adversely affecting yield characteristics of the integrated circuits. In addition, the prior art post-fabrication solutions disadvantageously introduce additional manufacturing and testing steps into the manufacturing process. Using these prior art approaches, the manufacturer must first measure performance characteristics, trim the integrated circuits to conform to a selected set of performance and tolerance criteria, and test the results to ensure that the integrated circuit is trimmed appropriately. Thus, the prior art post-fabrication trimming techniques add additional time to the design and fabrication of integrated circuit devices and consequently add to the manufacturing costs of the integrated circuits.
- Therefore, an improved method for improving the tolerances of passive electrical devices in an integrated circuit is needed which does not require the use of post-fabrication trimming techniques. Further, an improved method and apparatus is needed which dynamically monitors and corrects the performance characteristics of integrated circuits under all operating conditions. The improved method and apparatus should monitor and correct the performance characteristics of tuned networks especially as these performance characteristics are adversely affected by poor tolerances of on-chip passive electrical devices.
- FIG. 1 shows a prior art attempt at solving the problem of implementing tuned circuits using on-chip passive electrical devices having poor or unacceptable tolerance values. As shown in FIG. 1, using an integrated
switchable capacitor circuit 100, two terminals of an integrated tuned circuit (i.e.,terminal A 101 and terminal B 103) can be selectively coupled to a bank of switchably connected capacitors (C1 through Cn). Each of the capacitors is selectively coupled between theterminals capacitor C 1 102 is coupled between theterminals switch S 1 110. Similarly,capacitor C 2 104 is coupled between theterminals switch S 2 112. Finally,capacitor C n 108 is coupled between theterminals switch S n 116. Because the individual capacitors are connected in a parallel configuration, the total capacitance between theterminals terminals switchable capacitor circuit 100, the capacitors can be selectively switched in and out of the tuned circuit, thereby changing the capacitance between theterminals terminals A 101 andB 103. - Disadvantageously, this prior art approach is undesirable when the tuned circuit operates at relatively high frequencies. For example, when the tuned circuit operates in the GHz range of operating frequencies, the bank of switches (e.g.,110, 112, 114, and 116) introduce significant loss into the tuned circuit and thereby degrade the circuit's performance characteristics. The prior art solution shown in FIG. 1 also disadvantageously increases both the amount of space (i.e., integrated circuit real estate) and the amount of power required to accommodate and operate the switches. Power requirements are increased due to the D.C. current required to operate the bank of switches.
- Therefore, a need exists for a method and apparatus that can overcome the disadvantages associated with the prior art solutions and that will facilitate the integration of tuned capacitor networks on a single integrated circuit. The need exists for an apparatus that facilitates the full integration of a calibrated tuned capacitor network such as a voltage-controlled oscillator (VCO). In addition, the need exists for an apparatus and method that can dynamically calibrate an integrated tuned capacitor network such as a VCO. The present invention provides such a method and apparatus. The present method and apparatus uses a one-bit or “binary” capacitor formed from a MOSFET transistor that can be switched from a first pre-determined capacitance value to a second pre-determined capacitance value by varying an applied control voltage between first and second pre-determined voltage values. A multi-bit digital capacitor can be implemented by connecting a bank of the binary capacitors in parallel, and by weighting the individual capacitors as desired. The multi-bit digital capacitor allows capacitance values to be customized to any desired and convenient value.
- The present invention is a novel apparatus comprising a one-bit or “binary” capacitor formed from a MOSFET integrated device that can be switched from a first pre-determined capacitance value C1 to a second predetermined capacitance value C2 by varying an applied control voltage between a first and a second pre-determined voltage value. An inventive multi-bit digital capacitor is implemented by connecting a bank of the binary capacitors in parallel, and by weighting the individual capacitors in a desired fashion. The multi-bit digital capacitor allows capacitance values within an integrated circuit device to be customized to any desired and convenient value.
- The gate-to-bulk capacitance of the binary capacitor is dependent upon the D.C. voltage applied between the gate of the device and electrically coupled well contact implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region where there is little or no voltage dependency and where the capacitance equals a first low capacitance of C1; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C2. Simply changing the polarity of the applied D.C. voltage from a first value to a second value abruptly changes the capacitance of the binary capacitor from C1 to C2.
- In accordance with one aspect of the present invention, a plurality of binary capacitors is arranged in a parallel configuration to produce a digitally controlled capacitor. Advantageously, the digitally controlled capacitor can be used in any integrated circuit that requires a tightly controlled tuned network. One such application is a voltage-controlled oscillator (VCO). In accordance with one aspect of the present invention, the inventive digitally controlled capacitor is used in implementing a LC-resonator circuit, which is part of a fully integrated VCO device. The LC resonance frequency of the LC-resonator is varied by digitally modifying the capacitance of the LC tank circuit. The LC tank circuit is tuned with respect to an applied D.C. control voltage. Process variations introduced during the integrated circuit manufacturing process require that the LC-resonance frequency be re-centered after fabrication. In accordance with the present invention, the center output frequency of the VCO is calibrated by digitally modifying the capacitance of the VCO's digitally controlled capacitor. A means for determining whether the VCO requires calibration and a means for calibrating the center output frequency of the VCO is also presented.
- Consequently, the inventive VCO can be implemented in an integrated circuit design despite poor tolerance values typically associated with process variations in integrated circuit fabrication. The present invention advantageously increases the effectiveness of integrated circuit VCO designs, tuning networks, and the like. The present invention improves the performance of wireless communication devices without requiring the use of expensive and large discrete components. The present invention is particularly useful in broadband wireless digital communication systems such as CDMA cellular systems, however it can also find utility in other communication systems such as those made in accordance with the proposed Bluetooth standard.
- The details of the preferred and alternative embodiments of the present invention are set forth in the accompanying drawings and the description below. Once the details of the invention are known, numerous additional innovations and changes will become obvious to one skilled in the art.
- FIG. 1 is a prior art attempt at solving the problem of implementing tuned circuits using on-chip passive electrical devices having poor or unacceptable tolerance values.
- FIG. 2 shows a simplified cross-sectional view of a MOSFET structure configured for use as a “binary” capacitor in accordance with the present invention.
- FIG. 3 is a capacitance-voltage (CV) plot showing the dependency of the gate-to-bulk capacitance Cgate-bulk versus the D.C. bias voltage applied between the gate and the well of the binary capacitor shown in FIG. 2.
- FIG. 4a is a simplified schematic showing the binary capacitor of FIG. 2 configured for use as a digitally controlled multi-bit digital capacitor having a digitally selectable and variable capacitance.
- FIG. 4b is a simplified schematic representation of the digital capacitor of FIG. 4a.
- FIG. 5 is a plot showing how the capacitance of the multi-bit digital capacitor of FIG. 4a varies depending upon the digital control word CALword applied to the terminals of the plurality of binary capacitors shown in FIG. 4a.
- FIG. 6 shows a differential mode implementation of the digital capacitor of FIG. 4a.
- FIG. 7 is a schematic of a simple differential LC-oscillator circuit.
- FIG. 8 shows a modified version of the LC-resonator circuit of FIG. 7 wherein the digital capacitor of FIG. 4a is connected in a parallel arrangement with an analog tuning varactor and a fixed LC-tank circuit capacitor.
- FIG. 9 is a schematic of a calibrating voltage-controlled oscillator (VCO) made in accordance with the present invention.
- FIG. 10 is a simplified schematic of the calibrating VCO of FIG. 9 using a simplified schematic representation of the digital capacitor of the present invention.
- FIG. 11 is a simplified block diagram of a phase locked loop (PLL)
circuit 600 using the VCO of FIGS. 9 and 10. - FIG. 12 is a simplified block diagram demonstrating the principles of auto-calibration of the output center frequency of the inventive VCO of FIGS. 9 and 10.
- FIG. 13 shows a flowchart of one embodiment of a VCO center frequency auto-calibration method in accordance with the present invention.
- Like reference numbers and designations in the various drawings indicate like elements.
- Throughout this description, the preferred embodiment and examples shown should be considered as exemplars, rather than as limitations on the present invention.
- FIG. 2 shows a simplified cross-sectional view of a MOSFET structure configured for use as a “binary” capacitor in accordance with the present invention. As shown in FIG. 2, a
binary capacitor 200 made in accordance with the present invention preferably comprises an N-well (or “bulk”) 120, N+ well contactimplant regions contacts silicon P-gate 130. Using well-known MOSFET fabrication techniques, thebinary capacitor 200 of the present invention is preferably formed by lightly doping the N-well implant layer 120 (for a p-channel MOSFET device) with appropriate n-type dopant materials. The N+ well contactimplant regions well implant layer 120. The metal area of the P-gate 130, in conjunction with the insulating dielectric oxide layer and the semiconductor channel formed between the N+ well contactimplant regions contacts binary capacitor 200 varies depending upon the D.C. bias voltage applied between theP-gate terminal 134 and the wellcontact implant terminals - FIG. 3 shows the dependency of the gate-to-bulk capacitance Cgate-bulk upon the D.C. bias voltage that is applied between the
P-gate terminal 134 and the wellcontact implant terminals binary capacitor 200 of FIG. 2. As shown in the capacitance-voltage plot of FIG. 3, the gate-to-bulk capacitance Cgate-bulk varies between a first capacitance value CLOW and a second capacitance value CHIGH as the applied D.C. bias voltage is varied between a first threshold voltage V1 and a second voltage threshold V2. In this embodiment of the binary capacitor 200 (i.e., a P-gate/N-well embodiment), V1 and V2 are applied to theP-gate terminal 134 with positive polarities with respect to thewell contact terminals implant regions binary capacitor 200 is said to be operating in an “accumulation” mode in this embodiment. - Referring again to FIG. 3, by applying a D.C. bias voltage Vapplied that is equal to or less than V1 , Cgate-bulk (V)=CLOW. By applying a positive D.C. bias voltage Vapplied that is equal to or greater than V2, Cgate-bulk (V)=CHIGH. As the D.C. bias voltage varies between the threshold voltages V1 and V2, Cgate-bulk (V) follows the slope as shown in FIG. 3 and varies between the first capacitance value CLOW and the second capacitance value CHIGH (i.e., the
binary capacitor 200 behaves as a varactor in this relatively narrow voltage range). Thus, as shown, thebinary capacitor 200 of FIG. 2 has a first lower capacitance CLOW (that is flat over a relatively wide voltage range less than or equal to V1), a second higher capacitance CHIGH (that is flat over a relatively wide voltage range greater than or equal to V2), and a variable capacitance (variable between CLOW and CHIGH) in the relatively narrow range of voltages between V1 and V2. - In one preferred embodiment of the binary capacitor, the second capacitance value CHIGH is approximately two to three times greater than the first capacitance value CLOW. That is, CHIGH/CLOW is approximately equal to 2 or 3 in one preferred embodiment. Simply varying the device geometry and thereby making the physical size of the capacitor larger or smaller can vary the specific values of CLOW and CHIGH for any specific binary capacitor.
- By varying the D.C. bias voltage applied across the terminals (e.g., the
terminals binary capacitor 200 of FIG. 2, the capacitance value is varied between CLOW and CHIGH. If V1 represents a Boolean logic value of “zero”, and V2 represents a logical “one”, then the capacitance Cgate-bulk (V) can be digitally controlled using one control bit to be equal to either CLOW (when a logical zero is applied) or CHIGH (when a logical one is applied). Thus, the device shown in FIG. 2 is referred to as a “binary” capacitor because the capacitance of thedevice 200 can be digitally controlled to be equal to one of two states. Specifically, the digital control signal controls the difference or differential between CHIGH and CLOW (referred to hereinafter as the “differential capacitance”). That is CLSB (the differential capacitance of thebinary capacitor 200 as controlled by a least significant bit of a digital control word) is equal to CHIGH minus CLOW. - Although one embodiment of the binary capacitor of the binary capacitor is shown in FIG. 2, other alternative embodiments are possible. As described above, the
binary capacitor 200 may be implemented using a bulk CMOS process. Alternatively, the binary capacitor may be implemented as an integrated circuit varactor structure that includes a P-gate/N-well layer structure preferably formed on a Silicon-on-Insulator (“SOI”) substrate. In this embodiment of thebinary capacitor 200, the varactor structure is completely isolated from the substrate of the integrated circuit by an oxide layer of the SOI substrate, and by oxide-filled trenches formed on both sides of the varactor structure. The trenches preferably extend to the oxide layer of the SOI substrate. This alternative embodiment of thebinary capacitor 200 is described more fully in commonly assigned U.S. Pat. No. 6,172,378, entitled “Integrated Circuit Varactor having a Wide Capacitance Range,” issued on Jan. 9, 2001. This issued patent is incorporated by reference herein for its teachings of P-gate/N-well varactor structures. - In another preferred embodiment, the
binary capacitor 200 may be implemented as an integrated circuit varactor structure that includes an N-gate/P-well structure formed on either an N-substrate bulk CMOS substrate or an SOI CMOS substrate. The N-gate/P-well embodiment of the binary capacitor is identical to the P-gate/N-well structure of FIG. 2, with the exception that the N-gate/P-well structure uses p-type dopant materials in the place of the n-type dopant materials used in the N-well device. More specifically, and referring again to FIG. 2, in a P-well implementation of thebinary capacitor 200, thewell implant layer 120 is preferably lightly doped with appropriate p-type dopant materials. Similarly, thecontact implant regions well implant layer 120 in the preferred P-well implementation of thebinary capacitor 200 of FIG. 2. - The capacitance of the P-well
binary capacitor 200 is controlled by applying a D.C. bias voltage between theN-gate terminal 134 and the electrically coupled well contactterminals N-gate terminal 134 as negative polarity voltages with respect to the P-well contact terminals contact implant regions - As described above with reference to the N-well embodiment, by applying a negative polarity D.C. bias voltage Vapplied that is equal to or less than V1 (i.e., in this embodiment, equal to or more positive than V1), Cgate-bulk (V) CLOW. By applying a negative D.C. bias voltage Vapplied that is equal to or greater than V2 (i.e., in this embodiment, equal to or more negative than V2), Cgate-bulk (V)=CHIGH. As the D.C. bias voltage varies between the threshold voltages V1 and V2, Cgate-bulk (V) varies between the first capacitance value CLOW and the second capacitance value CHIGH (i.e., the
binary capacitor 200 behaves as a varactor in this relatively narrow voltage range). - Note that in this embodiment, the applied voltage Vapplied is increased to become more and more negative (e.g., from −0.5V to −1.5V) as it changes from the “low” threshold voltage of V1 to the “high” threshold voltage V2.
- The N-gate/P-well integrated circuit varactor structure formed on an SOI substrate is described more fully in the incorporated U.S. Pat. No. 6,172,378. This issued patent is incorporated by reference herein for its teachings of N-gate/P-well varactor structures.
- As described in more detail below with reference to FIGS.4-10, the present
binary capacitor 200 of FIG. 2 can be used as an integral building block in any integrated circuit that requires the use of passive components having improved tolerances. For example, thebinary capacitor 200 can be used to improve the performance of integrated circuit implementations of tuned capacitor networks such as voltage-controlled oscillators (VCO). Further, thebinary capacitor 200 of the present invention can be used to implement a means of calibrating (both manually and automatically) a tuned capacitor network such as a VCO. Although the presentbinary capacitor 200 is described below with reference to its use in an integrated circuit implementation of a VCO, this specific use is exemplary only and should not be interpreted as limiting the scope or application of the present invention. Those skilled in the integrated circuit design and fabrication art will recognize that thebinary capacitor 200 can be used to improve the performance of any integrated circuit requiring the use of passive electrical components. - FIG. 4a shows how the
binary capacitor 200 described above with reference to FIGS. 2 and 3 is used to create a digitally controlled or multi-bitdigital capacitor 300 having a digitally selectable and variable capacitance. As shown in FIG. 4a, a plurality of binary capacitors are preferably connected in parallel between two terminals (i.e., betweenterminal A 301 and terminal B 303) within an integrated circuit (not shown). The terminals A 301 andB 303 are analogous to the terminals A 101 andB 103 of FIG. 1 and, as described in more detail below, may be connected to a tuned circuit such as a VCO. In accordance with the present invention, the capacitance values of the binary capacitors are preferably weighted in a convenient and desirable manner. For example, in the embodiment shown in FIG. 4a, the binary capacitors of the multi-bitdigital capacitor 106 are given binary weighting. More specifically, the least-significantbinary capacitor C 1 302 is manufactured to have a desired least significant (or lowest) differential capacitance of CLSB (defined as the difference between C1's highest capacitance C1 HIGH and C1's lowest capacitance C1 LOW). - The next significant
binary capacitor C 2 304 is preferably manufactured to have a differential capacitance of twice CLSB, or 2*CLSB. The binary weighting is assigned in like fashion with each next significant capacitor having a differential capacitance that is a power of two greater than the previous significant capacitor. Finally, the most significantbinary capacitor C n 306 is manufactured to have a differential capacitance of 2n-1*CLSB. Those skilled in the IC manufacturing art will appreciate that several alternative means may be used to make the differential capacitance of a selected binary capacitor (for example, C2) have a value that is a power of two greater than the previous significant capacitor (in this example, C1). For example, in one embodiment, the selected capacitor (e.g., C2) can be formed by placing two previous significant capacitors (in this example, C1) in parallel. Similarly, the next significant capacitor (e.g., C3) can be formed by placing four of the previous significant capacitors (e.g., C1) in parallel. Alternatively, the capacitors may be manufactured to different physical dimensions to have the desired differential capacitance characteristics. - In addition, although the binary capacitors of the embodiment shown in FIG. 4a are given a binary weighting, those skilled in the art will recognize that any convenient capacitance-weighting scheme can be assigned to the capacitors. For example, in an alternative embodiment where a logarithmic scaling is desired, each binary capacitor can be manufactured to have a capacitance value that is ten times greater than its previous significant capacitor. More specifically,
binary capacitor C 2 304 can be manufactured to have a differential capacitance that is 10*CLSB, whereC 1 302 is manufactured to have a differential capacitance of CLSB. In this embodiment, Cn is assigned a differential capacitance of 10n-1*CLSB. - Referring again to FIG. 4a, the differential capacitance of each binary capacitor of the
digital capacitor 106 is individually controlled by an associated and respective digital control signal that is applied over the terminals of the associated binary capacitor (i.e., by an associated and respective digital bit of a digital control word applied between the respective gate and well contact terminals). The control bits are ordered from least significant bit (LSB) to most significant bit (MSB), and are assigned to control the least significant capacitor to the most significant capacitor. Accordingly, the binary capacitors are ordered from least significant to most significant. For example, as shown in FIG. 4a, the least significant bit LSB, B1 of the digital control word is preferably applied over the terminals of the least significantbinary capacitor C 1 302 and thereby controls the capacitance of thebinary capacitor C 1 302. The next most significant bit, B2, is applied to the terminals of the binary capacitor C2 and thereby controls its capacitance. The most significant bit, Bn, similarly controls the capacitance of binary capacitor Cn. - As described above with reference to FIGS. 2 and 3, when B1, for example, is a logical low value, or D.C. for example, the capacitance of
binary capacitor C 1 302 is equal to a first lower capacitance C1 LOW. Alternatively, when B1 is a logical high value, or Vcc for example, the capacitance of thebinary capacitor C 1 302 is equal to a second higher capacitance C1 HIGH. The differential between C1 HIGH and C1 LOW is equal to CLSB. Similarly, when B2, for example, is a logical low value, or D.C., the capacitance of C2 is equal to C2 LOW. When B2 is a logical high value, or Vcc, the capacitance of binary capacitor C2 is equal to C2 HIGH. Due to the binary weighting of C2, the differential capacitance of C2 (i.e., the difference between C2 HIGH and C2 LOW) is equal to 2*CLSB. The trend continues as such, with each next significant binary capacitor having a differential capacitance that is twice the differential capacitance of its previous significant capacitor. Finally, as shown in FIG. 4a, the capacitance ofbinary capacitor C n 306 varies between Cn LOW and Cn HIGH, as Bn varies between a logic low and logic high value. Again, due to the binary weighting of the capacitors the differential capacitance between Cn HIGH and Cn LOW is approximately equal to 2n-1*CLSB. - Because the plurality of binary capacitors are connected together in a parallel configuration as shown in FIG. 4a, their respective capacitance values combine by simply adding the capacitance values of all of the individual binary capacitors. The capacitance of the digital capacitor 106 (as measured between the terminals A 301 and B 303) is therefore equal to the sum of the capacitance of each of the binary capacitors Cn. FIG. 4b is a simplified schematic representation of the
digital capacitor 106 shown in FIG. 4a. - FIG. 5 shows a plot of the capacitance of the
digital capacitor 106 as it varies depending upon the digitalcontrol word CAL word 114 applied over the terminals of the plurality of binary capacitors. In the example shown, CALword is assumed to be three bits wide and therefore, in this embodiment, the number of binary capacitors used to implement thedigital capacitor 106 is three. As shown in FIG. 5, the lowest capacitance value CFLOOR is produced when thecontrol word CAL word 114 is set equal to all zeros (e.g., assuming a three-bit control word, n=3, CALword=000). Here, CFLOOR=C1 LOW+C2 LOW+C3 LOW. The next higher capacitance value is produced using a control word CALword of “001”. In this case, the capacitance of thedigital capacitor 106 is equal to C1 HIGH+C2 LOW+C3 LOW, or CFLOOR+CLSB. By increasing the value of CALword by one to “010”, the capacitance of thedigital capacitor 106 is increased to the next step to a value of C1 LOW+C2 HIGH+C3 LOW, or CFLOOR+(2*CLSB). The digital control word CALword can be similarly incremented to produce the capacitance plot shown in FIG. 5. The capacitance of thedigital capacitor 106 has its highest capacitance CMAX equal to C1 HIGH+C2 HIGH+C3 HIGH when the digital control word CALword is set equal to “111”. Stated in other terms, the highest capacitance CMAX of the digital capacitor is CFLOOR +(7*CLSB). - FIG. 6 shows a differential mode implementation of the
digital capacitor 106 described above with reference to FIGS. 1-5. Thedigital capacitor 106 is preferably implemented differentially because this provides a convenient third terminal for digitally controlling the capacitance values of the binary capacitors. For example, as shown in FIG. 6, the control signal B1 is applied between thebinary capacitors C control terminal 310. Similarly, the control signal B2 is applied between thebinary capacitors C control terminal 312. The most significant control bit of the digitalcontrol word CAL word 114, Bn, is applied between the binary capacitors Cn, 306, 306′ at acontrol terminal 314. The control terminals are common mode AC grounds. - The differential mode implementation of the
digital capacitor 106 functions similarly to thedigital capacitor 106 described above with reference to FIGS. 4-5. For example, the binary capacitors are preferably assigned a binary weighting, with the leastsignificant capacitors C binary capacitors control terminal 310 by the LSB of the digital control word CALword, i.e., by B1. The differential capacitance of the next significantbinary capacitors C - The capacitance of the
binary capacitors C control terminal 312 by the next most significant bit of the digital control word CALword, i.e., by B2. The width of the control word CALword corresponds to the number of binary capacitor pairs used in the differential mode implementation of thedigital capacitor 106. The differential capacitance of the most significant binary capacitors is equal to (2n-1*CLSB). The MSB of the control word, i.e., Bn, controls the differential capacitance of thebinary capacitors C digital capacitor 106 is as follows: - C total =C FLOOR +B 1 ′C LSB +B 2′(2*C LSB)+B 3′(4*C LSB)+ . . . +B n′* (2n-1 C LSB);
- where the control word bits Bn′ determine whether the differential capacitance of the nth capacitor (CLSB or a multiple of CLSB in the case when n is higher than 2) is or is not added to CFLOOR. More specifically, if Bn′ is a logical zero, the differential capacitance of the nth capacitor is not added (i.e., CLSB, or its multiple, is not added to CFLOOR for the nth capacitor). If Bn′ is a logical one, then the differential capacitance of CLSB (or its multiple in the case of higher order bits) is added to CFLOOR for the nth capacitor.
- Thus, by varying the value of the digital
control word CAL word 114 appropriately, and thereby varying the capacitance of each individual binary capacitor (i.e.,binary capacitor C 1 302,C 2 304, . . . Cn 306), the capacitance of thedigital capacitor 106 can be customized to any desired value. The step size shown in FIG. 5 (i.e., the resolution of the capacitance of the digital capacitor 106) depends upon the CLSB of the capacitors. When the multi-bitdigital capacitor 300 is used in implementing a tuned capacitor in an integrated circuit, the capacitance can be digitally calibrated as desired to meet pre-defined operational parameters. - Applications of the Multi-bit Digital Capacitor in an Integrated Circuit
- The
digital capacitor 300 of FIG. 4a and 300′ of FIG. 6 can be used in place of the switched-capacitor circuit 100 of FIG. 1 to provide a calibrated capacitor for use in virtually any integrated circuit implementation of a tuned capacitor network. For example, consider the simple differential LC-oscillator circuit 400 shown in FIG. 7. The differential LC-oscillator 400 comprises an LC-resonator circuit 402, anamplifier 404, and acurrent source 405. As is well known in the electrical engineering art, the resonance frequency of the LC-resonator 402 defines the frequency of oscillation, or the center frequency, of the LC-oscillator 400 and is determined by the values of L and C. More specifically, the oscillation frequency, fo=1/(2π*SQRT(L*Ctot)). - Disadvantageously, if any of the integrated circuit components used to implement the LC-
resonator 402 have poor tolerance values due to process variations or other factors, the oscillation frequency fo will be adversely affected. This is particularly disadvantageous when the oscillation frequency is relatively high, for example, when the oscillation frequency operates in the Gigahertz range. At such high frequencies, the tolerance variations of the passive electrical components will dramatically affect variations in the oscillation frequency. For example, with a desired oscillation frequency of 2 GHz, a ±10% tolerance will yield an oscillation frequency of 2 GHz±200 MHz. This may be unacceptable in some applications. In addition, in order to obtain desired performance characteristics such as low phase noise and low power dissipation, the components of the LC-oscillator 400 (i.e., the L and C components) should have low series losses (i.e., the components should have high “Q” gain values). - A modified
version 402′ of the LC-resonator 402 of FIG. 7 is shown in FIG. 8. Thedigital capacitor C CAL 300 described above with reference to FIGS. 4a and 4 b is connected in a parallel arrangement with ananalog tuning varactor 406 and a fixed LC-tankcircuit capacitor C L 408 as shown. As described above with reference to the LC-oscillator 400 of FIG. 7, the resonance frequency of the LC-resonator 402′ of FIG. 8 is determined by the values of L and Ctotal. More specifically, the oscillation frequency, fo=1/(2π*SQRT(L*Ctotal)). The value of L remains fixed. Because thedigital capacitor 300, thetuning varactor 406, and the fixedcapacitor C L 408 are connected in parallel, their capacitance values add together to yield a total capacitance Ctotal of the LC-resonator 402. That is, Ctotal=CCAL+Ctune+CL. - The
capacitance C L 408 is a fixed and known pre-determined value. The capacitance Ctune is determined by applying a D.C.control voltage V tune 410 to thetuning varactor 406. In practice, Ctune is tuned so that the oscillation frequency fo is nominally equal to a desired center frequency, for example, 2 GHz. However, as described above, in order to compensate for fabrication process variations and other factors, the resonance or oscillation frequency fo may require calibration in order to re-center the LC-resonance frequency to a desired center frequency value. Thedigital capacitor C CAL 300 is used for this purpose. By applying an appropriate digitalcontrol word CAL word 412 to thedigital capacitor 300, the capacitance of the digital capacitor is changed to a desired value, and the center frequency of the LC-resonator 402′ is thereby changed accordingly. The oscillation frequency fo is therefore calibrated and re-centered by appropriately adjusting the digital control word CALword. Calibration of the LC-resonator 402′ oscillation frequency fo can be performed using either manual or automatic methods of calibration. - For example, in one embodiment, the LC-
resonator 402′ is manually calibrated by first measuring the oscillation frequency fo during a production testing phase of the integrated circuit fabrication process. In this embodiment, the circuit is tuned to a desired oscillation frequency and the actual output frequency is measured. If the desired oscillation frequency differs from the measured output frequency the digital control word CALword is modified until the output frequency equals the desired oscillation frequency. The calibration control word thereby determined for CALword may then be stored in a non-volatile memory either within the same integrated circuit as the resonator or on a printed circuit board adjacent the integrated circuit. In another embodiment, the oscillation frequency fo is automatically calibrated until a desired oscillation frequency is obtained. - Such an automatic calibration method may be executed every time the circuit is powered on. In one preferred embodiment, the automatic calibration method is executed by a microprocessor or other data processing device located within the integrated circuit or on the same printed circuit board as the integrated circuit. Alternatively, the method can be implemented using any convenient or desirable sequencing device such as a state machine, present state-next state discrete logic, or field programmable gate array device. A more detailed description of the auto-calibration method is described in more detail below together with a description of a self-calibrating VCO made in accordance with the present invention.
- Use of the Digital Capacitor in Implementing a VCO in an Integrated Circuit
- FIG. 9 shows a schematic of a voltage-controlled oscillator (VCO) made in accordance with the present invention. The
VCO 500 shown in FIG. 9 uses both the differential mode implementation of thedigital capacitor 300′ of FIG. 6 and a differential mode implementation of the LC-resonator 402″ of FIG. 8 to produce a VCO that can be calibrated to generate a desired output frequency fo based upon a given control voltage and given digital control word. As shown in FIG. 9, one preferred embodiment of the calibratingVCO 500 of the present invention comprises twoinductors L digital capacitor 300′ described in more detail above with reference to FIG. 6, anamplifier 404′, and acurrent source 405. Theamplifier 404′ functions similarly to theamplifier 404 of FIG. 7. Similarly, the binary capacitors (e.g., the LSBbinary capacitor C binary capacitor C binary capacitor C - In the VCO of FIG. 9, the capacitance of the binary capacitors are controlled by a digital control word (comprising VC1 (LSB), VC2, VC3, and VC4 (MSB)) that is buffered by associated and
corresponding buffers 506. FIG. 10 is a simplified schematic of the calibratingVCO 500 of FIG. 9 using the simplified schematic representation of thedigital capacitor 300′. Similar to the operation of the LC-resonator 402′ of FIG. 8, the oscillation or output frequency fo of theVCO 500 is established by appropriately adjusting the analogtuning voltage V tune 410 to a desired D.C. voltage level. Fabrication process variations can be compensated and the oscillation frequency fo can be calibrated and re-centered by thereafter varying the digital control word CALword and thereby adjusting the capacitance of thedigital capacitor 300′. Advantageously, despite process variations in the fabrication of integrated circuits, theinventive VCO 500 of FIGS. 9 and 10 allows circuit designers to accurately control the center frequency of the integrated circuit VCO. This is essential in some applications, especially when the VCO operates at relatively high frequencies. - In addition, given a set of tunable frequency ranges, the present invention provides a VCO having much lower gain and sensitivity characteristics than prior art VCO designs. Owing to the calibration function provided by the
digital capacitor 300′, the calibratingVCO 500 need be tunable only over a relatively narrow frequency range (i.e., the VCO only has to cover the frequency band of interest) as compared with the prior art VCO designs. Therefore, the presentinventive VCO 500 is much less sensitive to noise than are the prior art VCO designs. Thepresent VCO 500 performs better and is easier to implement that its prior art counterparts because it is less sensitive to low frequency noise and the deleterious effects of interfering RF signals. - FIG. 11 is a simplified block diagram of a phase locked loop (PLL)
circuit 600 that uses theVCO 500 described above with reference to FIGS. 9 and 10. As shown in FIG. 11 the preferred embodiment of thePLL 600 comprises a multiplier orphase error detector 602, aloop filter 604, theVCO 500, and a divide-by-M circuit 606. ThePLL 600 functions in a well-known manner to generate an output frequency fo that is locked in phase with a precision reference signal fr. ThePLL 600 is a negative feedback system. The reference signal fr and the output of the divide-by-M circuit 606 are applied to the inputs of themultiplier 602 as shown in FIG. 11. Themultiplier 602 produces both a high frequency and a low-frequency component. - The high frequency component is eliminated by the combination of the
loop filter 604 and theVCO 500. The low frequency component output by themultiplier 602 contains information related to the phase error or difference in phase between the reference signal fr and the divided down output signal fo (i.e., the output of theVCO 500 as divided-down by the divide-by-M circuit 606). This phase error signal is filtered and used (as the tuning voltage Vtune) to control the frequency produced by theVCO 500. The output signal generated by theVCO 500 is fed back to the divide-by-M circuit 606 thereby closing the PLL negative feedback loop. - When the phase error produced at the output of the
multiplier 602 is zero, thePLL 600 is in a phase-lock condition. The VCO output signal fo is a multiple of the reference signal fr, specifically fo=M*fr. Due to the negative feedback operation of thePLL 600 described above, the output signal fo tracks or follows the reference signal fr. In the embodiment shown in FIG. 11, the reference frequency fr is maintained at a desirable base frequency, while the output center frequency fo is varied by varying the value of “M” in the divide-by-M circuit 606 (i.e., M can be assigned the values of M1, M2, M3, etc., with each M-value having an associated and corresponding output center frequency fo1, fo2, fo3, etc.). - When the
VCO 500 is used in a radio communication system designed in accordance with the proposed “Bluetooth” standard, theVCO 500 must be capable of generating output signals having a frequency range of at least 78 MHz (i.e., the tunable range of the VCO must be at least 78 MHz), starting at 2.402 GHz and stopping at 2.48 GHz. Spectrum spreading in Bluetooth is accomplished in 79 frequency channel hops displaced by 1 MHz per frequency channel. TheVCO 500 must therefore be capable of generating output signals corresponding to the transmit and receive frequency channels used in Bluetooth. However, it is desirable to reduce the gain of the VCO in order to reduce sensitivity to low-frequency noise signals. In one embodiment, the gain of theVCO 500 is approximately 50 MHz and the maximum tunable range of theVCO 500 is 300 MHz. In this embodiment, fr is maintained at a base frequency of approximately 1 MHz. By changing the value of M in the divide-by-M circuit 606, theVCO 500 generates multiple output channels separated by the 1 MHz reference frequency. More specifically, in an embodiment designed for use in a Bluetooth system, the output frequency varies between 2.402 GHz and 2.48 GHz at a 1 MHz channel spacing. - However, those skilled in the art will recognize that the
VCO 500 of the present invention can be modified for use in a wide variety of applications without departing from the scope of the claims. For example, the tuning range and the output frequency channels generated by theinventive VCO 500 can be modified for use in a wideband communication system simply by changing the reference frequency, the value of M in the divide-by-M circuit 606, and the value of CALword. In one wideband communication system contemplated for use with the presentinventive VCO 500, the VCO tuning range is approximately 300 MHz and the frequency channels are separated by approximately 16 MHz-wide steps. Theinventive VCO 500 can also be used in applications such as use in implementing tunable filters. - Automatic Calibration of the VCO Center Frequency fo
- In one embodiment of the present invention, the output center frequency fo generated by the
VCO 500 is automatically calibrated to fall approximately in the center of the VCO tuning range (i.e., centered between the minimum and maximum values of the tuning voltage Vtune that is applied to the control input of the VCO 500). FIG. 12 shows a simplified block diagram that demonstrates the principles of auto-calibration of the VCO center frequency. As shown in FIG. 12, theVCO 500 generates an output frequency fo that is input to the phase lockedloop circuit 600 described above with reference to FIG. 11. ThePLL 600 performs a frequency-to-voltage conversion function whereby the output frequency fo is compared with a reference frequency fr to generate the tuning voltage Vtune. The tuning voltage Vtune is subsequently compared by acomparator 702 with a reference or threshold voltage Vref as shown in FIG. 12. The total capacitance of the LC-resonator circuit (FIG. 8) within theVCO 500 is modified based upon the comparison of the tuning voltage Vtune with the reference or threshold voltage Vref. This voltage-to-capacitance function is performed by thedigital capacitor circuit 300, and specifically by updating the digital control word CALword. Thus, by periodically monitoring the input tuning voltage Vtune, and by comparing the tuning voltage to a threshold voltage, the VCO output center frequency can be automatically calibrated. - FIG. 13 shows a flowchart of one embodiment of a VCO center frequency auto-
calibration method 800 in accordance with the present invention. In one embodiment of the present invention, themethod 800 shown in FIG. 13 is implemented in software instructions that are executed by a micro-processor, state machine, or other digital logic device operatively coupled to theinventive VCO 500. However, those skilled in the digital control art will recognize that themethod 800 may also be implemented in hardware, or by use of discrete logic circuits. As shown in FIG. 13, the VCO auto-calibration method 800 is initiated atSTEP 801 when theVCO 500 is first powered on (i.e., after theVCO 500 enters a “powerup” state). Themethod 800 proceeds to aSTEP 802 whereat the digital control word CALword is initialized to a pre-determined value. In the embodiment shown in FIG. 13, CALword is initialized to a value that is halfway between its maximum number (binary “1111”) and its minimum number (binary “0000”), that is, CALword is set to a binary “1000”. The inventive VCO auto-calibration method 800 then proceeds to a waitingSTEP 804 whereat the method waits for a pre-determined “settling” period of time. - The method waits for the pre-determined “settling” period (shown as a scaling factor X1 multiplied by a settling time Tsettle) in order to allow the
VCO 500 and the PLL 600 (FIG. 11) to settle after the powerup condition and to thereafter establish a nominal output frequency. The settling time can be determined experimentally and adjusted to meet the needs of specific VCO designs. In the embodiment shown in FIG. 13, after waiting the pre-determined settling period, themethod 800 proceeds to aSTEP 806 whereat a decision is made as to whether the radio system utilizing theVCO 500 is operating within a receive or transmit time slot. One preferred application for the presentinventive VCO 500 is use in a frequency hop transceiver capable of generating receive and transmit frequencies in a wireless Time-Division Duplex scheme. One exemplary application of theinventive VCO 500 is in a radio system designed according to the proposed Bluetooth standard. When theVCO 500 is used in such a system themethod 800 preferably prevents calibration of the VCO during the time slots that voice/data is being received or transmitted (i.e., during the Rx and Tx time slots). Accordingly, as shown in FIG. 13, if the VCO is currently operating in a receive/transmit time slot, thedecision STEP 806 “yes” output will be followed and theVCO 500 will not be calibrated. Themethod 800 will continue to loop back to thedecision STEP 806 until the VCO is no longer operating in a receive/transmit time slot. - When the receive/transmit time slot is no longer active, the method proceeds to a
decision STEP 808 and determines whether a “channel jump” or “channel hop” condition exits. In a communication system designed according to the proposed Bluetooth standard as described above, certain time slots are dedicated for frequency or channel “hopping.” Consequently, when the inventive auto-calibration method 800 determines that a channel hop has occurred in theSTEP 808, and that the channel frequency change or channel hop delta is greater than a pre-determined threshold, the method preferably proceeds to aSTEP 810 and updates the digital control word CALword to reflect the corresponding change in output frequency. More specifically, in the embodiment shown in FIG. 13, a determination is made at thedecision STEP 808 as to whether the channel frequency was increased or decreased by a factor of n*LSB; wherein n is an integer and “LSB” is a pre-defined frequency resolution determined by the least significant bit of the digital control word CALword. - For example, in one embodiment of the present invention, one LSB of the digital control word CALword changes the
VCO 500 output frequency fo by 30 MHz. In such an embodiment, if the channel jump detected inSTEP 808 is greater than or equal to 30 MHz (i.e., greater than plus orminus 1 LSB), then CALword is updated accordingly atSTEP 810 to change the center frequency of theVCO 500. Similarly, if the channel jump is greater than 60 MHz (i.e., greater than plus orminus 2 LSB), the CALword is updated inSTEP 810 to change the center frequency fo of the VCO by 60 MHz. Those skilled in the VCO art will appreciate that theSTEPS method 800 of FIG. 13 proceeds directly from the waitingSTEP 804 to adecision STEP 812. - The remainder of the inventive VCO auto-calibration method monitors the VCO analog tuning voltage Vtune and determines whether the VCO output frequency fo requires calibration. For example, at the
decision STEP 812, the method determines whether the analog tuning voltage Vtune is less than a pre-determined Vout “low threshold” value “VoutL.” In some situations, especially when theVCO 500 is first powered on, thePLL 600 can become locked into a condition wherein the output frequency fo is saturated to a given high frequency, and the analog tuning voltage becomes locked below a low threshold voltage of VoutL. In this scenario, the method will modify the digital control word CALword and thereby decrease the output frequency fo generated by theVCO 500. The method will increase the digital control word CALword to thereby decrease the output frequency, which, due to the negative feedback of thePLL 600, will, in turn, increase the analog tuning voltage Vtune. - If the method determines at
STEP 812 that the analog tuning voltage Vtune is greater than the low threshold value VoutL, then the method proceeds to adecision STEP 822 whereat it determines whether the analog tuning voltage Vtune is greater than a pre-determined Vout “high threshold” value “VoutH.” As described above, in some situations, especially when theVCO 500 is first powered on, thePLL 600 can become locked into a condition wherein the output frequency fo is saturated to a given low frequency, and the analog tuning voltage becomes locked above a high threshold voltage VoutH. In this scenario, the method will modify the digital control word CALword and thereby modify the output frequency fo generated by theVCO 500. The method will decrease the digital control word CALword and thereby increase the output frequency, which, due to the negative feedback of thePLL 600, will decrease the analog tuning voltage Vtune. The remainder of themethod 800 is now described in more detail. - If a determination is made at the
decision STEP 812 that Vtune is less than the pre-determined low threshold voltage VoutL (i.e., the outcome of the decision step is “yes”), the method proceeds to a waitingSTEP 814 and waits for a pre-determined period of time for the output frequency of the VCO to settle. For example, as shown in FIG. 13, at theSTEP 814 the method waits for a time period equal to a scaling factor “X2” multiplied by a pre-defined settling time Tsettle to allow theVCO 500 to settle. In one embodiment of the present invention, the waiting time provided bySTEP 814 is approximately 100 microseconds. However, those skilled in the VCO design art shall recognize that both the scaling factor X2 and the settling time Tsettle can be modified to accommodate various VCO designs without departing from the scope of the present invention. - The
method 800 waits during the waitingSTEP 814 to determine whether the tuning voltage Vtune is still less than the low threshold voltage VoutL, and therefore whether the VCO still requires calibration. The method proceeds from theSTEP 814 to adecision STEP 816 to determine whether the analog tuning voltage Vtune is greater than the pre-defined high threshold VoutH. If Vtune is greater than VoutH, the method returns to theSTEP 806 and proceeds as described above. However, if Vtune is less than VoutH the method proceeds todecision STEP 818 to once again determine if the analog tuning voltage Vtune is less than the low threshold VoutL. If not, there is no reason to calibrate theVCO 500, and the method returns to theSTEP 806 and proceeds as described above. However, if Vtune is still less than the low threshold voltage VoutL, the method proceeds to theSTEP 820 to calibrate theVCO 500. As shown in FIG. 13, calibration of theVCO 500 is preferably accomplished by modifying the digital control word CALword. In this case, calibration is accomplished by increasing CALword by one bit (i.e., CALword<−CALword+1). Increasing CALword by one bit causes the VCO output frequency to decrease, which, due to the negative-feedback operation of thePLL 600, causes the tuning voltage Vtune to increase. The method then returns to theSTEP 806 to determine whether further calibration is required. - The right side of the flowchart shown in FIG. 13 operates in a similar manner to decrease CALword when the analog tuning voltage Vtune is determined to be greater than a pre-defined high threshold voltage VoutH. Specifically, the
method 800 waits during aSTEP 824 to determine whether the tuning voltage Vtune is still greater than the high threshold voltage VoutH, and therefore whether the VCO still requires calibration. The method proceeds from theSTEP 824 to adecision STEP 826 to determine whether the analog tuning voltage Vtune is less than the pre-defined low threshold VoutL. If Vtune is less than VoutL, the method returns to STEP 806 and proceeds as described above. However, if Vtune is greater than VoutL, the method proceeds to adecision STEP 828 to once again determine if the analog tuning voltage Vtune is greater than the high threshold voltage VoutH. If not, there is no reason to calibrate theVCO 500, and the method returns to theSTEP 806 and proceeds as described above. However, if Vtune is still greater than the high threshold voltage VoutH, the method proceeds to theSTEP 830 to calibrate theVCO 500. As described above, calibration of theVCO 500 is accomplished by modifying the digital control word CALword. In this case, calibration is accomplished by decreasing CALword by one bit (i.e., CALword<−CALword−1). Decreasing CALword by one bit causes the VCO output frequency to increase, which, due to the negative-feedback operation of thePLL 600, causes the tuning voltage Vtune to decrease. The method then returns to theSTEP 806 to determine whether further calibration is required. - In summary, the invention includes a digital or binary capacitor comprised of a MOSFET device wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to the D.C. voltage applied between its gate and well implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region where there is little or no voltage dependency and where the capacitance equals a first low capacitance of C1; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C2. The capacitance of the binary capacitor can be changed from C1 to C2 simply by changing the polarity of the applied D.C. voltage from a positive to a negative value.
- A plurality of binary capacitors are configured in a parallel arrangement to produce a digitally-controlled capacitor. The digitally-controlled capacitor can be used in any integrated circuit requiring a tightly controlled tuned network. One application is a voltage-controlled oscillator (VCO) wherein the center output frequency of the VCO is calibrated by digitally modifying the capacitance of the VCO's digitally controlled capacitor. A means for determining whether the VCO requires calibration and a means for calibrating the center output frequency of the VCO is presented. Consequently, the inventive VCO can be implemented in an integrated circuit design despite poor tolerance values typically associated with process variations in integrated circuit fabrication. The present invention advantageously increases the effectiveness of integrated circuit VCO designs, tuning networks, and the like. The present invention improves the performance of wireless communication devices without requiring the use of expensive and large discrete components. The present invention is particularly useful in broadband wireless digital communication systems such as CDMA cellular systems, however it can also find utility in other digital cellular communication systems such as those made in accordance with the proposed Bluetooth standard.
- A number of embodiments of the present invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the claimed invention.
- Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiment, but only by the scope of the appended claims.
Claims (24)
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US09/824,277 US6323736B2 (en) | 1999-05-03 | 2001-04-02 | Method and apparatus for calibrating a frequency adjustable oscillator in an integrated circuit device |
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US09/304,443 US6211745B1 (en) | 1999-05-03 | 1999-05-03 | Method and apparatus for digitally controlling the capacitance of an integrated circuit device using mos-field effect transistors |
US09/824,277 US6323736B2 (en) | 1999-05-03 | 2001-04-02 | Method and apparatus for calibrating a frequency adjustable oscillator in an integrated circuit device |
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US09/824,277 Expired - Lifetime US6323736B2 (en) | 1999-05-03 | 2001-04-02 | Method and apparatus for calibrating a frequency adjustable oscillator in an integrated circuit device |
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Also Published As
Publication number | Publication date |
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WO2000067325A8 (en) | 2001-05-25 |
US6211745B1 (en) | 2001-04-03 |
WO2000067325A1 (en) | 2000-11-09 |
AU5267200A (en) | 2000-11-17 |
US6323736B2 (en) | 2001-11-27 |
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