CN105575885A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN105575885A
CN105575885A CN201410541924.2A CN201410541924A CN105575885A CN 105575885 A CN105575885 A CN 105575885A CN 201410541924 A CN201410541924 A CN 201410541924A CN 105575885 A CN105575885 A CN 105575885A
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layer
stop
dielectric layer
contact plunger
grid structure
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CN105575885B (zh
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洪庆文
黄志森
陈意维
林建廷
邹世芳
吕佳霖
陈俊隆
廖琨垣
张峰溢
陈界得
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。其制作方法包括：首先提供一基底，然后形成多个栅极结构于基底上，形成一第一停止层于栅极结构上，形成一第二停止层于第一停止层上，形成一第一介电层于第二停止层上，形成多个第一开口于第一介电层中并暴露第二停止层，形成多个第二开口于第一介电层及第二停止层中并暴露第一停止层以及去除部分第二停止层及部分第一停止层以暴露出栅极结构。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种利用四道光刻暨蚀刻制作工艺于介电层中形成开口的方法。
背景技术
近年来，随着场效晶体管(fieldeffecttransistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(finfieldeffecttransistor,FinFET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininducedbarrierlowering,DIBL)效应，并可以抑制短通道效应(shortchanneleffect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(thresholdvoltage)也可通过调整栅极的功函数而加以调控。
然而，在现有的鳍状场效晶体管元件制作工艺中，结合金属栅极与接触插塞等元件的制作工艺时仍因光学的限制遇到一些瓶颈，例如所形成的接触插塞常因所设置的位置不佳而直接贯穿金属栅极，影响元件的整体电性表现。因此如何改良现有鳍状场效晶体管制作工艺与架构即为现今一重要课题。
发明内容
为解决上述问题，本发明优选实施例公开一种制作半导体元件的方法。首先提供一基底，然后形成多个栅极结构于基底上，形成一第一停止层于栅极结构上，形成一第二停止层于第一停止层上，形成一第一介电层于第二停止层上，形成多个第一开口于第一介电层中并暴露第二停止层，形成多个第二开口于第一介电层及第二停止层中并暴露第一停止层以及去除部分第二停止层及部分第一停止层以暴露出栅极结构。
本发明另一实施例公开一种半导体元件，包含一基底、多个栅极结构设于基底上、一层间介电层环绕栅极结构、一第一停止层设于层间介电层及栅极结构上、一第一介电层设于第一停止层上、一第二停止层设于第一介电层上、一第二介电层设于第二停止层上、多个第一接触插塞设于层间介电层、第一停止层及第一介电层中并电连接至基底中的一源极/漏极区域、多个第二接触插塞设于第二停止层及第二介电层中并电连接至第一接触插塞以及多个第三接触插塞设于第一停止层、第一介电层、第二停止层及第二介电层中并电连接至栅极结构。
附图说明
图1至图4为本发明第一实施例制作一半导体元件的方法示意图；
图5至图8为本发明另一实施例制作半导体元件的方法示意图；
图9至图12为本发明另一实施例制作半导体元件的方法示意图。
主要元件符号说明
12基底14鳍状结构
16浅沟隔离18金属栅极
20金属栅极
24间隙壁26源极/漏极区域
28外延层30接触洞蚀刻停止层
32层间介电层34功函数金属层
36低阻抗金属层38停止层
40介电层42图案化硬掩模
44开口46接触洞
48接触插塞
52介电层54接触插塞
56停止层58介电层
60有机介电层62含硅硬掩模及抗反射层
64图案化光致抗蚀剂66开口
68开口70开口
72开口74接触插塞
82停止层84介电层
86接触插塞88停止层
90介电层92ODL
94SHB层96图案化光致抗蚀剂
98开口100开口
102开口104开口
106接触插塞108接触插塞
具体实施方式
请参照图1至图4，图1至图4为本发明第一实施例制作一半导体元件的方法示意图，其可实施于平面型或非平面型晶体管元件制作工艺，现以应用于非平面型晶体管元件制作工艺为例。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，其上定义有一晶体管区，例如一PMOS晶体管区或一NMOS晶体管区。基底12上具有至少一鳍状结构14及一绝缘层，其中鳍状结构14的底部被绝缘层，例如氧化硅所包覆而形成浅沟隔离16，且部分的鳍状结构14上还分别设有多个金属栅极18、20。
鳍状结构14的形成方式可以包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中。接着，对应三栅极晶体管元件及双栅极鳍状晶体管元件结构特性的不同，而可选择性去除或留下图案化掩模，并利用沉积、化学机械研磨(chemicalmechanicalpolishing,CMP)及回蚀刻制作工艺而形成一环绕鳍状结构14底部的浅沟隔离16。除此之外，鳍状结构14的形成方式也可以是先制作一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出半导体层，此半导体层即可作为相对应的鳍状结构14。同样的，另可以选择性去除或留下图案化硬掩模层，并通过沉积、CMP及回蚀刻制作工艺形成一浅沟隔离16以包覆住鳍状结构14的底部。另外，当基底12为硅覆绝缘(SOI)基板时，则可利用图案化掩模来蚀刻基底上的一半导体层，并停止于此半导体层下方的一底氧化层以形成鳍状结构，故可省略前述制作浅沟隔离16的步骤。
金属栅极18、20的制作方式可依据制作工艺需求以先栅极(gatefirst)制作工艺、后栅极(gatelast)制作工艺的先栅极介电层(high-kfirst)制作工艺以及后栅极制作工艺的后栅极介电层(high-klast)制作工艺等方式制作完成。以本实施例的先栅极介电层制作工艺为例，可先于鳍状结构14与浅沟隔离16上形成一优选包含高介电常数介电层与多晶硅材料所构成的虚置栅极(图未示)，然后于虚置栅极侧壁形成间隙壁24。接着于间隙壁24两侧的鳍状结构14以及/或基底12中形成一源极/漏极区域26与外延层28、形成一接触洞蚀刻停止层30覆盖虚置栅极，并形成一由四乙氧基硅烷(Tetraethylorthosilicate,TEOS)所组成的层间介电层32于接触洞蚀刻停止层30上。
之后可进行一金属栅极置换(replacementmetalgate)制作工艺，先平坦化部分的层间介电层32及接触洞蚀刻停止层30，并再将虚置栅极转换为金属栅极18、20。金属栅极置换制作工艺可包括先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammoniumhydroxide,NH4OH)或氢氧化四甲铵(TetramethylammoniumHydroxide,TMAH)等蚀刻溶液来去除虚置栅极中的多晶硅材料以于层间介电层32中形成一凹槽。之后形成一至少包含U型功函数金属层34与低阻抗金属层36的导电层于该凹槽内，并再搭配进行一平坦化制作工艺使U型功函数金属层34与低阻抗金属层36的表面与层间介电层32表面齐平。
在本实施例中，功函数金属层34优选用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层34可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层34可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层34与低阻抗金属层36之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层36则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungstenphosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极乃此领域者所熟知技术，在此不另加赘述。
随后如图2所示，可先去除部分金属栅极18、20形成凹槽，再填入一停止层38于凹槽内并平坦化之。其中停止层38可为单一材料层或复合材料层，例如一包含氧化硅与氮化硅的复合层，且停止层38的上表面优选与层间介电层32的上表面齐平。
然后形成一介电层40于停止层38上，形成一图案化硬掩模42于介电层40上，并利用图案化硬掩模42来去除部分介电层40以形成一开口44暴露出层间介电层32及金属栅极20。在本实施例中，图案化硬掩模42优选由氮化钛所构成，但不局限于此。
接着如图3所示，可选择性去除图案化硬掩模42，或直接利用图案化硬掩模42去除部分层间介电层32以形成多个接触洞46。
随后如图4所示，形成多个接触插塞48于接触洞46中。形成接触插塞48的方法可依序形成一阻障/黏着层(图未示)、一晶种层(图未示)以及一导电层(图未示)覆盖并填满开口44及接触洞46，其中阻障/黏着层共形地(conformally)填入接触洞46中而导电层则完全填满接触洞46。阻障/黏着层的材料例如是钽(Ta)、钛(Ti)、氮化钛(TiN)、钽化钛(TaN)、氮化钨(WN)或是其任意组合例如钛/氮化钛所构成，但并不以此为限。晶种层的材料优选与导电层的材料相同，导电层的材料包含各种低电阻金属材料，例如是铝(Al)、钛(Ti)、钽(Ta)、钨(W)、铌(Nb)、钼(Mo)、铜(Cu)等材料，优选是钨或铜，最佳是钨。最后进行一平坦化制作工艺例如化学机械研磨(CMP)制作工艺、蚀刻制作工艺或是两者的结合，去除部分阻障/黏着层、晶种层、导电层、图案化硬掩模42及介电层40，使剩余的导电层上表面与层间介电层32和金属栅极18、20上表面齐平以形成接触插塞48。
请继续参照图5至图8，图5至图8为本发明另一实施例制作半导体元件的方法示意图。相较于前述图1至图4仅以一道光刻暨蚀刻制作工艺来形成接触插塞48，本发明另一实施例又可利用两道光刻暨蚀刻来制作接触插塞。例如，如图5所示，本实施例可于停止层38与层间介电层32上表面先形成一介电层52，然后再搭配两次光刻暨蚀刻制作工艺、金属层沉积以及平坦化制作工艺于层间介电层32与介电层52中形成多个电连接源极/漏极区域26的接触插塞54。需注意的是，本实施例优选以两次光刻暨蚀刻制作工艺形成接触插塞的方式来进行后续制作工艺，但不局限于此，又可依据制作工艺需求选择上述以一次光刻暨蚀刻制作工艺来制作接触插塞来进行后续制作工艺，此变化型也属本发明所涵盖的范围。
接着依序形成一停止层56、一介电层58、一有机介电层(organicdielectriclayer,ODL)60、一含硅硬掩模及抗反射(silicon-containinghardmaskbottomanti-reflectivecoating,SHB)层62以及一图案化光致抗蚀剂62于介电层52及接触插塞54上。
接着如图6所示，进行两次光刻暨蚀刻制作工艺，以于介电层58中形成两个对应接触插塞54的开口。举例来说，先以图案化光致抗蚀剂62为掩模进行一蚀刻制作工艺，去除部分SHB层62、部分ODL60以及部分介电层58以形成一开口66暴露停止层56。然后先去除图案化光致抗蚀剂64、SHB层62以及ODL60，形成另一ODL(图未示)于介电层58上填满开口66，并依序形成另一SHB层(图未示)与另一图案化光致抗蚀剂(图未示)于ODL上。接着比照前述蚀刻方式再以图案化光致抗蚀剂为掩模去除部分SHB层、部分ODL以及部分介电层以形成另一开口68于开口66旁，然后再去除图案化光致抗蚀剂、SHB层以及ODL。
如图7所示，然后再进行两次光刻暨蚀刻制作工艺，以于介电层58、停止层56及介电层52中形成两个开口70、72。如同前述形成开口66、68的制作方式，可先形成一ODL(图未示)于介电层58上并填满开口66、68，然后依序形成一SHB层(图未示)与一图案化光致抗蚀剂(图未示)于ODL上。接着以图案化光致抗蚀剂为掩模进行一蚀刻制作工艺，去除部分SHB层、部分ODL、部分介电层58、部分停止层56及部分介电层52以形成一开口70暴露停止层38。之后去除图案化光致抗蚀剂、SHB层以及ODL，形成另一ODL(图未示)于介电层58上填满开口66、68、70，并依序形成另一SHB层(图未示)与另一图案化光致抗蚀剂(图未示)于ODL上。接着比照前述蚀刻方式再以图案化光致抗蚀剂为掩模去除部分SHB层、部分ODL、部分介电层58、部分停止层56及部分介电层52以形成另一开口72于开口70旁，然后再去除图案化光致抗蚀剂、SHB层以及ODL。
值得注意的是，蚀刻形成各开口66、68与开口70、72时，分别停止于停止层56与停止层38上，故开口66、68与开口70、72的底部分别暴露停止层56停止层38。
接着如图8所示，同时去除浅沟隔离16上的部分停止层38及鳍状结构14上的部分停止层56以暴露出浅沟隔离16上的金属栅极18及鳍状结构14上的接触插塞54，之后可依据前述图4形成接触插塞48的方式，填入各导电材料再平坦化，以同时形成多个接触插塞74电连接接触插塞54以及金属栅极18。
请继续参照图9至图12，图9至图12为本发明另一实施例延续图1的制作工艺步骤制作半导体元件的方法示意图。如图9所示，首先形成一停止层82于金属栅极18、20及层间介电层32上，以及形成一介电层84于停止层82上，接着进行两次图案转移制作工艺与两次蚀刻制作工艺，再填入各导电材料再平坦化，以同时形成多个接触插塞86于层间介电层32、停止层82及介电层84中电连接基底12中的源极/漏极区域26。然后形成另一停止层88覆盖于介电层84及接触插塞86上，形成一介电层90于停止层88上，并再依序形成一ODL92、一SHB层94以及一图案化光致抗蚀剂96于介电层90上。
如图10所示，接着进行两次光刻暨蚀刻制作工艺，以于介电层90中形成两个对应接触插塞的开口98、100。如同前述图6实施例形成开口66、68的方式，先以图案化光致抗蚀剂96为掩模进行一蚀刻制作工艺，去除部分SHB层94、部分ODL92以及部分介电层90以形成一开口98暴露停止层88。然后去除图案化光致抗蚀剂96、SHB层94以及ODL92，形成另一ODL(图未示)于介电层90上填满开口98，并依序形成另一SHB层(图未示)与另一图案化光致抗蚀剂(图未示)于ODL上。接着再以图案化光致抗蚀剂为掩模去除部分SHB层、部分ODL以及部分介电层90以形成另一开口100于开口98旁，之后再去除图案化光致抗蚀剂、SHB层以及ODL。
随后如图11所示，再进行两次光刻暨蚀刻制作工艺，以于介电层90、停止层88及介电层84中形成两个开口102、104。如同图7的实施例形成开口70、72的方式，可先形成一ODL(图未示)于介电层90上并填满开口98、100，然后依序形成一SHB层(图未示)与一图案化光致抗蚀剂(图未示)于ODL上。接着以图案化光致抗蚀剂为掩模进行一蚀刻制作工艺，去除部分SHB层、部分ODL、部分介电层90、部分停止层88及部分介电层84以形成一开口102暴露停止层82。之后去除图案化光致抗蚀剂、SHB层以及ODL，形成另一ODL(图未示)于介电层90上填满开口98、100、102，并依序形成另一SHB层(图未示)与另一图案化光致抗蚀剂(图未示)于ODL上。接着再以图案化光致抗蚀剂为掩模去除部分SHB层、部分ODL、部分介电层90、部分停止层88及部分介电层84以形成另一开口104于开口102旁。需注意的是，本实施例由第一次图案转移所形成的开口98及第四次图案转移所形成的开口104可依据制作工艺需求调整曝光的位置，可如图8所示的彼此分离，或可例如本图11所示相互紧邻而一同构成一更大的开口，来桥接不同MOS的栅极与源极/漏极区域，以应用于SRAM的元件制作工艺中，此实施例也属本发明所涵盖的范围。
同样地，蚀刻形成各开口98、100与开口102、104时，分别停止于停止层88与停止层82上，故开口98、100与开口102、104的底部分别暴露停止层88停止层82。
最后如图12所示，同时去除部分金属栅极18上的停止层82与接触插塞86上的部分停止层88以暴露出金属栅极18及接触插塞86，然后可依据图4形成接触插塞48的方式，填入各导电材料再平坦化，以同时形成多个接触插塞106、108电连接接触插塞86以及金属栅极18。
请继续参照图12，其另公开一种半导体元件的结构示意图。如图中所示，半导体元件包含一基底12；多个金属栅极18、20设于基底12上；一层间介电层32环绕金属栅极18、20；一停止层82设于层间介电层32及金属栅极18上；一介电层84设于停止层82上；一停止层88设于介电层84上；一介电层90设于停止层88上；多个接触插塞86设于层间介电层32、停止层82及介电层84中并电连接至基底12中的源极/漏极区域26；多个接触插塞106设于停止层88及介电层90中并电连接至接触插塞86；以及多个接触插塞108设于停止层82、介电层84、停止层88及介电层90中并电连接至金属栅极18。
综上所述，本发明优选公开一种利用四道光刻暨蚀刻制作工艺于介电层中形成开口的方法，其中第一道与第二道光刻暨蚀刻制作工艺优选于接触插塞上形成两个开口而暴露一停止层，第三道与第四道光刻暨蚀刻制作工艺则优选于金属栅极上形成两个开口并暴露另一停止层，然后再以另一道蚀刻同时去除接触插塞与金属栅极上部分的两停止层以暴露出接触插塞及金属栅极。由此制作工艺本发明可有效改善现有因光学上的限制而无法完美结合金属栅极与接触插塞的缺点。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (17)

1.一种制作半导体元件的方法，包含：
提供一基底；
形成多个栅极结构于该基底上；
形成一第一停止层于该多个栅极结构上；
形成一第二停止层于该第一停止层上；
形成一第一介电层于该第二停止层上；
形成多个第一开口于该第一介电层中并暴露该第二停止层；
形成多个第二开口于该第一介电层及该第二停止层中并暴露第一停止层；以及
去除部分该第二停止层及部分该第一停止层以暴露出该多个栅极结构。
2.如权利要求1所述的方法，还包含：
形成一层间介电层于该多个栅极结构周围，其中该层间介电层的上表面与该第一停止层的上表面齐平；
形成一第二介电层于该第一停止层上；
形成一图案化硬掩模于该第二介电层上；
利用该图案化硬掩模来去除部分该第二介电层以形成一第三开口暴露出该层间介电层及该多个栅极结构；
利用该图案化硬掩模去除部分该层间介电层以形成多个接触洞；以及
形成多个第一接触插塞于该多个接触洞中。
3.如权利要求2所述的方法，其中该图案化硬掩模包含氮化钛。
4.如权利要求1所述的方法，还包含：
形成一层间介电层于该多个栅极结构周围，其中该层间介电层的上表面与该第一停止层的上表面齐平；
形成一第二介电层于该第一停止层上；
形成多个第一接触插塞于该层间介电层与该第二介电层中以电连接该基底中的一源极/漏极区域；
形成该第二停止层于该第二介电层及该多个第一接触插塞上；
形成该第一介电层于该第二停止层上；
去除部分该第一介电层以形成该多个第一开口暴露该第二停止层；
去除部分该第一介电层、部分该第二停止层及部分该第二介电层以形成该多个第二开口暴露该第一停止层；
去除部分该第二停止层及部分该第一停止层以暴露出该多个栅极结构及该多个第一接触插塞；以及
形成多个第二接触插塞电连接该多个第一接触插塞以及多个第三接触插塞电连接该多个栅极结构。
5.如权利要求4所述的方法，其中该第一介电层及该第二介电层包含氧化硅。
6.如权利要求4所述的方法，还包含一鳍状结构设于该基底上，该鳍状结构位于该多个第一接触插塞正下方。
7.如权利要求6所述的方法，还包含一浅沟隔离围绕该鳍状结构，该浅沟隔离位于该多个第三接触插塞正下方。
8.如权利要求1所述的方法，其中该第一停止层及该第二停止层包含氮化硅。
9.如权利要求1所述的方法，还包含：
形成一层间介电层于该多个栅极结构周围，其中该层间介电层的上表面与该多个栅极结构的上表面齐平；
形成该第一停止层于该多个栅极结构及该层间介电层上；
形成一第二介电层于该第一停止层上；
形成多个第一接触插塞于该层间介电层与该第二介电层中以电连接该基底中的一源极/漏极区域；
形成该第二停止层于该第二介电层及该多个第一接触插塞上；
形成该第一介电层于该第二停止层上；
去除部分该第一介电层以形成该多个第一开口暴露该第二停止层；
去除部分该第一介电层、部分该第二停止层及部分该第二介电层以形成该多个第二开口暴露该第一停止层；
去除部分该第二停止层及部分该第一停止层以暴露出搞多个栅极结构及该多个第一接触插塞；以及
形成多个第二接触插塞电连接该多个第一接触插塞以及多个第三接触插塞电连接该多个栅极结构。
10.如权利要求9所述的方法，其中该第一介电层及该第二介电层包含氧化硅。
11.如权利要求9所述的方法，还包含一鳍状结构设于该基底上，该鳍状结构位于该多个第一接触插塞正下方。
12.如权利要求9所述的方法，还包含一浅沟隔离围绕该鳍状结构，该浅沟隔离位于该多个第三接触插塞正下方。
13.如权利要求1所述的方法，其中该多个栅极结构包含金属栅极。
14.一种半导体元件，包含：
基底；
多个栅极结构，设于该基底上；
层间介电层，环绕该多个栅极结构；
第一停止层，设于该层间介电层及该多个栅极结构上；
第一介电层，设于该第一停止层上；
第二停止层，设于该第一介电层上；
第二介电层，设于该第二停止层上；
多个第一接触插塞，设于该层间介电层、该第一停止层及该第一介电层中并电连接至该基底中的一源极/漏极区域；
多个第二接触插塞，设于该第二停止层及该第二介电层中并电连接至该多个第一接触插塞；以及
多个第三接触插塞，设于该第一停止层、该第一介电层、该第二停止层及该第二介电层中并电连接至该多个栅极结构。
15.如权利要求14所述的半导体元件，其中该多个栅极结构包含金属栅极。
16.如权利要求14所述的半导体元件，其中该第一停止层及该第二停止层包含氮化硅。
17.如权利要求14所述的半导体元件，其中该第一介电层及该第二介电层包含氧化硅。
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