TWI650804B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI650804B
TWI650804B TW104125042A TW104125042A TWI650804B TW I650804 B TWI650804 B TW I650804B TW 104125042 A TW104125042 A TW 104125042A TW 104125042 A TW104125042 A TW 104125042A TW I650804 B TWI650804 B TW I650804B
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dielectric layer
region
disposed
layer
interlayer dielectric
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洪裕祥
許智凱
林昭宏
傅思逸
鄭志祥
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聯華電子股份有限公司
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Abstract

本發明揭露一種製作半導體元件的方法。首先提供一基底具有一第一鰭狀結構設於一第一區域上以及一第二鰭狀結構設於一第二區域上，然後形成複數個第一閘極結構於第一鰭狀結構上、複數個第二閘極結構於第二鰭狀結構上以及一層間介電層圍繞第一閘極結構及第二閘極結構，形成一第一圖案化遮罩於層間介電層上及第一區域與第二區域之間，形成一第二圖案化遮罩於第二區域上，利用第一圖案化遮罩及第二圖案化遮罩去除第一區域上之層間介電層及第二區域上部分之層間介電層，以於第一區域形成複數個第一接觸洞以及於第二區域形成複數個第二接觸洞。

Description

半導體元件及其製作方法
本發明是關於一種製作半導體元件的方法，尤指一種利用多個圖案化遮罩於基底形成具有不同線寬之閘極結構的方法。
近年來，隨著場效電晶體(field effect transistors, FETs)元件尺寸持續地縮小，習知平面式(planar)場效電晶體元件之發展已面臨製程上之極限。為了克服製程限制，以非平面(non-planar)之場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor, Fin FET)元件來取代平面電晶體元件已成為目前之主流發展趨勢。由於鰭狀場效電晶體元件的立體結構可增加閘極與鰭狀結構的接觸面積，因此，可進一步增加閘極對於載子通道區域的控制，從而降低小尺寸元件面臨的汲極引發能帶降低(drain induced barrier lowering, DIBL)效應，並可以抑制短通道效應(short channel effect, SCE)。再者，由於鰭狀場效電晶體元件在同樣的閘極長度下會具有更寬的通道寬度，因而可獲得加倍的汲極驅動電流。甚而，電晶體元件的臨界電壓(threshold voltage)亦可藉由調整閘極的功函數而加以調控。
然而，在現行鰭狀場效電晶體元件製程中，一般以蝕刻方式同時去除設於鰭狀結構邊緣上閘極結構的硬遮罩以及形成接觸洞容易產生開口大小不均的情況，進而影響後續接觸插塞的形成與電性表現。因此如何改良現有鰭狀場效電晶體製程即為現今一重要課題。
本發明較佳實施例揭露一種製作半導體元件的方法。首先提供一基底，該基底具有一第一鰭狀結構設於一第一區域上以及一第二鰭狀結構設於一第二區域上，然後形成複數個第一閘極結構於第一鰭狀結構上、複數個第二閘極結構於第二鰭狀結構上以及一層間介電層圍繞第一閘極結構及第二閘極結構，形成一第一圖案化遮罩於層間介電層上並位於第一區域與第二區域之間，形成一第二圖案化遮罩於第二區域上，利用第一圖案化遮罩及第二圖案化遮罩去除第一區域上所有之層間介電層及第二區域上部分之層間介電層，以於第一區域形成複數個第一接觸洞以及於第二區域形成複數個第二接觸洞。
本發明另一實施例揭露一種半導體元件，包含一基底，該基底上具有一第一區域及一第二區域；一第一鰭狀結構設於第一區域上以及一第二鰭狀結構設於第二區域上；複數個第一閘極結構設於第一鰭狀結構上，其中第一閘極結構之間不具有任何層間介電層；以及複數個第二閘極結構設於第二鰭狀結構上，其中第二閘極結構之間設有一層間介電層。
本發明又一實施例揭露一種半導體元件，包含：一基底，該基底上具有一鰭狀結構；複數個第一閘極結構設於鰭狀結構上以及一層間介電層環繞第一閘極結構；一第一接觸插塞設於層間介電層中且鄰近第一閘極結構；一第一介電層設於層間介電層上；一第二接觸插塞設於第一介電層中並接觸第一接觸插塞；一第二介電層設於第一介電層上；一第三接觸插塞設於第二介電層中並接觸第二接觸插塞；以及一第四接觸插塞設於第二介電層及第一介電層中並電連接第一閘極結構之一者。
請參照第1圖至第8圖，第1圖至第8圖為本發明較佳實施例製作一半導體元件之方法示意圖，其可實施於平面型或非平面型電晶體元件製程，現以應用於非平面型電晶體元件製程為例。如第1圖所示，首先提供一基底12，例如一矽基底或矽覆絕緣(SOI)基板，其上定義有一第一區域40與一第二區域42，其中第一區域40較佳於後續製程中用來製作較小線寬或間距的閘極結構，第二區域42則用來形成具有較大線寬或間距的閘極結構。然後形成一鰭狀結構14於第一區域40的基底12上以及一鰭狀結構14於第二區域42的基底12上，其中鰭狀結構14的底部係被絕緣層，例如氧化矽所包覆而形成淺溝隔離16。接著形成複數個閘極結構18、20於第一區域40的鰭狀結構14上以及複數個閘極結構22於第二區域42的鰭狀結構14上，其中第一區域40的閘極結構20較佳設於鰭狀結構14邊緣且同時跨在鰭狀結構14與淺溝隔離16上。
鰭狀結構14之形成方式可以包含先形成一圖案化遮罩(圖未示)於基底12上，再經過一蝕刻製程，將圖案化遮罩之圖案轉移至基底12中。接著，對應三閘極電晶體元件及雙閘極鰭狀電晶體元件結構特性的不同，而可選擇性去除或留下圖案化遮罩，並利用沈積、化學機械研磨(chemical mechanical polishing, CMP)及回蝕刻製程而形成一環繞鰭狀結構14底部之淺溝隔離16。除此之外，鰭狀結構14之形成方式另也可以是先製作一圖案化硬遮罩層(圖未示)於基底12上，並利用磊晶製程於暴露出於圖案化硬遮罩層之基底12上成長出半導體層，此半導體層即可作為相對應的鰭狀結構14。同樣的，另可以選擇性去除或留下圖案化硬遮罩層，並透過沈積、CMP及回蝕刻製程形成一淺溝隔離16以包覆住鰭狀結構14之底部。另外，當基底12為矽覆絕緣(SOI)基板時，則可利用圖案化遮罩來蝕刻基底上之一半導體層，並停止於此半導體層下方的一底氧化層以形成鰭狀結構，故可省略前述製作淺溝隔離16的步驟。
閘極結構18、20、22之製作方式可依據製程需求以先閘極(gate first)製程、後閘極(gate last)製程之先閘極介電層(high-k first)製程以及後閘極製程之後閘極介電層(high-k last)製程等方式製作完成。以本實施例之先閘極介電層製程為例，可先於鰭狀結構14與淺溝隔離16上形成一較佳包含高介電常數介電層與多晶矽材料所構成的虛置閘極(圖未示)，然後於虛置閘極側壁形成側壁子24。接著於側壁子24兩側的鰭狀結構14以及/或基底12中形成一源極/汲極區域26與磊晶層(圖未示)、選擇性形成一接觸洞蝕刻停止層(圖未示)覆蓋虛置閘極，並形成一由四乙氧基矽烷(Tetraethyl orthosilicate, TEOS)所組成的層間介電層32上。在本實施例中，側壁子24較佳包含一由氧化矽-氮化矽-氧化矽等三層介電材料所構成的側壁子，但不侷限於此。
之後可進行一金屬閘極置換(replacement metal gate)製程，先平坦化部分之層間介電層32，並再將虛置閘極轉換為閘極結構18、20、22等金屬閘極。金屬閘極置換製程可包括先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide, NH4 OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide, TMAH)等蝕刻溶液來去除虛置閘極中的多晶矽材料以於層間介電層32中形成一凹槽。之後形成一至少包含U型功函數金屬層34與低阻抗金屬層36的導電層於該凹槽內，並再搭配進行一平坦化製程使U型功函數金屬層34與低阻抗金屬層36的表面與層間介電層32表面齊平。
在本實施例中，功函數金屬層34較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層34可選用功函數為3.9電子伏特(eV)～4.3 eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC (碳化鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層34可選用功函數為4.8 eV～5.2 eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層34與低阻抗金屬層36之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層36則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。由於依據金屬閘極置換製程將虛置閘極轉換為金屬閘極乃此領域者所熟知技藝，在此不另加贅述。
之後可選擇性先去除部分功函數金屬層34與低阻抗金屬層36，然後填入一硬遮罩38於功函數金屬層34與低阻抗金屬層36上形成閘極結構18、20、22。其中硬遮罩38可為單一材料層或複合材料層，例如一包含氧化矽與氮化矽之複合層。
接著先全面性覆蓋一遮蓋層44於閘極結構18、20、22與層間介電層32上，然後再形成一遮罩層46於遮蓋層44上。在本實施例中，遮蓋層44主要作為一前金屬介電層(pre-metal dielectric, PMD)，其可選擇與層間介電層32相同或不同之材料所構成，例如較佳為氧化矽，而遮罩層46則為一金屬遮罩，且較佳由氮化鈦(TiN)所構成。
然後如第2圖所示，依序形成一有機介電層(organic dielectric layer, ODL)48、一含矽硬遮罩及抗反射(silicon-containing hard mask bottom anti-reflective coating, SHB)層50以及一圖案化遮罩52於遮罩層46上，其中圖案化遮罩52可包含一圖案化光阻或由氮化鈦所構成的圖案化遮罩，且圖案化遮罩52較佳設置於第一區域40與第二區域42之間。
如第3圖所示，接著利用圖案化遮罩52進行一蝕刻製程，去除部分SHB 50、部分ODL 48以及部分遮罩層46，然後去除圖案化遮罩52、剩餘的SHB 50與剩餘的ODL 48，以於遮蓋層44上形成一圖案化遮罩54，且圖案化遮罩54較佳設於第一區域40與第二區域42之間的遮蓋層44上。
如第4圖所示，再依序形成另一ODL 56、另一SHB 58以及另一圖案化遮罩60於遮蓋層44與圖案化遮罩54上，其中圖案化遮罩60可包含一圖案化光阻或由氮化鈦所構成的圖案化遮罩，且圖案化遮罩60較佳設置於第二區域42並暴露所有第一區域40的SHB 58與部分第二區域42的SHB 58。
如第5圖所示，接著利用圖案化遮罩60與第3圖所形成的圖案化遮罩54為遮罩進行一蝕刻製程，去除未被圖案化遮罩60與圖案化遮罩54所遮蔽的部分SHB 58、部分ODL 56、部分遮蓋層44以及部分層間介電層32，以於第一區域40與第二區域42分別形成複數個接觸洞62、64。然後再去除圖案化遮罩60、剩餘的SHB 58以及剩餘的ODL 56。值得注意的是，由於圖案化遮罩60與圖案化遮罩54遮住部分第二區域42但暴露出所有第一區域40，並利用閘極結構18、20的側壁子24來進行自對準接觸洞製程，使蝕刻製程較佳去除第一區域40上所有的層間介電層32形成接觸洞62，但此同時，蝕刻製程僅去除第二區域42上部分層間介電層32，並於第二區域42的層間介電層32中形成接觸洞64，因此蝕刻製程完成後第一區域40的閘極結構18、20之間將不存在任何層間介電層32而第二區域42的閘極結構22之間仍設有層間介電層32。
接著如第6圖所示，再依序形成另一ODL 66、另一SHB 68以及另一圖案化遮罩70於閘極結構18、20、22、層間介電層32、圖案化遮罩54以及遮蓋層44上，並填入各接觸洞62、64中，其中圖案化遮罩70可包含一圖案化光阻或由氮化鈦所構成的圖案化遮罩。
然後如第7圖所示，利用圖案化遮罩70進行一蝕刻製程，去除第一區域40內未被圖案化遮罩70所覆蓋的部分SHB 68、部分ODL 66以及設置於鰭狀結構14右邊邊緣上的部分閘極結構20，藉此暴露出閘極結構20的閘極電極表面，例如閘極結構20中的功函數金屬層34與低阻抗金屬層36。之後再去除圖案化遮罩70、剩餘的SHB 68以及剩餘的ODL 66。
接著如第8圖所示，進行一接觸插塞製程，例如先依序沉積一阻障層72以及一由低電阻材料所構成的金屬層74於閘極結構18、20、22、層間介電層32、圖案化遮罩54以及遮蓋層44上並填滿第一區域40與第二區域42的各接觸洞62、64，然後利用硬遮罩38當作停止層來進行一CMP製程，去除部分金屬層74、阻障層72、圖案化遮罩54以及遮蓋層44，以於第一區域40與第二區域42分別形成複數個接觸插塞76、78。在本實施例中，阻障層72可選自由鈦(Ti)、氮化鈦(TiN)、鉭(Ta)以及氮化鉭(TaN)等所構成的群組而金屬層74可選自由鎢(W)、銅(Cu)、鋁(Al)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等所構成的群組。
以第8圖的結構來看，半導體元件主要包含複數個閘極結構18、20設於第一區域40的鰭狀結構14上，複數個閘極結構22設於第二區域42的鰭狀結構14上，複數個接觸插塞76設於第一區域70的閘極結構18、20之間以及複數個接觸插塞78設於第二區域42的閘極結構22之間。在本實施例中，第一區域40的閘極結構18、20之間不具有任何層間介電層32，因此第一區域40的接觸插塞76除了設於閘極結構18、20之間又同時直接接觸閘極結構18、20旁的側壁子24。第二區域42的閘極結構22之間則設有一層間介電層32，因此第二區域42的接觸插塞78除了設於閘極結構22之間又同時接觸層間介電層32。
請繼續參照第9圖至第10圖，第9圖至第10圖為本發明另一實施例於第8圖形成接觸插塞76、78後繼續於接觸插塞76、78上形成多層介電層與接觸插塞之方法示意圖。如第9圖所示，先依序形成停止層80與一介電層82於層間介電層32與接觸插塞76、78上，然後利用微影暨蝕刻製程去除部分介電層82與停止層80以形成接觸洞(圖未示)暴露接觸插塞76、78。接著比照第8圖的接觸插塞製程依序形成阻障層72與金屬層74於接觸洞內，並搭配進行一CMP製程以形成接觸插塞84、86於接觸插塞76、78正上方。
隨後再重複沉積一停止層88與一介電層90於介電層82上，然後進行一次或多次微影暨蝕刻製程去除部分介電層90、部分停止層88、部分介電層82、部分停止層80以及硬遮罩38以形成接觸洞92暴露接觸插塞84、86以及接觸洞94暴露閘極結構18、20、22中的閘極電極或功函數金屬層34與低阻抗金屬層36。
之後如第10圖所示，再比照第8圖進行接觸插塞製程，依序形成阻障層72與金屬層74於接觸洞92、94內，並搭配進行一CMP製程以形成接觸插塞96、98於接觸插塞84、86正上方以及接觸插塞100電連接各閘極結構18、20、22。至此即完成本發明另一實施例之半導體元件的製作。
以第10圖第一區域40的結構來看，半導體元件主要包含複數個閘極結構18、20設於鰭狀結構14上、一層間介電層32環繞閘極結構18、20、複數個接觸插塞76設於層間介電層32中以及閘極結構18、20之間、一介電層82設於閘極結構18、20與層間介電層32上、一停止層80設於介電層82與層間介電層32之間、複數個接觸插塞84設於介電層82中並接觸接觸插塞76、一介電層90設於介電層82上、另一停止層88設於介電層90與介電層82之間、複數個接觸插塞96設於介電層90中並接觸接觸插塞84以及一接觸插塞100設於介電層90及介電層82中並電連接閘極結構18、20。
整體來看，本實施例較佳揭露一種三層接觸插塞結構，其中源極/汲極區域26正上方設有三個接觸插塞76、84、96分別設於層間介電層32、介電層82與介電層90中且均彼此接觸，閘極結構18、20正上方則設有單一一個接觸插塞100，且源極/汲極區域26上方最上層的接觸插塞96上表面與閘極結構18、20上方之接觸插塞100上表面齊平。
需注意的是，有別於習知利用雙鑲嵌製程所形成的接觸插塞具有溝渠導體與接觸洞導體，本發明之接觸插塞76、84、96、100並非採用雙鑲嵌製程來形成，因此各接觸插塞76、84、96、100僅具有單一導體，例如一般雙鑲嵌結構中的溝渠導體或接觸洞導體。其次，本實施例所揭露的各接觸插塞76、84、96、100均包含一U型阻隔層72與一金屬層74設於其上，且各接觸插塞76、84、96、100的U型阻隔層72上表面均與金屬層74上表面切齊。
另外在本實施例中，第一區域40的鰭狀結構14的左右邊緣上各設有一閘極結構20，其中右邊邊緣的閘極結構20上具有一接觸插塞76同時接觸並電連接閘極結構20與源極/汲極區域26，且接觸插塞76正上方另設有兩個接觸插塞84、96。換句話說，相較於左邊三個閘極結構18、20正上方僅電連接單一一個接觸插塞100，第一區域40最右邊的閘極結構20是電連接三層接觸插塞76、84、96。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12‧‧‧基底
14‧‧‧鰭狀結構
16‧‧‧淺溝隔離
18‧‧‧閘極結構
20‧‧‧閘極結構
22‧‧‧閘極結構
24‧‧‧側壁子
26‧‧‧源極/汲極區域
32‧‧‧層間介電層
34‧‧‧功函數金屬層
36‧‧‧低阻抗金屬層
38‧‧‧硬遮罩
40‧‧‧第一區域
42‧‧‧第二區域
44‧‧‧遮蓋層
46‧‧‧遮罩層
48‧‧‧有機介電層
50‧‧‧含矽硬遮罩及抗反射層
52‧‧‧圖案化遮罩
54‧‧‧圖案化遮罩
56‧‧‧ODL
58‧‧‧SHB
60‧‧‧圖案化遮罩
62‧‧‧接觸洞
64‧‧‧接觸洞
66‧‧‧ODL
68‧‧‧SHB
70‧‧‧圖案化遮罩
72‧‧‧阻障層
74‧‧‧金屬層
76‧‧‧接觸插塞
78‧‧‧接觸插塞
80‧‧‧停止層
82‧‧‧介電層
84‧‧‧接觸插塞
86‧‧‧接觸插塞
88‧‧‧停止層
90‧‧‧介電層
92‧‧‧接觸洞
94‧‧‧接觸洞
96‧‧‧接觸插塞
98‧‧‧接觸插塞
100‧‧‧接觸插塞
第1圖至第8圖為本發明較佳實施例製作一半導體元件之方法示意圖。 第9圖至第10圖為本發明另一實施例製作一半導體元件之方法示意圖。

Claims (14)

  1. 一種製作半導體元件的方法，包含：提供一基底，該基底具有一第一鰭狀結構設於一第一區域上以及一第二鰭狀結構設於一第二區域上；形成複數個第一閘極結構於該第一鰭狀結構上、複數個第二閘極結構於該第二鰭狀結構上以及一層間介電層圍繞該等第一閘極結構及該等第二閘極結構；形成一第一圖案化遮罩於該層間介電層上並位於該第一區域及該第二區域之間；形成一第二圖案化遮罩於該第二區域上；利用該第一圖案化遮罩及該第二圖案化遮罩去除該第一區域上所有之該層間介電層及第二區域上部分之該層間介電層，以於該第一區域形成複數個第一接觸洞以及於該第二區域形成複數個第二接觸洞。
  2. 如申請專利範圍第1項所述之方法，另包含於形成該第一圖案化遮罩前形成一遮蓋層於該等第一閘極結構、該等第二閘極結構及該層間介電層上。
  3. 如申請專利範圍第2項所述之方法，另包含於去除該第一區域上所有之該層間介電層及第二區域上部分該層間介電層之前利用該第一圖案化遮罩及該第二圖案化遮罩去除部分該遮蓋層。
  4. 如申請專利範圍第1項所述之方法，其中該第一圖案化遮罩 包含氮化鈦。
  5. 如申請專利範圍第1項所述之方法，其中該第一鰭狀結構之一邊緣上設有一第三閘極結構，該方法另包含利用一第三圖案化遮罩去除部分該第三閘極結構。
  6. 如申請專利範圍第5項所述之方法，另包含：形成一金屬層於該等第一接觸洞及該等第二接觸洞中及該第一圖案化遮罩及該層間介電層上；以及去除部分該金屬層及該第一圖案化遮罩以形成複數個第一接觸插塞於該第一區域及複數個第二接觸插塞於該第二區域。
  7. 一種半導體元件，包含：一基底，該基底上具有一第一區域及一第二區域；一第一鰭狀結構設於該第一區域上以及一第二鰭狀結構設於該第二區域上；複數個第一閘極結構設於該第一鰭狀結構上，其中該等第一閘極結構之間不具有任何層間介電層；以及複數個第二閘極結構設於該第二鰭狀結構上，其中該等第二閘極結構之間設有一層間介電層。
  8. 如申請專利範圍第7項所述之半導體元件，其中各該第一閘極結構旁設有一側壁子，該半導體元件另包含複數個第一接觸插塞設於該等第一閘極結構之間並直接接觸該側壁子。
  9. 如申請專利範圍第7項所述之半導體元件，另包含複數個第二接觸插塞設於該等第二閘極結構旁並直接接觸該層間介電層。
  10. 一種半導體元件，包含：一基底，該基底上具有一鰭狀結構；複數個第一閘極結構設於該鰭狀結構上以及一層間介電層環繞該等第一閘極結構；一第一接觸插塞設於該層間介電層中且鄰近該等第一閘極結構；一第一介電層設於該層間介電層上；一第二接觸插塞設於該第一介電層中並接觸該第一接觸插塞；一第二介電層設於該第一介電層上；一第三接觸插塞設於該第二介電層中並接觸該第二接觸插塞；以及一第四接觸插塞設於該第二介電層及該第一介電層中並電連接該等第一閘極結構之一者。
  11. 如申請專利範圍第10項所述之半導體元件，另包含：一第一停止層設於該層間介電層及該第一介電層之間；以及一第二停止層設於該第一介電層及該第二介電層之間。
  12. 如申請專利範圍第10項所述之半導體元件，其中該第二接觸插塞及該第三接觸插塞設於該第一接觸插塞正上方。
  13. 如申請專利範圍第10項所述之半導體元件，其中各該第一 接觸插塞、第二接觸插塞、該第三接觸插塞及該第四接觸插塞包含一U型阻隔層。
  14. 如申請專利範圍第10項所述之半導體元件，另包含一第二閘極結構設於該鰭狀結構之一邊緣及一淺溝隔離上。
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