CN105502280A - Mems器件的形成方法 - Google Patents
Mems器件的形成方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 59
- 230000008569 process Effects 0.000 claims abstract description 29
- 238000005520 cutting process Methods 0.000 claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 48
- 239000000758 substrate Substances 0.000 claims description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 33
- 229910052710 silicon Inorganic materials 0.000 claims description 33
- 239000010703 silicon Substances 0.000 claims description 33
- 239000011521 glass Substances 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 13
- 239000011435 rock Substances 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 9
- 238000009966 trimming Methods 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 8
- 239000003292 glue Substances 0.000 claims description 8
- 239000004411 aluminium Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 abstract 12
- 239000004065 semiconductor Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000001312 dry etching Methods 0.000 description 8
- 239000013078 crystal Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 229960001866 silicon dioxide Drugs 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- ZWEHNKRNPOVVGH-UHFFFAOYSA-N 2-Butanone Chemical compound CCC(C)=O ZWEHNKRNPOVVGH-UHFFFAOYSA-N 0.000 description 2
- 229920000297 Rayon Polymers 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000013467 fragmentation Methods 0.000 description 2
- 238000006062 fragmentation reaction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000011946 reduction process Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 230000003319 supportive effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00333—Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
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- B81—MICROSTRUCTURAL TECHNOLOGY
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- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/8232—Field-effect technology
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- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
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Abstract
一种MEMS器件的形成方法。采用第一支撑板的支撑,对第一晶圆与第二晶圆中的一个进行减薄,并在减薄面上做对准标记,后在减薄面上粘合第二支撑板;去除第一支撑板,利用对准标记将第三晶圆与未减薄的另一个晶圆形成的双层堆叠结构与该减薄后的晶圆键合形成三层堆叠结构,第二支撑板能提高上述键合过程中已减薄的晶圆的支撑力;去除第二支撑板,对具有对准标记的该个已减薄晶圆进行切割,后在减薄面上粘合第三支撑板,以提高已切割晶圆的支撑力,使得对三层堆叠结构中未减薄的该个晶圆进行减薄过程中,三层堆叠晶圆不易发生破碎;最后切割三层堆叠结构形成各个MEMS器件。采用了第一至第三支撑板,获得了完整且体积小的MEMS器件。
Description
技术领域
本发明涉及半导体技术领域,尤其涉及一种MEMS器件的形成方法。
背景技术
从二十世纪八十年代末开始,随着微机电***(MicroElectroMechanicalSystem,MEMS)技术的发展,一些半导体器件,例如各种传感器实现了微小型化,实现了批量生产,成为未来发展的主要方向。
现有技术中,一些MEMS器件包括三层晶圆,即将三片晶圆通过键合的方式堆叠在一起进行切割形成。实际工艺中发现,中间层晶圆由于边缘为弧形,而减薄量又需比较大,因而为防止减薄过程中中间层晶圆破裂,中间层晶圆需做切边处理,上述切边后的空间会使得三片式晶圆堆叠结构中,中间层晶圆边缘存在间隙。具有上述间隙的三片式晶圆堆叠结构在对上层用于形成MEMS器件的盖层的晶圆或下层用于形成MEMS器件的衬底的晶圆进行减薄或对减薄后的三片式晶圆堆叠结构进行切割过程中,某层或几层晶圆容易破裂导致无法将减薄或切割过程中进行下去,因而无法获得完整且体积小的MEMS器件。
针对上述技术问题,本发明提供一种MEMS器件的形成方法加以解决。
发明内容
本发明解决的问题是对于中间层晶圆进行切边后的三片式晶圆堆叠结构,在上层晶圆或下层晶圆减薄或对减薄后的三片式晶圆堆叠结构进行切割过程中,某层或几层晶圆容易破裂,无法得到完整且体积小的MEMS器件。
为解决上述问题,本发明提供一种MEMS器件的形成方法,包括:
分别提供第一晶圆、第二晶圆以及第三晶圆,所述第一晶圆用于形成MEMS器件的衬底,其正面具有MOS晶体管、金属互连结构以及第一沟槽;所述第二晶圆用于形成MEMS器件的盖层,其正面具有第二沟槽;
将第一晶圆与第二晶圆之一与第三晶圆的正面键合;
对键合后的第三晶圆进行切边、后进行减薄工序;
在所述减薄后的第三晶圆上至少制作可动电极;
在第一晶圆与第二晶圆中的另一个的正面粘贴第一支撑板,后进行背面减薄并在减薄面上制作对准标记,后在具有所述对准标记的减薄面上粘贴第二支撑板;
去除所述第一支撑板,利用所述对准标记将所述第一晶圆与第二晶圆中减薄的该个与所述第三晶圆键合形成晶圆堆叠结构,使得可动电极悬浮于所述第一沟槽与第二沟槽形成的空腔内;
去除所述第二支撑板,对具有对准标记的该个晶圆进行切割,后在被切割的晶圆的背面粘贴第三支撑板;
对第一晶圆与第二晶圆中未减薄的该个晶圆进行减薄,并在减薄面上贴切割用膜,去除所述第三支撑板,沿已切割的该个晶圆的切割道对所述晶圆堆叠结构进行切割形成MEMS器件。
可选地,所述第一支撑板为玻璃基板,所述玻璃基板的尺寸与第一晶圆与第二晶圆的尺寸匹配。
可选地,所述第一基板的粘贴采用紫外固化胶。
可选地,所述第二支撑板为玻璃基板,所述玻璃基板的尺寸与第一晶圆与第二晶圆的尺寸匹配。
可选地,所述第三支撑板为UV膜。
可选地,所述第一晶圆的正面还形成有固定电极,在减薄后的第三晶圆上制作可动电极前,还所述第三晶圆上制作第一穿硅通孔导电结构、第二穿硅通孔导电结构以及第三穿硅通孔导电结构,分别用于将固定电极、可动电极以及MOS晶体管的信号引出。
可选地,在减薄后的第三晶圆上还制作有若干焊垫,所述若干焊垫分别与所述固定电极、可动电极以及MOS晶体管电连接。
可选地,所述若干焊垫分别位于所述第一穿硅通孔导电结构、第二穿硅通孔导电结构以及第三穿硅通孔导电结构上。
可选地,具有对准标记的该个晶圆为第二晶圆。
可选地,所述对准标记为凹槽,采用光刻、刻蚀法形成。
可选地,还在所述减薄后的第三晶圆上制作第一凸起,粘贴第一支撑板前,还在未与第三晶圆键合的第一晶圆或第二晶圆上制作第二凸起,形成所述晶圆堆叠结构时,所述第一凸起与第二凸起键合形成用于可动电极悬浮的空腔。
可选地,所述第一凸起与所述第二凸起中的一个的材质为铝,另一个材质为锗。
与现有技术相比,本发明的技术方案具有以下优点:1)采用第一支撑板的支撑,对下层用于形成MEMS器件的衬底的第一晶圆与上层用于形成MEMS器件的盖层的第二晶圆中的一个进行减薄,并在减薄面上做对准标记,后在具有对准标记的减薄面上粘合第二支撑板;去除第一支撑板后,利用对准标记将中间层用于形成MEMS器件可动电极的第三晶圆与未减薄的第一晶圆与第二晶圆中的另一个形成的双层堆叠结构与该减薄后的第一晶圆或第二晶圆键合形成三层堆叠结构,该第二支撑板能提高上述键合过程中已减薄的该个晶圆的支撑力;去除第二支撑板,对具有对准标记的该个已减薄晶圆进行切割,并在已切割晶圆外表面上粘合第三支撑板,该第三支撑板能提高已切割晶圆的支撑力,使得对三层堆叠结构中的未减薄的该个晶圆进行减薄过程中,三层堆叠晶圆不易发生破碎;最后沿已切割的该个晶圆的切割道对三层堆叠晶圆进行切割,形成各个MEMS器件。由于采用了第一至第三支撑板,获得了完整且体积小的MEMS器件。
2)可选方案中,该第一支撑板为玻璃基板或裸片,玻璃基板的尺寸与第一晶圆与第二晶圆的尺寸匹配,相对于裸片,玻璃基板的成本较低,另外,由于玻璃基板透明,易在形成对准标记过程中,进行正反两面对准。
3)可选方案中,该第二支撑板为玻璃基板或裸片,玻璃基板的尺寸与第一晶圆与第二晶圆的尺寸匹配,相对于裸片,玻璃基板的成本较低,另外,由于玻璃基板透明,易在形成三层堆叠晶圆过程中,实现对准。
4)可选方案中,具有对准标记的该个晶圆为上层用于形成MEMS器件的盖层的第二晶圆,相对于在下层用于形成MEMS器件的衬底的第一晶圆背面形成对准标记的方案,前者能减少MEMS器件被翻转的次数,降低上述翻转过程中对MEMS器件中可动电极或其它部件的损坏风险。
5)可选方案中,MEMS器件的固定电极形成在第一晶圆的正面,在减薄后的第三晶圆上制作可动电极前,还在减薄的第三晶圆上制作第一穿硅通孔、第二穿硅通孔以及第三穿硅通孔,分别用于将固定电极、可动电极以及MOS晶体管的信号引出,相对于从第一晶圆的正面或背面将固定电极、可动电极以及MOS晶体管的信号引出的方案,前者能提高MEMS器件的集成度。
附图说明
图1至图11是本发明一实施例中的MEMS器件形成过程的结构示意图。
具体实施方式
如背景技术中所述,现有技术中对于中间层晶圆进行切边后的三片式晶圆堆叠结构,在上层晶圆或下层晶圆减薄或对减薄后的三片式晶圆堆叠结构进行切割过程中,某层或几层晶圆容易破裂,无法得到完整且体积小的MEMS器件。针对上述技术问题,本发明提出:采用第一支撑板的支撑,对下层用于形成MEMS器件的衬底的第一晶圆与上层用于形成MEMS器件的盖层的第二晶圆中的一个进行减薄,并在减薄面上做对准标记,后在具有对准标记的减薄面上粘合第二支撑板;去除第一支撑板后,利用对准标记将中间层用于形成MEMS器件可动电极的第三晶圆与未减薄的第一晶圆与第二晶圆中的另一个形成的双层堆叠结构与该减薄后的第一晶圆或第二晶圆键合形成三层堆叠结构,该第二支撑板能提高上述键合过程中已减薄的该个晶圆的支撑力;去除第二支撑板,对具有对准标记的该个已减薄晶圆进行切割,并在已切割晶圆的减薄面上粘合第三支撑板,该第三支撑板能提高已切割晶圆的支撑力,使得对三层堆叠结构中的未减薄的该个晶圆进行减薄过程中,三层堆叠晶圆不易发生破碎;最后沿已切割的该个晶圆的切割道对三层堆叠晶圆进行切割,形成各个MEMS器件。可以看出,由于采用了第一至第三支撑板,获得了完整且体积小的MEMS器件。
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图1至图11是本发明一实施例中的MEMS器件形成过程的结构示意图。以下结合图1至图11所示,详细介绍制作方法。
本实施例以形成两个MEMS器件为例进行说明。
首先,参照图1所示,提供第一晶圆1与第三晶圆3,并对两者键合。第一晶圆1用于形成MEMS器件的衬底,包括半导体基底10以及半导体基底10表面的介质层11,介质层11用于将形成在半导体基底10正面的MOS晶体管(未图示)、金属互连结构等电绝缘。图1中示出两个金属线图案113,该两个金属线图案113分别与半导体基底10正面的若干MOS晶体管电连接。此外,介质层11内还形成有第一沟槽111,以及电极板112,其中,第一沟槽111暴露部分电极板112。
本实施例中,第三晶圆3只具有半导体基底,材质例如为硅。
上述键合采用熔胶键合(Fusionbonding),即对第三晶圆3的正面与第一晶圆1正面的氧化硅层(Silicondioxide)进行化学处理,使得两者之间产生吸附力,具体工艺参数参照现有技术中的熔胶键合参数。上述氧化硅层为金属互连结构的一部分。第一沟槽111可以采用光刻、干法刻蚀形成。
本步骤中,第一晶圆1与第三晶圆3的厚度为常规晶圆的厚度,一个实施例中,大约725μm。
接着,参照图2所示,对键合后的第三晶圆3进行切边、后进行减薄工序。
上述减薄的目的是减小MEMS器件的尺寸。由于常规晶圆的边缘为弧形,切边可以防止上述弧形导致的晶圆减薄过程中所出现的破碎问题。
在具体实施过程中,上述切边的尺寸大约为2mm~4mm。一个实施例中,减薄后的第三晶圆3的厚度范围为20μm~50μm。
参照图3,在减薄后的第三晶圆3上制作可动电极31、所述可动电极31的制作过程可以为光刻、干法刻蚀。
在制作可动电极31前,还减薄后的第三晶圆3上制作了若干穿硅通孔,具体地,本实施例中的穿硅通孔包括:第一穿硅通孔,第二穿硅通孔以及第三穿硅通孔。其中,第一穿硅通孔的底部暴露了电极板112,该电极板112用作MEMS器件的固定电极;第二穿硅通孔(未图示)的底部暴露了适于形成可动电极的该部分硅材质,第三穿硅通孔的底部暴露了金属线图案113。在第三晶圆3的表面形成导电材料,例如钨、铜等,化学机械研磨去除各穿硅通孔外的多余的导电材料,参照图3所示,分别形成第一穿硅通孔导电结构32,第二穿硅通孔导电结构(未图示)以及第三穿硅通孔导电结构33,分别用于将固定电极112、可动电极31以及MOS晶体管的信号引出。
之后,仍参照图3所示,还在第一穿硅通孔导电结构32,第二穿硅通孔导电结构(未图示)以及第三穿硅通孔导电结构33上分别制作第一焊垫34、第二焊垫(未图示)以及第三焊垫35,用于与其它器件电连接。在具体实施过程中,上述焊垫34的材质例如为铝,采用光刻、干法刻蚀法形成。
接着,继续参照图3所示,还在第三晶圆3的减薄面上制作四个第一凸起36,该第一凸起36的材质例如为铝,采用光刻、干法刻蚀法形成。四个第一凸起36对应两个MEMS器件,其中,图3左边的两个第一凸起36分别位于左边的可动电极31两侧,对应一个MEMS器件;右边的两个第一凸起36分别位于右边的可动电极31两侧,对应另一个MEMS器件。
之后,光刻、干法刻蚀形成可动电极31。
参照图4,提供第二晶圆2,该第二晶圆2用于形成MEMS器件的盖层,其正面具有第二沟槽20,以及分别位于第二沟槽20两边的两第二凸起21。
相应地,第二晶圆2也对应形成两个MEMS器件,具体地,为两个MEMS器件的盖层。因而具有两个第二沟槽20以及四个第二凸起21,位于左边的第二沟槽20以及两边的两第二凸起21对应一个MEMS器件,位于右边的第二沟槽20以及两边的两第二凸起21对应另一个MEMS器件。
第二晶圆2的厚度为常规晶圆厚度,本实施例中,例如为725μm左右。
四个第二凸起21的形成方法例如为:在第二晶圆2的半导体基底正面依次沉积二氧化硅层、锗层,光刻、干法刻蚀该二氧化硅层、锗层形成第二凸起21。第二晶圆2的半导体基底材质例如为硅。二氧化硅层用于提高硅与锗之间的粘附力。
后在四个第二凸起21以及第二晶圆2的半导体基底正面形成一光刻胶,曝光显影后,干法刻蚀半导体基底的部分厚度形成第二沟槽20。
接着,参照图5所示,在第二晶圆2的正面粘贴第一支撑板4。
在具体实施过程中,该第一支撑板4为玻璃基板或裸片,本实施例中为玻璃基板,该玻璃基板的尺寸与第一晶圆1与第二晶圆2的尺寸匹配,即大致相等,相对于裸片,玻璃基板的成本较低。
粘结第一支撑板4的方式例如采用紫外固化胶,由于第二凸起21的尺寸较小,因而优选在第一支撑板4的一个表面涂布紫外固化胶,携带有紫外固化胶的该面与第二晶圆2对准后,第二凸起21与第一支撑板4之间具有紫外固化胶,紫外线照射下,紫外固化胶变性,将第二凸起21与第一支撑板4粘结在一起。
然后,参照图6所示,对第二晶圆2进行背面减薄并在减薄面上制作对准标记22。
上述对第二晶圆2进行背面减薄的工艺参照现有的减薄工艺。
在减薄面上制作的对准标记22例如为沟槽,制作工艺例如为光刻、干法刻蚀形成。
可以理解的是,第一支撑板4在第二晶圆2的减薄过程中起支撑作用。此外,由于采用了玻璃基板做第一支撑板4,玻璃基板透明,易在形成对准标记22过程中,进行正反两面对准。
之后,参照图7所示,在具有所述对准标记22的减薄面上粘贴第二支撑板5。
粘结第二支撑板5的工艺参照粘结第一支撑板4的工艺,在此不再赘述。
可以理解的是,上述图4至图7中的步骤与图1至图3中的步骤可以分别进行,无先后顺序,也可以同时进行。
之后,参照图8所示,去除第一支撑板4,利用对准标记22将所述第二晶圆2与所述第三晶圆3键合形成晶圆堆叠结构,使得可动电极31悬浮于所述第一沟槽111与第二沟槽20形成的空腔内。
本步骤中,去除第一支撑板4采用可溶解变性后的紫外固化胶的有机溶剂,例如甲苯、丁酮等。
本实施例中,键合第二晶圆2与第三晶圆3通过第一凸起36与第二凸起21的键合实现,采用铝与锗的共熔键合(Eutecticbonding),具体工艺参数参照现有技术中的工艺参数。可以理解的是,本实施例中,第一凸起36的材质为铝,第二凸起21的材质为锗,其它实施例中,第一凸起36的材质也可以为锗,第二凸起21的材质为铝。
本步骤中,第二支撑板5在键合第二晶圆2与第三晶圆3过程中,可以提高已减薄的第二晶圆2的支撑力。
接着,参照图9所示,去除所述第二支撑板5,对第二晶圆2进行切割,后在被切割的第二晶圆2的背面粘贴第三支撑板6。
一个实施例中,第三支撑板6的材质为UV膜,厚度为400μm~500μm。其它实施例中,上述第三支撑板6也可以为玻璃基板,相对于玻璃基板,上述UV膜可以进行一定程度变形,较服帖。在具体实施过程中,UV膜上具有一些化学物质,例如黏胶,能将已切割的第二晶圆2仍保持一个整体,在UV光照射下,上述黏胶变性,使得UV膜与已切割的第二晶圆2分离,工艺简单,成本较低。可以理解的是,在其它实施例中,为使得第三支撑板6具有较好支撑力,同时也较服帖,能与已切割的第二晶圆2的每个切割块物理接触,第三支撑板6可以为UV膜和玻璃基板,UV膜具有相对的第一表面和第二表面,其中,第一表面与已切割的第二晶圆2接触,第二表面与玻璃基板接触。需要说明的是,对于后一实施例,其中的UV膜的厚度可以较薄。
然后,参照图10与图11所示,对第一晶圆1进行减薄,并在减薄面上贴切割用膜7,去除所述第三支撑板6,沿第二晶圆2的切割道对第三晶圆3以及第一晶圆1进行切割形成MEMS器件。
参照图9与图10所示,翻转第一晶圆1、第三晶圆3以及第二晶圆2形成的堆叠结构,以第二晶圆2及其减薄面上粘贴的第三支撑板6为支撑,对第一晶圆1的背面进行减薄,上述减薄工艺参照现有技术中的工艺。
可以理解的是,第三支撑板6在对第一晶圆1进行减薄过程中,提高了已减薄且分割的第二晶圆2的支撑力。
第一晶圆1减薄完成后,去除第三支撑板6,参照图11所示,再次翻转堆叠结构,第二晶圆2、第三晶圆3以及第一晶圆1自上而下依次排布,沿第二晶圆2的切割道自上而下依次切割第三晶圆3、第一晶圆1,形成分立的晶粒,去除第一晶圆1背面的切割用膜7,形成各个分立的MEMS器件。对第三晶圆3以及第一晶圆1的切割参照现有的工艺。
可以理解的是,本步骤执行完后,分割三片晶圆堆叠结构,得到两个晶粒,即得到两个MEMS器件。其它实施例中,分割三片晶圆堆叠结构,也可以得到其它数目的晶粒,即得到其它数目的MEMS器件。
上述实施例中,如图1所示,首先将第三晶圆3与用于形成MEMS器件衬底的第一晶圆1键合形成两层晶圆的堆叠结构,在用于形成MEMS器件盖层的第二晶圆2与上述两层晶圆堆叠结构键合时,该第二晶圆2已经过减薄。其它实施例中,也可以首先将第三晶圆3与用于形成MEMS器件盖层的第二晶圆2键合形成两层晶圆的堆叠结构,在用于形成MEMS器件衬底的第一晶圆1与上述两层晶圆堆叠结构键合时,该第一晶圆1已经过减薄。对于后一实施例,第一晶圆1在减薄过程中时,其正面粘合有第一支撑板4,减薄完成后的减薄面上设置有对准标记22,具有对准标记22的减薄面上粘贴有第二支撑板5。去除第一支撑板4,对准标记22在将第一晶圆1键合在第二晶圆2与第三晶圆3形成的双层堆叠结构上时,用于与该双层堆叠结构对准。上述键合过程中,由于第一晶圆1已减薄,因而其减薄面上粘贴的第二支撑板5可以起到提高第一晶圆1的支撑力的作用。翻转第二晶圆2、第三晶圆3、第一晶圆1形成的三层堆叠结构,使得第一晶圆1朝上,去除第二支撑板5,对已减薄的第一晶圆1进行切割,后在减薄面上粘贴第三支撑板6,该第三支撑板6仍保证已被分割的第一晶圆1为一整体。在第三支撑板6的支撑下,对第二晶圆2进行减薄,之后在第二晶圆2的减薄面粘贴切割用膜7,沿第一晶圆1的切割道对第二晶圆2与第三晶圆3进行切割,以形成多个MEMS器件(晶粒)。
可以看出,后一实施例中,第一晶圆1的切割,以及沿第一晶圆1的切割道依次切割第三晶圆3、第二晶圆2时,MEMS结构都处于翻转状态,因而与后一实施例相比,图1至图11实施例中的形成MEMS器件的方法,可以降低上述翻转过程中造成的MEMS器件的可动电极以及其它部件损坏的几率。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。
Claims (12)
1.一种MEMS器件的形成方法,其特征在于,包括:
分别提供第一晶圆、第二晶圆以及第三晶圆,所述第一晶圆用于形成MEMS器件的衬底,其正面具有MOS晶体管、金属互连结构以及第一沟槽;所述第二晶圆用于形成MEMS器件的盖层,其正面具有第二沟槽;
将第一晶圆与第二晶圆之一与第三晶圆的正面键合;
对键合后的第三晶圆进行切边、后进行减薄工序;
在所述减薄后的第三晶圆上至少制作可动电极;
在第一晶圆与第二晶圆中的另一个的正面粘贴第一支撑板,后进行背面减薄并在减薄面上制作对准标记,后在具有所述对准标记的减薄面上粘贴第二支撑板;
去除所述第一支撑板,利用所述对准标记将所述第一晶圆与第二晶圆中减薄的该个与所述第三晶圆键合形成晶圆堆叠结构,使得可动电极悬浮于所述第一沟槽与第二沟槽形成的空腔内;
去除所述第二支撑板,对具有对准标记的该个晶圆进行切割,后在被切割的晶圆的背面粘贴第三支撑板;
对第一晶圆与第二晶圆中未减薄的该个晶圆进行减薄,并在减薄面上贴切割用膜,去除所述第三支撑板,沿已切割的该个晶圆的切割道对所述晶圆堆叠结构进行切割形成MEMS器件。
2.根据权利要求1所述的形成方法,其特征在于,所述第一支撑板为玻璃基板,所述玻璃基板的尺寸与第一晶圆与第二晶圆的尺寸匹配。
3.根据权利要求1所述的形成方法,其特征在于,所述第一基板的粘贴采用紫外固化胶。
4.根据权利要求1所述的形成方法,其特征在于,所述第二支撑板为玻璃基板,所述玻璃基板的尺寸与第一晶圆与第二晶圆的尺寸匹配。
5.根据权利要求1所述的形成方法,其特征在于,所述第三支撑板为UV膜。
6.根据权利要求1所述的形成方法,其特征在于,所述第一晶圆的正面还形成有固定电极,在减薄后的第三晶圆上制作可动电极前,还在所述第三晶圆上制作第一穿硅通孔导电结构、第二穿硅通孔导电结构以及第三穿硅通孔导电结构,分别用于将固定电极、可动电极以及MOS晶体管的信号引出。
7.根据权利要求6所述的形成方法,其特征在于,在减薄后的第三晶圆上还制作有若干焊垫,所述若干焊垫分别与所述固定电极、可动电极以及MOS晶体管电连接。
8.根据权利要求7所述的形成方法,其特征在于,所述若干焊垫分别位于所述第一穿硅通孔导电结构、第二穿硅通孔导电结构以及第三穿硅通孔导电结构上。
9.根据权利要求1所述的形成方法,其特征在于,具有对准标记的该个晶圆为第二晶圆。
10.根据权利要求1所述的形成方法,其特征在于,所述对准标记为凹槽,采用光刻、刻蚀法形成。
11.根据权利要求1所述的形成方法,其特征在于,还在所述减薄后的第三晶圆上制作第一凸起,粘贴第一支撑板前,还在未与第三晶圆键合的第一晶圆或第二晶圆上制作第二凸起,形成所述晶圆堆叠结构时,所述第一凸起与第二凸起键合形成用于可动电极悬浮的空腔。
12.根据权利要求11所述的形成方法,其特征在于,所述第一凸起与所述第二凸起中的一个的材质为铝,另一个材质为锗。
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