CN101246893A - 具有高传导面积的集成电路封装体及其制作方法 - Google Patents

具有高传导面积的集成电路封装体及其制作方法 Download PDF

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CN101246893A
CN101246893A CNA2007100057334A CN200710005733A CN101246893A CN 101246893 A CN101246893 A CN 101246893A CN A2007100057334 A CNA2007100057334 A CN A2007100057334A CN 200710005733 A CN200710005733 A CN 200710005733A CN 101246893 A CN101246893 A CN 101246893A
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integrated circuit
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刘建宏
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XinTec Inc
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Abstract

本发明提供一种具有高传导面积的集成电路封装体及其制作方法。上述集成电路封装体，包含集成电路芯片，具有上表面及下表面，且该上表面形成有感光元件；焊盘，形成于该集成电路芯片的上表面上，且电连接该感光元件；以及导电层，形成于该集成电路芯片的侧壁上，且包覆该焊盘的边缘，以电连接该焊盘。在上述集成电路封装体中，由于导电层会包覆焊盘的侧壁，使得导电层会同时接触焊盘的上表面、侧壁及下表面，以增加导电层与焊盘的接触面积及其结构强度。

Description

具有高传导面积的集成电路封装体及其制作方法
技术领域
本发明有关于集成电路封装体，特别是一种具有改善的导电性及稳固性的集成电路封装体及其制作方法。
背景技术
在集成电路装置的制造工艺中，集成电路必须经过封装步骤处理后，以适用于各种不同的应用领域，例如，计算机、手机或数码相机等。因此，集成电路封装体的结构也直接影响最终集成电路装置的性能。
图1显示一种公知的集成电路封装体1。在图1中，感光元件4形成于集成电路芯片2的上方，且电连接焊盘6。接着，保护层8形成在上述集成电路芯片2上方，且覆盖焊盘6。导电层10形成于集成电路芯片2的侧壁上，且电连接焊盘6，如图1所示。在公知的集成电路封装体中，导电层仅与焊盘的侧壁接触，因此，导电层与焊盘之间的导电性并不好。再者，由于导电层仅与焊盘的侧壁接触，使得导电层与焊盘之间的结构强度较弱。
因此，亟需一种新的集成电路封装体及其制作方法，以增加导电层与焊盘的接触面积及其结构强度。
发明内容
有鉴于此，本发明的目的是提供一种具有高传导面积的集成电路封装体。上述集成电路封装体包含：集成电路芯片，具有上表面及下表面，且该上表面形成有感光元件；焊盘，形成于该集成电路芯片的上表面上，且电连接该感光元件；以及导电层，形成于该集成电路芯片的侧壁上，且包覆该焊盘的边缘，以电连接该焊盘。
如上所述的具有高传导面积的集成电路封装体，还包含保护层，形成于部分该焊盘的上表面上方。
如上所述的具有高传导面积的集成电路封装体，还包含胶材，形成于该集成电路芯片的下表面及部分焊盘的下表面上。
如上所述的具有高传导面积的集成电路封装体，其中该导电层同时接触该焊盘的暴露的上表面、侧壁及其下表面，以包覆该焊盘的边缘。
如上所述的具有高传导面积的集成电路封装体，还包含阻焊膜，形成于该导电层上，且暴露部分导电层。
如上所述的具有高传导面积的集成电路封装体，还包含焊料球体，形成于该暴露的部分该导电层上。
本发明的另一目的是提供一种具有高传导面积的集成电路封装体的制作方法。上述集成电路封装体的制作方法包括：提供具有上表面及下表面的集成电路芯片，且该上表面形成有感光元件；形成焊盘于该集成电路的该上表面上，且电连接该感光元件；以及在该集成电路芯片的侧壁上形成导电层，且包覆该焊盘的边缘，以电连接该焊盘。
如上所述的具有高传导面积的集成电路封装体的制作方法，还包括覆盖保护层于该焊盘的上表面上。
如上所述的具有高传导面积的集成电路封装体的制作方法，还包括：移除部分的该集成电路芯片，以暴露该焊盘的下表面；通过胶材，贴附第二基板于该集成电路芯片的下表面上，其中该胶材覆盖该焊盘的暴露的下表面；以及形成凹槽，以暴露该保护层、该焊盘及该胶材的侧壁。
如上所述的具有高传导面积的集成电路封装体的制作方法，其中在形成该凹槽之后，还包括进行等离子体蚀刻的步骤，以移除部分该保护层及部分该胶材，且暴露该焊盘的部分上表面及下表面。
如上所述的具有高传导面积的集成电路封装体的制作方法，在移除部分该保护层及该胶材的步骤之后，还包括形成该导电层于该焊盘的暴露的上表面、侧壁及其下表面上，以包覆该焊盘的该边缘。
如上所述的具有高传导面积的集成电路封装体的制作方法，还包括形成焊料球体于该导电层上。
上述集成电路封装体中，由于导电层会包覆焊盘的侧壁，使得导电层会同时接触焊盘的上表面、侧壁及下表面，以增加导电层与焊盘的接触面积，进而增加导电层与焊盘之间的导电性(conductivity)。再者，由于上述导电层会包覆焊盘的侧壁，因此，也可以增加导电层与焊盘接触部位的结构强度，进而增加集成电路封装体的机械强度以及稳固性。
附图说明
图1显示公知集成电路封装体的剖面图；以及
图2A-图2G显示根据本发明的实施例制作集成电路封装体的剖面图。
其中，附图标记说明如下：
现有技术的附图标记
1～集成电路封装体； 2～集成电路芯片；4～感光元件；
6～焊盘；           8～保护层；      10～导电层。
本发明的附图标记
102～集成电路芯片； 104～中央区域；  106～***区域；
107～上表面；       108～焊盘；      109～下表面；
110～感光元件；     112～保护层；    1121～保护层侧壁；
114～黏着层；       116～第一基板；  118～间隙；
120～开口；         122～胶材；      1221～胶材侧壁；
124～第二基板；     126～绝缘层；    128～凹槽；
130～导电层；32～阻焊膜；134～焊料球体；140～集成电路封装体。
具体实施方式
接下来以实施例并配合附图以详细说明本发明，在附图或描述中，相似或相同部分使用相同的符号。在附图中，实施例的形状或厚度可扩大，以简化或是方便标示。将以描述说明附图中元件的部分。可了解的是，未描绘或描述的元件，可以是具有各种本领域技术人员所知的形式。此外，当叙述一层位于基材或是另一层上时，此层可直接位于基材或是另一层上，或是其间亦可以有中间层。
图2A-图2G显示根据本发明实施例制作集成电路封装体的剖面图。在图2A中，显示集成电路芯片102的俯视图，且在上述集成电路芯片102的上表面区分中央区104及周边区106。图2B显示沿着图2A的A至A’的剖面图。在图2B中，提供具有上表面107及下表面109的集成电路芯片102，且设置感光元件110于集成电路芯片102上方的中央区104。又如图2B所示，形成焊盘108于集成电路芯片102上方的周边区106，且电连接感光元件110。上述焊盘108会围绕各中央区104的感光元件110，如图2A所示。
如图2C所示，形成保护层(Dam)112于集成电路芯片102的上表面107，且覆盖焊盘108，以保护焊盘108，而避免焊盘108的氧化现象。接着，通过黏着剂114，贴附第一基板116于集成电路芯片102的上方，且形成间隙118于第一基板116与集成电路芯片102之间。上述第一基板116也可以称为盖板。
在优选实施例中，上述第一基板116优选可以是玻璃、石英、蛋白石、塑料或其它合适的透明基板。上述保护层112优选可以是聚酰亚胺树脂(polyimide；PI)、环氧树脂(epoxy)或其它合适的绝缘材料。在实施例中，上述黏着剂114优选可以是包含环氧树脂的黏着材料。
又如图2C所示，使用光刻及蚀刻步骤，沿着切开个别晶粒的预定切割线，移除部分集成电路芯片102，且形成开口120，以切开个别的晶粒。上述开口120会暴露焊盘108的底部表面及保护层112。上述蚀刻步骤优选可以是干蚀刻或湿蚀刻。
在上述切开个别的晶粒之前，也可选择性地进行研磨步骤，以薄化集成电路芯片102的厚度，以利于切开晶粒步骤的进行。
在图2D中，通过胶材122，贴附第二基板124于集成电路芯片102的下表面上109。接着，形成绝缘层126于第二基板124的下表面上。上述胶材122优选可以是包含环氧树脂、聚酰亚胺树脂或其它合适的材料。上述第二基板124可以是与上述第一基板相似材质的基板，值得注意的是，第二基板124也可以是其它合适材料的不透明基板，且第二基板124可作为集成电路芯片102的承载基板。
如图2E中，通过刻痕装置，沿着切开个别晶粒的预定切割线，进行刻痕步骤，以形成凹槽128，且暴露胶材122、焊盘108、保护层112的侧壁及第一基板116的表面。接着，进行移除部分保护层112及胶材122的步骤，以暴露焊盘108的部分上表面及下表面。
在优选实施例中，通过上述移除步骤，优选例如是使用氧气(O2)或四氟化碳(CF4)气体的等离子体蚀刻步骤，移除凹槽128内部分保护层112及部分胶材122，使得胶材122的侧壁1221及保护层112的侧壁1121会往后缩，以暴露焊盘108的上表面及下表面，如图2E所示。
在图2F中，接着，形成导电层130于上述凹槽128之中，且电连接焊盘108。在优选实施例中，通过例如溅射(sputtering)、无电镀(electroless plating)或电镀(plating)，在绝缘层126的下表面上形成例如是铜、铝、镍或其它合适的金属层，且由第二基板124及集成电路芯片102的侧壁，延伸至焊盘108的下表面、侧壁及上表面，以包覆焊盘108的侧壁。接着，以光刻及蚀刻工艺图案化金属层，以形成导电层130。在另一实施例中，也可以是使用溅射的方式形成金属层于绝缘层126的下表面上，接着再进行无电镀(也可以称为化学电镀)，形成金属层于凹槽128之中。
值得注意的是，由于上述导电层130会包覆焊盘108的侧壁，使得导电层130会同时接触焊盘108的上表面、侧壁及下表面，以增加导电层130与焊盘108的接触面积，进而增加导电层130与焊盘108之间的导电性。
又如图2F所示，形成阻焊膜132于上述导电层130上，且暴露部分导电层130。接着，形成焊料球体134于暴露的导电层130上。在完成上述步骤后，接着，通过切割刀片沿着个别晶粒的预切割线，分割成个别晶粒，以完成集成电路封装体140，如图2G所示。
在图2G中，提供上方形成有感光元件110及焊盘108的集成电路芯片102，且保护层112覆盖于焊盘108上。又如图2G所示，第一基板116设置于集成电路芯片102的上方，以及通过胶材122贴附第二基板124于集成电路芯片102的下表面上。导电层130形成于集成电路芯片102的侧壁上，且包覆焊盘108的侧壁，以电连接上述焊盘108，如图2G所示。之后，阻焊膜覆盖部分导电层130，以暴露部分导电层。且，焊料球体134形成在暴露的导电层130上，电连接导电层130，以完成集成电路封装体140。
值得注意的是，由于导电层会包覆焊盘的侧壁，使得导电层会同时接触焊盘的上表面、侧壁及下表面，以增加导电层与焊盘的接触面积，进而增加导电层与焊盘之间的导电性。再者，由于上述导电层会包覆焊盘的侧壁，因此，也可以增加导电层与焊盘接触部位的结构强度，进而增加集成电路封装体的机械强度以及其稳固性。
虽然本发明已以优选实施例公开如上，然其并非用以限制本发明，本领域技术人员，在不脱离本发明的精神和范围内，当可作此许的变更与修饰，因此本发明的保护范围当视后附的权利要求书所界定的范围为准。

Claims (12)

1. 一种具有高传导面积的集成电路封装体，包含：
集成电路芯片，具有上表面及下表面，且该上表面形成有感光元件；
焊盘，形成于该集成电路芯片的上表面上，且电连接该感光元件；以及
导电层，形成于该集成电路芯片的侧壁上，且包覆该焊盘的边缘，以电连接该焊盘。
2. 如权利要求1所述的具有高传导面积的集成电路封装体，还包含保护层，形成于部分该焊盘的上表面上方。
3. 如权利要求2所述的具有高传导面积的集成电路封装体，还包含胶材，形成于该集成电路芯片的下表面及部分焊盘的下表面上。
4. 如权利要求3所述的具有高传导面积的集成电路封装体，其中该导电层同时接触该焊盘的暴露的上表面、侧壁及其下表面，以包覆该焊盘的边缘。
5. 如权利要求1所述的具有高传导面积的集成电路封装体，还包含阻焊膜，形成于该导电层上，且暴露部分导电层。
6. 如权利要求5所述的具有高传导面积的集成电路封装体，还包含焊料球体，形成于该暴露的部分该导电层上。
7. 一种具有高传导面积的集成电路封装体的制作方法，包括：
提供具有上表面及下表面的集成电路芯片，且该上表面形成有感光元件；
形成焊盘于该集成电路的上表面上，且电连接该感光元件；以及
形成导电层于该集成电路芯片的侧壁上，且包覆该焊盘的一边缘，以电连接该焊盘。
8. 如权利要求7所述的具有高传导面积的集成电路封装体的制作方法，还包括覆盖保护层于该焊盘的上表面上。
9. 如权利要求8所述的具有高传导面积的集成电路封装体的制作方法，还包括：
移除部分的该集成电路芯片，以暴露该焊盘的下表面；
通过胶材，贴附第二基板于该集成电路芯片的下表面上，其中该胶材覆盖该焊盘的暴露的下表面；以及
形成凹槽，以暴露该保护层、该焊盘及该胶材的侧壁。
10. 如权利要求9所述的具有高传导面积的集成电路封装体的制作方法，其中在形成该凹槽之后，还包括进行等离子体蚀刻的步骤，以移除部分该保护层及部分该胶材，且暴露该焊盘的部分上表面及下表面。
11. 如权利要求10所述的具有高传导面积的集成电路封装体的制作方法，在移除部分该保护层及该胶材的步骤之后，还包括形成该导电层于该焊盘的暴露的上表面、侧壁及其下表面上，以包覆该焊盘的该边缘。
12. 如权利要求7所述的具有高传导面积的集成电路封装体的制作方法，还包括形成焊料球体于该导电层上。
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Cited By (3)

* Cited by examiner, † Cited by third party
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* Cited by examiner, † Cited by third party
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TWI375321B (en) * 2007-08-24 2012-10-21 Xintec Inc Electronic device wafer level scale packages and fabrication methods thereof
TWI360207B (en) 2007-10-22 2012-03-11 Advanced Semiconductor Eng Chip package structure and method of manufacturing
US9142586B2 (en) 2009-02-24 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
US8569894B2 (en) 2010-01-13 2013-10-29 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
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US9406658B2 (en) 2010-12-17 2016-08-02 Advanced Semiconductor Engineering, Inc. Embedded component device and manufacturing methods thereof
US8507316B2 (en) * 2010-12-22 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Protecting T-contacts of chip scale packages from moisture
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US9142695B2 (en) 2013-06-03 2015-09-22 Optiz, Inc. Sensor package with exposed sensor array and method of making same
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US9996725B2 (en) 2016-11-03 2018-06-12 Optiz, Inc. Under screen sensor assembly

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6153829A (en) * 1998-09-15 2000-11-28 Intel Corporation Split cavity wall plating for an integrated circuit package
US6566745B1 (en) * 1999-03-29 2003-05-20 Imec Vzw Image sensor ball grid array package and the fabrication thereof
IL133453A0 (en) * 1999-12-10 2001-04-30 Shellcase Ltd Methods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US7340181B1 (en) * 2002-05-13 2008-03-04 National Semiconductor Corporation Electrical die contact structure and fabrication method
CN100587962C (zh) * 2003-07-03 2010-02-03 泰塞拉技术匈牙利公司 用于封装集成电路器件的方法和设备
JP2005057067A (ja) * 2003-08-05 2005-03-03 Renesas Technology Corp 半導体装置およびその製造方法
JP4591222B2 (ja) * 2005-06-09 2010-12-01 セイコーエプソン株式会社 電気光学装置及び画像形成装置
US7394152B2 (en) * 2006-11-13 2008-07-01 China Wafer Level Csp Ltd. Wafer level chip size packaged chip device with an N-shape junction inside and method of fabricating the same

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* Cited by examiner, † Cited by third party
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