CN105489591A - 半导体封装及其制造方法 - Google Patents
半导体封装及其制造方法 Download PDFInfo
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- CN105489591A CN105489591A CN201510640726.6A CN201510640726A CN105489591A CN 105489591 A CN105489591 A CN 105489591A CN 201510640726 A CN201510640726 A CN 201510640726A CN 105489591 A CN105489591 A CN 105489591A
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Abstract
本发明公开一种设有电连接半导体封装的上部和下部的导电性路径的半导体封装及其制造方法。本发明的实施例的半导体封装包括:半导体芯片;基板,包括容纳半导体芯片的容纳部;包封材料,将半导体芯片和基板一体地塑封;贯穿布线,将基板沿上下方向贯穿;布线部,电连接半导体芯片和贯穿布线的一侧;外部连接部,与贯穿布线的另一侧电连接,可与外部电连接,其中,布线部的布线层与贯穿布线连接。
Description
技术领域
本发明涉及一种半导体封装及其制造方法,更为具体地,涉及一种具备电连接半导体的上部和下部的导电路径的半导体封装及其制造方法。
背景技术
随着半导体制造工艺的持续发展,半导体芯片的大小也不断缩小。近来,半导体芯片的尺寸变得非常小,以至于形成半导体封装时,为了电连接反而需要增加封装的大小。在这种发展过程中,所提出的半导体封装技术中的一个是扇出型封装(Pan-outPackage)。
并且,伴随着在扇出型封装的外侧区域形成上下垂直传输信号的图案结构,并上下层叠相同类型的封装或不同类型的封装,从而在同一封装面积中扩展存储容量或提高半导体的运行性能的技术,正在研发各种类型的半导体封装技术。
扇出型封装结构是指在半导体芯片的外周面配置将半导体芯片封装在电路板内部的嵌入式结构或半导体芯片的最终的输入和输出端的焊锡球,通常,为了设置电连接半导体封装的上部和下部的导电路径,在基板上形成导通孔(via-hole),并形成电连接导通孔和半导体芯片的金属再布线层。
现有的形成有导通孔的扇出型封装,为了连接半导体芯片的焊盘和导通孔,在形成有导通孔的基板上表面形成金属焊盘,同时为了连接外部基板和焊锡球,在基板的下表面形成金属焊盘。并且,在基板的上表面,在金属焊盘上表面形成第一绝缘层,并通过金属再布线层电连接半导体芯片的焊盘和导通孔,然后涂布第二绝缘层。
但是这种结构的基板上表面的金属焊盘具有一定厚度以上的段差,因此,为了均匀地形成第一绝缘层,需要涂布绝缘层,使其厚度厚于金属焊盘。由于需要形成较厚的绝缘层,在选择绝缘材料方面受限,而且在细间距的图案化方面也面临着受到限制的问题。
现有技术文献
专利文献
授权专利公报10-1362714(2014年2月13日公告)
发明内容
(一)要解决的技术问题
本发明的实施例涉及一种可制造成薄型的半导体封装及其制造方法。
并且,涉及一种在贯穿基板的贯穿布线与布线层之间不***另外的金属焊盘等,也能够层叠布线层的半导体封装及其制造方法。
(二)技术方案
根据本发明的一个方面,能够提供一种半导体封装,其包括:半导体芯片;基板,包括容纳所述半导体芯片的容纳部和在所述容纳部的外侧沿上下方向贯穿的导通孔;包封材料,将所述半导体芯片和所述基板一体地塑封;贯穿布线,在所述导通孔的内周面沿上下方向延伸;贯穿部件,容纳在所述贯穿布线内部;布线部,包括电连接所述半导体芯片和所述贯穿布线的一侧的布线层;以及外部连接部,与所述贯穿布线的另一侧电连接,可与外部电连接。
与所述布线层连接的所述贯穿布线的端部可与所述基板的一面设置在同一的平面上。
与所述布线层连接的所述贯穿布线的端部可设置成在+20μm至-20μm的范围内从所述基板的一面突出或凹陷形成,或者与所述基板的一面设置在同一平面上。
所述布线部层叠在所述半导体芯片、所述基板和所述包封材料上,层叠有所述布线部的所述半导体芯片、所述基板和所述包封材料的一面设置在同一平面上,所述布线部可包括:第一绝缘层,层叠在所述半导体芯片、所述基板和所述包封材料上,露出所述半导体芯片的信号垫和所述贯穿布线;布线层,设置在所述第一绝缘层上,电连接所述信号垫和所述贯穿布线;第二绝缘层,设置在所述第一绝缘层和所述布线层上。
所述第一绝缘层包括分别露出所述信号垫和所述贯穿布线的开口部,所述布线层可填充所述第一绝缘层的开口部,并与所述信号垫和所述贯穿布线连接。
所述贯穿部件可由非导电性树脂制成。
所述贯穿部件可由导电性膏制成。
所述贯穿布线可由导电性膏制成。
露出所述贯穿布线的所述第一绝缘层的开口部可设置成其内部容纳所述导通孔的棱角。
所述半导体封装,还可包括焊盘部,其一面与所述贯穿布线粘贴,另一面与所述外部连接部粘贴,并由导电性物质制成。
粘贴有所述焊盘部的贯穿布线的端部可从所述基板突出,并向外侧延伸。
所述基板与所述贯穿布线的端部之间可夹杂有金属层。
根据本发明的另一方面,可提供一种半导体封装的制造方法,所述制造方法如下:准备形成有容纳半导体芯片的容纳部和在所述容纳部的外侧沿上下方向贯穿的导通孔的基板,在所述导通孔的内周面沿上下方向形成贯穿布线,在所述贯穿布线的中空部填充贯穿部件,对所述基板的一面进行平坦化,使所述基板和所述贯穿布线的一端部位于同一平面上,在所述容纳部中容纳半导体芯片,在所述半导体芯片和所述基板上层叠绝缘层,所述绝缘层以露出所述半导体芯片的信号垫和所述贯穿布线的方式层叠,在所述绝缘层上形成布线层,以便将所述信号垫和所述贯穿布线电连接。
形成所述贯穿布线的方法可以是,利用在所述基板的两面上进行沉积或者电镀工艺来使所述贯穿布线包围所述导通孔的内周面。
所述贯穿部件可以通过填充导电性膏来设置。
所述贯穿部件可以通过填充非导电性树脂或者非导电性油墨来设置。
在填充所述贯穿部件后,可层叠所述基板的一面上所设置的贯穿布线和所述贯穿部件上设置的导电性物质的焊盘部。
所述半导体制造方法,还包括:在设置在所述基板的一面上的所述焊盘部粘贴干膜(dryfilm)并图案化(patterning),并去除除了粘贴有所述干膜的部分之外的其余部分的所述焊盘部和所述贯穿布线的蚀刻(etching)工艺。
所述半导体制造方法,还包括将与通过所述图案化而所述焊盘部存在的面相对的面进行平坦化的工艺,通过所述平坦化工艺,可使所述基板、所述贯穿布线和所述贯穿部件设置在同一平面上。
根据本发明的又一方面,可提供一种半导体封装,其包括:半导体芯片;基板,包括容纳所述半导体芯片的容纳部;包封材料,将所述半导体芯片和所述基板一体地塑封;贯穿布线,将所述基板沿上下方向贯穿;贯穿部件,填充在所述贯穿布线的中空部;布线部,电连接所述半导体芯片和所述贯穿布线的一侧;以及外部连接部,与所述贯穿布线的另一侧电连接,可与外部电连接,所述半导体芯片、所述基板和所述包封材料设置在同一平面上,所述布线部包括:第一绝缘层,层叠在所述半导体芯片、所述基板和所述包封材料上,露出所述半导体芯片的信号垫和所述贯穿布线;布线层,设置在所述第一绝缘层上,电连接所述信号垫和所述贯穿布线;第二绝缘层,设置在所述第一绝缘层和所述布线层上,与所述布线部连接的所述贯穿布线的端部与所述基板设置在同一平面上,所述布线部的布线层包括以与所述贯穿布线接触的方式设置的第一半导体封装和第二半导体封装,所述第一半导体封装和所述第二半导体封装上下设置,从而形成封装体叠层(package-on-package),位于下方的所述第一半导体封装的第二绝缘层以露出所述布线层的一部分的方式设置,位于上方的所述第二半导体封装的外部连接部以与所述第一半导体封装的布线层电连接的方式设置。
(三)有益效果
本发明的实施例的半导体封装及其制造方法,可将设置在半导体芯片与布线层之间的绝缘层的厚度变薄,由此能够制造薄型封装,使绝缘层材料的可选择范围变广。因此,根据各种应用产品的需求能够选择具有合适的可靠性的材料,从而能够实现细间距的图案化。
并且,通过使半导体芯片的活性表面与整个堆焊层之间的厚度最小化,从而能够提高检测灵敏度。
附图说明
图1是本发明的实施例的半导体封装的剖视图。
图2是沿A-A线切割图1的半导体封装的俯视图。
图3是表示本发明的另一个实施例的基板的俯视图。
图4是表示本发明的第一实施例的贯穿布线和布线层的结合结构的放大图。
图5是表示本发明的第二实施例的贯穿布线和布线层的结合结构的放大图。
图6是表示本发明的第三实施例的贯穿布线和布线层的结合结构的放大图。
图7至图21是表示本发明的实施例的半导体封装的制作工艺的剖视图。
图22是层叠多个图1所示的半导体封装的封装叠层体的剖视图。
附图说明标记
100:半导体封装110:半导体芯片
111:活性表面112:非活性表面
113:信号垫120:基板
121:容纳部122:导通孔
123:贯穿布线124:贯穿部件
125:焊盘部130:布线部
131:第一绝缘层132:布线层
133:第二绝缘层140:包封材料
150:外部连接部160:第一载体
161:第一粘贴部170:第二载体
171:第二粘贴部
具体实施方式
最优选实施方式
下面,参照附图对本发明的实施例进行详细说明。以下介绍的实施例只是为了向本发明所属领域的普通技术人员完整地说明本发明的范围而提供的,本发明并不限定于在下面说明的实施例。本发明还可以以其他形式具体化。并且,为了明确说明本发明,附图中省略了与说明无关的部分,且为了便于说明本发明,附图中各组成构件的大小可以放大表示。并且,在整个说明书中相同的附图标记表示相同的组成构件。并且,下面使用的术语中的“和/或”包括举出的项目中的某一个或一个以上的所有组合。
参考图1至图4,说明本发明的实施例的半导体封装100。图1是本发明的实施例的半导体封装100的剖视图,图2是沿A-A线切割图1的半导体封装100的俯视图。并且,图3是表示本发明的另一个实施例的基板的俯视图,图4是表示本发明的第一实施例的贯穿布线123和布线层132的结合结构的放大图。
本发明的实施例的半导体封装100包括:基板120;半导体芯片110,容纳在基板120;贯穿布线123,设置在半导体芯片110的外侧;布线部130,电连接半导体芯片110和贯穿布线123;外部连接部150,通过与贯穿布线123连接而与外部电路连接;包封材料140,塑封半导体芯片110和基板120。
基板120可以设置成绝缘基板。绝缘基板可包括绝缘物质,例如可以包括硅(silicon)、玻璃(glass)、陶瓷(ceramic)、塑料(plastic)或聚合物(polymer)。基板120可以设置成平板、圆形或多角形等多种形状。
基板120可包括容纳半导体芯片110的容纳部121。容纳部121可以以贯穿基板120的方式设置,并可位于基板120的中央部。容纳部121可设置成比半导体芯片110的宽度更宽,从而容纳半导体芯片110。此时,半导体芯片110和容纳部121之间可填充将要在后面叙述的包封材料140。并且,与图示不同,容纳部121可设置成一面不开放的凹槽。并且,设置成与半导体芯片110的宽度方向的形状相同,由此压入半导体芯片110。
参考图3,本发明的另一个实施例的基板120-1可以配置在半导体芯片110的外侧。并且,基板120-1可设置多个。虽然附图中仅示出半导体芯片110的两侧配置有两个基板120-1,与此不同地,也可以以包围半导体芯片110的方式设置4个基板。
此时,基板120-1的容纳部121-1可指相互隔开配置的基板之间的空间。即,在基板之间的空间可配置半导体芯片110。并且,后面将要说明的包封材料140可塑封基板120-1与半导体芯片110之间、基板和基板之间,并围绕基板的外侧进行塑封。
半导体芯片110可以是存储器芯片或逻辑芯片。作为一个例子,存储器芯片可以包括动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、闪存(flash)、相变随机存取存储器(PRAM)、可变电阻式存储器(ReRAM)、铁电随机存取存储器(FeRAM)、磁阻式随机存取存储器(MRAM)等。作为一个例子的逻辑芯片可以是控制存储器芯片的控制器。
半导体芯片110的一面可以是包括形成电路的活性区域的活性表面111。另一方面,半导体芯片110的背面可以是非活性表面112。与此不同地,半导体芯片110的两面可全部设置成活性表面。半导体芯片110的活性表面111设有多个用于与外部交换信号的信号垫113,信号垫113可由如铝Al的导电性物质膜形成。信号垫113可与半导体芯片110一体形成。
图1中示出了一个半导体芯片110,与此不同地,也可以是层叠两个以上的半导体芯片的形态。此时,层叠的半导体芯片可以是同一类型的产品或者是不同类型的产品。例如,一个半导体芯片可以是存储器芯片,另一个半导体芯片可以是逻辑芯片。层叠两个以上的半导体芯片的半导体封装可以是***芯片(systemonchip,SOC)或者***级封装(systeminpackage,SIP)。并且,多个半导体芯片沿宽度方向彼此相邻地或接触地配置。
为了将半导体封装100封装在主板(未示出)上或者与另一个芯片或封装进行电连接,需要将半导体芯片110与主板等之间进行电连接的电连接部。另一方面,为了将半导体封装100封装在比半导体芯片110的信号垫113的间距更宽区域的主板连接区域,可设置成电路向半导体芯片110的***扩展的形状的扇出型封装形状。
虽然图中未示出,主板包括印刷电路的印刷电路板(PrintedCircuitBoard)或者引线框架(LeadFlame)。并且,印刷电路板包括薄型的膜(Film)、玻璃(Glass)或者胶带(Tape)等。
为了形成扇出型封装的形状,本发明的实施例的半导体封装100可包括贯穿布线123,其设置在半导体芯片110的信号垫113的外侧,并可沿上下方向传输信号。贯穿布线123的一侧可与半导体芯片110电连接,另一侧可与外部连接部150电连接,外部连接部150可与主板或者另一个芯片或者封装电连接。
贯穿布线123可通过设置在基板120上的导通孔122而上下配置,并在半导体芯片110和主板等之间传输数据信号或功率信号等。导通孔122贯穿基板120,可沿着基板120的容纳部121的***设置多个。参考图2可知,沿容纳部121的***设置一列贯穿布线123。或者,与此不同地,可设置两列以上的贯穿布线123或者只在容纳部121的一侧设置贯穿布线123。
图4中示出贯穿布线123的一个实施例。贯穿布线123可以是沿着导通孔122的内周面设置的导电性物质,也可以是涂覆在导通孔122上的金属层。贯穿布线123可设置成圆柱形,贯穿布线123的中空部可容纳贯穿部件124。
贯穿部件124可填补或填充在贯穿布线123的中空部。并且,贯穿部件124可以是非导电性树脂(resin)或非导电性油墨(ink)。或者,贯穿部件124可以是导电性物质,例如可以是导电性膏。导电性膏包括银浆料(Agpaste)。
另一方面,贯穿布线123可设置成焊锡球等形态,并贯穿导通孔122,或者可以是填充在导通孔122中的阻焊油墨(Solderresistink)。
贯穿布线123的形成方法可包括无电解电镀、电解电镀、溅射或印刷等。
贯穿布线123的一侧(图1的上侧)可与基板120设置在同一平面上,另一侧(图1的下侧)可从基板120突出设置。从基板120突出的另一侧(或者下侧)可向外侧延伸并形成凸缘形状,在基板120与向外侧延伸的凸缘部之间可夹杂金属层120a。作为金属层120a的一个例子,可以包括铜箔(Cufoil)。
贯穿布线123的一侧可与布线部130的布线层132电连接,另一侧与外部连接部150电连接。另一方面,贯穿布线123与外部连接部150之间可夹杂由焊盘部125。焊盘部125可以是导电性物质,以便将贯穿布线123和外部连接部150电连接,并可将外部连接部150与贯穿布线123坚固地粘结。焊盘部125的形成方法包括无电解电镀、电解电镀、溅射或打印等。
布线部130可设置成电连接半导体芯片110的信号垫113与贯穿布线123的一侧。作为一个例子,布线部130可包括第一绝缘层131、第二绝缘层133以及布线层132。第一绝缘层131和第二绝缘层133由绝缘物质构成,以使布线层132绝缘。
第一绝缘层131可层叠在半导体芯片110的活性表面111、包封材料140和基板120的一个面上。并且,第一绝缘层131露出半导体芯片110的信号垫113和贯穿布线123,以使层叠在第一绝缘层131上的布线层132与信号垫113和贯穿布线123连接。另一方面,包封材料140以覆盖半导体芯片110和/或基板120的一面的方式设置时,第一绝缘层131也可不层叠在半导体芯片110和/或基板120上。
布线层132包括导电性物质,可通过再布线工艺层叠在第一绝缘层131上。布线层132形成再布线图案,从而可细化半导体芯片110的输出和输入端子,并可增加输出和输入端子的数量,使得能够形成扇出型结构。导电性物质可包括金属,例如可包括铜、铜合金、铝或者铝合金。
另一方面,布线层132可设置成预先制造的结构体,这种结构体可通过辊压、粘贴或者回流等方式粘贴到半导体芯片110、包封材料140以及基板120上。
第二绝缘层133层叠在第一绝缘层131和布线层132上,并将布线层132与外部绝缘。附图中示出了第二绝缘层133密封布线层132,但是也可以将第二绝缘层133设置成与此不同地、露出布线层132的一部分,可通过露出的布线层132与外部(主板、半导体芯片或者封装等)电连接。
本发明的实施例的半导体封装100的贯穿布线123的一端也可不突出在基板120上。并且,贯穿布线123和布线层132可通过直接连接而实现电连接。此时,连接的意思不仅是物理性的连接,而且还包括贯穿布线123和布线层132之间***导电性粘结层(例如,种子层)而连接的方式。
本发明的实施例的半导体封装100不需要额外的用于连接贯穿布线123和布线层132的金属焊盘。贯穿布线123的端部置有金属焊盘时,在基板120的一面和金属焊盘的上表面之间形成相当于金属焊盘的厚度大小的段差,具有第一绝缘层131的厚度需要设置成大于金属焊盘的高度的限制。通常,可用于连接布线和布线的金属焊盘的厚度约为50μm。
像这样金属焊盘位于贯穿布线123的端部时,半导体封装100的厚度变厚,这违背了追求轻薄短小的产品的目的。并且,为了形成厚的绝缘层,选择绝缘材料方面受到限制,并且在细间距的图案化方面也受到限制。
本发明的实施例的半导体封装100设置成去除额外的金属焊盘也能够使贯穿布线123与布线层132直接连接,从而可制造轻薄短小的产品,并且能够扩展产品的适用范围。作为一个例子,本发明的实施例的半导体封装100可适用于传感器装置,尤其可适用于指纹传感器。
包括指纹传感器的传感器装置,可提高检测灵敏度的方法是在半导体芯片110的活性表面111上最小化所有积聚层之间的厚度。本发明的实施例的半导体封装100,可减少第一绝缘层131的厚度,因此用于指纹传感器等上的利用率高。
另一方面,贯穿布线123的上侧端部可相对于基板120的上部面微微(约为20μm以下)突出或凹陷。即,贯穿布线123的上侧端部可在+20μm至-20μm的范围内从基板的上部面突出或与基板的上部面在同一平面上或凹陷。贯穿布线123从基板120突出的高度为20μm以内时,不产生前面提及的在选择绝缘层材料方面受限制的问题,且也不影响细间距的图案化。并且,贯穿布线123从基板120凹陷的深度为20μm以内时,在填充布线层132凹陷部分的方面也不会存在问题。
外部连接部150可连接在贯穿布线123的另一侧,并封装在外部基板(未图示)上,或者可与另一个半导体芯片或者封装等电连接。外部连接部150可以是焊锡球、焊料凸点或者导电球。导电球可以由铜(Cu)、金(Au)、镍(Ni)、铝(Al)、银(Ag)或者包括这些金属中的一种以上金属的合金组成。
包封材料140可密封并一体化基板120和半导体芯片110。包封材料140可包括绝缘物质,例如可包括环氧塑封料(epoxymoldcompound,EMC)或者密封剂(encapsulant)。包封材料140可填充半导体芯片110和基板120之间,并包覆设置基板120的外侧面,从而能够从外部保护基板。
包封材料140可在流动性状态下被注入,然后在高温环境下被固化。作为一个例子,可包括加热包封材料140的同时进行加压的过程,此时进一步增加真空工艺,从而可去除包封材料140内部的气体等。并且,包封材料140可通过涂覆或印刷等方法设置,包封材料140的塑封方法可使用相关领域中通常使用的各种技术。
包封材料140的一面可设置成露出半导体芯片110的信号垫和贯穿布线123的一端部。附图中示出了包封材料140的一面和半导体芯片110的活性表面111以及基板120的一面设置在同一平面上。包封材料140平坦化的工艺可包括磨削、打磨或蚀刻等。
并且,包封材料140的另一面覆盖半导体芯片110的非活性表面112,从而能够气密并牢固地密封半导体芯片110。或者,根据所需的半导体封装100的特性,可设置成露出半导体芯片110的非活性表面。作为一个例子,包封材料140的一面与半导体芯片110的非活性表面112设置在同一平面上,从而能够利于减小半导体封装100的厚度和半导体芯片110的散热。
图5是表示本发明的第二实施例的贯穿布线123和布线层132-1的结合结构的放大图。
参考图5,第一绝缘层131-1可形成为露出所有贯穿布线123。为了连接布线层132-1和贯穿布线123,第一绝缘层131-1可设置有开口部,开口部的宽幅可设置成大于基板120的导通孔122的外径。布线层132-1在形成图案的过程中填充于第一绝缘层131-1的开口部,因此贯穿布线123的端部的整个面与布线层132-1的接触。比较图4和图5,贯穿布线123和布线层132-1的接触面积不同。贯穿布线123和布线层132-1的接触面积越大,越能提高电信号传输的可靠性。
图6是表示本发明的第三实施例的贯穿布线123-1和布线层132的结合结构的放大图。
参考图6,贯穿布线123-1可填充导通孔122。作为一个例子,贯穿布线123-1可以是填充导通孔122的导电性膏。本发明的第三实施例的贯穿布线123-1使用导电性膏,从而能够减少制造成本,并简化制造工艺。
图7至图21是表示本发明的实施例的半导体封装100的制造工艺的剖视图。
图7示出了提供形成有容纳部121的基板120的过程。基板120可包括绝缘物质。例如,可包括硅、玻璃、陶瓷、塑料或聚合物。基板120可以设置成平板、也可设置成圆形或多边形形状。
容纳部121是形成容纳半导体芯片110的空间,可设置成对应于半导体芯片110的形状的形状。作为一个例子,容纳四边形的半导体芯片110的情况下,容纳部121的宽度方向的形状可以设置成四边形。并且,容纳部121可贯穿基板120。或者,基板120还可以设置成一面不开放的凹槽。
在基板120的两面上可层叠金属层120a。例如,金属层120a可设置成铜箔(Cufoil)。
图8示出了形成导通孔122的过程。导通孔122沿基板120的上下方向贯穿,并可设置在容纳部121的***。导通孔122的剖面可以是圆形或者其他形状。导通孔122可沿容纳部121的周围设置多个,与图8不同地,容纳部121的***的一个方向上可贯穿两个以上的导通孔122。
图7的形成容纳部121的过程和图8的形成导通孔122的过程可同时进行,或者也可以先进行某一个过程。并且,与附图不同地,可先形成导通孔122,然后形成容纳部121。
形成容纳部121和导通孔122的工艺可以利用布线工艺、模具切割加工工艺、蚀刻工艺、钻孔工艺或激光烧蚀(laserablation)工艺等。
图9示出在导通孔122中形成贯穿布线123的过程。贯穿布线123可由导电性物质组成,可包括金属。例如,可包括铜、铜合金、铝或者铝合金。贯穿布线123可以通过无电解电镀、电解电镀、溅射或打印等工艺填补或填充到导通孔122中。作为一个例子,可以是包覆设置导通孔122内面的金属涂覆层,其内部可形成贯穿孔。作为另一个例子,可以是填充到导通孔122中的导电性膏或者阻焊油墨(Solderresistink)。
图9中示出了贯穿布线123的两侧覆盖基板120的两个面。这是因为利用电镀或溅射等工艺时贯穿布线123可层叠在基板120的露出的面上。
图10示出贯穿布线123的贯穿孔中填充贯穿部件124的过程。贯穿部件124可包括导电性物质或非导电性物质。贯穿部件124为导电性物质时,可通过将具有流动性的导电性膏填充贯穿布线123的贯穿孔中后进行固化来形成。导电性膏可以是金属粉末和/或碳粉末和液态树脂(resin)的混合物,可以由涂覆有银(Ag)、焊锡(SnAg)以及金(Au)中的一种以上的铜(Cu)设置。或者,贯穿部件124可以是非导电性树脂,可填充在贯穿布线123的中空部。贯穿部件124包括固化式和烧结式,可通过印刷、电镀、喷射(Jetting)方法填充。
另一方面,填充贯穿部件124后通过平坦化工艺可使贯穿布线123和贯穿部件124形成平坦面。
图11示出贯穿布线123的两侧形成焊盘部125(125a、125b)的过程。焊盘部125可包括导电性物质,例如,可包括金属。焊盘部125可设置成改善贯穿布线123和外部连接部150的电接触,例如可以改善接触角度和润湿性。焊盘部125可利用沉积、无电解电镀、电解电镀、溅射或打印等工艺层叠在贯穿布线123和贯穿部件124上。
如图10所示,焊盘部125可全部层叠在基板120的两面上所层叠的贯穿布线123上,也可以只层叠在基板120的两面中的某一面上所层叠的贯穿布线123上。另一方面,形成焊盘部125的工艺是选择性(optionally)的,可根据情况而省略。
图12示出了去除贯穿布线123和焊盘部125a的一部分的过程。在基板120的上表面上可以仅留贯穿部件124,去除覆盖着焊盘部125a和基板120的上表面的贯穿布线123和金属层120a。并且,在基板120的下表面上可留下一定范围,去除覆盖着焊盘部125b和基板120的上表面的贯穿布线123和金属层120a。
作为一个例子,在基板120的下表面,可通过只在要留下焊盘部125b的部位粘贴干膜(dryfilm)(未示出),并进行图案化,然后经过图案蚀刻工艺(patternetching),去除没有粘贴干膜的部位的焊盘部125b和贯穿布线123以及金属层120a。
图13示出平坦化基板120的上表面的过程。平坦化工艺可使用磨削、打磨或蚀刻等。可通过平坦化工艺,将基板120上表面和贯穿布线123以及贯穿部件124形成在同一平面上。与图12所示不同,在基板120上表面留有贯穿布线123、金属层120a和/或焊盘部125b的一部分或全部时,也能够通过平坦化工艺进行去除。
图14示出粘贴外部连接部150的过程。外部连接部150粘贴在留在基板120的下表面的焊盘部125上,由此可与贯穿布线123电连接。外部连接部150与贯穿布线120连接并封装于外部基板(未图示),或者可与半导体芯片110或封装等电连接。外部连接部150可以是焊锡球、焊料凸点或者导电球。导电球可以由铜(Cu)、金(Au)、镍(Ni)、铝(Al)、银(Ag)或者包括这些金属中的一种以上金属的合金组成。
图15示出在第一载体160上粘贴基板120和半导体芯片110的过程。作为一个例子,在第一载体160上表面可层叠第一粘贴部161,由此固定基板120和半导体芯片110。第一载体160可包括硅(silicon)、玻璃(glass)、陶瓷(ceramic)、塑料(plastic)或聚合物(polymer)等。第一粘贴部161可以是液态粘结剂或者胶带。
基板120的平坦化的面(图14中的基板120的上表面)可粘贴在第一载体160上,外部连接部150可位于上方。半导体芯片110可***于基板120的容纳部121,使活性表面111粘贴在第一载体160上。半导体芯片110的形成有信号垫113的活性表面111粘贴在第一粘贴部161上,非活性表面112向上部露出。
另一方面,半导体芯片110可与基板120的容纳部121内侧面隔开设置而被固定。即,容纳部121的平面面积可大于半导体芯片110的平面面积。另外,半导体芯片110的侧面可与基板120的容纳部121的内侧面相互接触设置。例如,容纳部121的平面面积可以与半导体芯片110的平面面积基本相同。
附图中示出了基板120和半导体芯片110的厚度相同,当粘贴在第一载体160上时,使得基板120的一面和半导体的非活性表面112具有相同高度。另一方面,半导体芯片110的高度可低于基板120的高度。此时,半导体芯片110的上部面相对于基板120的上部面可具有段差。
图16示出塑封包封材料140的过程。包封材料140可密封基板120和半导体芯片110,并一体化形成。包封材料140可包括绝缘物质,例如可包括环氧塑封料(epoxymoldcompound,EMC)或者密封剂(encapsulant)。
包封材料140可以填充在半导体芯片110和基板120之间,并设置成包覆基板120的外侧面,从而能够从外部保护基板。并且,包封材料140可设置成其上表面高于基板120的上表面和半导体芯片110的非活性表面112,并露出外部连接部150的端部。包封材料140可通过印刷(printing)方式或者压缩成型(compressionmolding)方式。
作为塑封包封材料140的方法的一个例子,可使用在模具内部注入液态的包封材料140后通过加热工艺来固化的方法。液态的包封材料140可注入于上部模具和下部模具之间,填充半导体芯片110和基板120之间。附图中,省略了用于塑封包封材料140的模具。
图17示出去除第一载体160和第一粘贴部161,并将包封材料140的上表面粘贴在第二载体170上的过程。通过包封材料140被一体化的封装半成品,可使外部连接部150向下,由此固定于第二载体170。作为一个例子,在第二载体170上表面可层叠第二粘贴部171,由此固定通过包封材料140被一体化的封装半成品。另一方面,去除第一载体160,从而露出半导体芯片110的活性表面111和贯穿布线123。第二载体170可包括硅、玻璃、陶瓷、塑料或聚合物等。第二粘贴部171可以是液态粘结剂或者胶带。
第二粘贴部171可粘贴包封材料140的一面,同时容纳从包封材料140突出的外部连接部150。作为一个例子,第二粘贴部171可以具有弹性。
图18示出形成第一绝缘层131的过程。第一绝缘层131可以以覆盖半导体芯片110、基板120以及包封材料140的方式层叠。此时,第一绝缘层131可露出贯穿布线123和信号垫113。去除第一绝缘层131的一部分的过程可利用蚀刻工艺或者激光去除工艺。第一绝缘层131可包括绝缘物质,例如,可包括氧化物、氮化物或者环氧塑封料等。
图19示出形成布线层132的过程。布线层132可层叠在第一绝缘层131上,形成电连接信号垫113和贯穿布线123的再布线图案。布线层132可填充在第一绝缘层131的开口的部分,在此过程中可与信号垫113和贯穿布线123连接。
布线层132可包括导电性物质,例如可包括金属,如铜、铜合金、铝或者铝合金。布线层132可通过沉积、电镀、印刷等多种方法形成。并且,布线层132可由预先制造的结构体组成,并且本发明的技术思想还包括通过这种结构体通过辊压、粘贴或者回流等方式粘贴到信号垫113、贯穿布线123和/或包封材料140上的情况。
图20示出形成第二绝缘层133的过程。第二绝缘层123可层叠在第一绝缘层131和布线层132的露出的面。附图中示出了第二绝缘层133覆盖布线层132而使布线层132不向外露出,然而也可与此不同地、去除一部分第二绝缘层133而使布线层132向外露出。此时,露出的布线层132可用作与外部电连接的路径。第二绝缘层133可包括绝缘物质,例如可包括氧化物、氮化物或者环氧塑封料等。
图21示出了去除第二载体170和第二粘贴部171来提供本发明的实施例的半导体封装100的过程。去除第二载体170而露出外部连接部150。
图22是层叠多个图1所示的半导体封装100的封装体叠层(Package-On-Package,POP)的剖视图。封装体叠层可以是多个半导体封装100-1、100-2垂直层叠的结构。具体地,下部半导体封装100-1上可设有上部半导体封装100-2,下部半导体封装100-1的第二绝缘层133可露出布线层132的一部分,上部半导体封装100-2的外部连接部150可连接在露出的下部半导体封装100-1的布线层132。
本发明参照附图所示的一个实施例进行说明,但是,所述实施例仅仅是示例而已,本发明所属领域的普通技术人员应该理解,可进行各种变形以及其它同等的实施例。因此,本发明的真正的技术保护范围是根据权利要求书中记载的技术思想来决定。
Claims (20)
1.一种半导体封装,其包括:
半导体芯片;
基板,包括容纳所述半导体芯片的容纳部和在所述容纳部的外侧沿上下方向贯穿的导通孔;
包封材料,将所述半导体芯片和所述基板一体地塑封;
贯穿布线,在所述导通孔的内周面沿上下方向延伸;
贯穿部件,容纳在所述贯穿布线内部;
布线部,包括电连接所述半导体芯片和所述贯穿布线的一侧的布线层;以及
外部连接部,与所述贯穿布线的另一侧电连接,可与外部电连接。
2.根据权利要求1所述的半导体封装,与所述布线层连接的所述贯穿布线的端部与所述基板的一面设置在同一平面上。
3.根据权利要求1所述的半导体封装,与所述布线层连接的所述贯穿布线的端部设置成在+20μm至-20μm的范围内从所述基板的一面突出或凹陷形成,或者与所述基板的一面设置在同一平面上。
4.根据权利要求1所述的半导体封装,所述布线部层叠在所述半导体芯片、所述基板和所述包封材料上,
层叠有所述布线部的所述半导体芯片、所述基板和所述包封材料的一面设置在同一平面上,
所述布线部包括:第一绝缘层,层叠在所述半导体芯片、所述基板和所述包封材料上,露出所述半导体芯片的信号垫和所述贯穿布线;布线层,设置在所述第一绝缘层上,电连接所述信号垫和所述贯穿布线;第二绝缘层,设置在所述第一绝缘层和所述布线层上。
5.根据权利要求4所述的半导体封装,所述第一绝缘层包括分别露出所述信号垫和所述贯穿布线的开口部,所述布线层填充所述第一绝缘层的开口部,并与所述信号垫和所述贯穿布线连接。
6.根据权利要求1所述的半导体封装,所述贯穿部件由非导电性树脂制成。
7.根据权利要求1所述的半导体封装,所述贯穿部件由导电性膏制成。
8.根据权利要求1所述的半导体封装,所述贯穿布线由电镀的金属制成。
9.根据权利要求5所述的半导体封装,露出所述贯穿布线的所述第一绝缘层的开口部设置成其内部容纳所述导通孔的棱角。
10.根据权利要求1所述的半导体封装,还包括焊盘部,其一面与所述贯穿布线粘贴,另一面与所述外部连接部粘贴,并由导电性物质制成。
11.根据权利要求10所述的半导体封装,粘贴有所述焊盘部的贯穿布线的端部从所述基板突出,并向外侧延伸。
12.根据权利要求11所述的半导体封装,所述基板与所述贯穿布线的端部之间夹杂有金属层。
13.一种半导体封装的制造方法,所述制造方法的步骤如下:
准备形成有容纳半导体芯片的容纳部和在所述容纳部的外侧沿上下方向贯穿的导通孔的基板,
在所述导通孔的内周面沿上下方向形成贯穿布线,
在所述贯穿布线的中空部填充贯穿部件,
对所述基板的一面进行平坦化,使所述基板和所述贯穿布线的一端部位于同一平面上,
在所述容纳部中容纳半导体芯片,
在所述半导体芯片和所述基板上层叠绝缘层,所述绝缘层以露出所述半导体芯片的信号垫和所述贯穿布线的方式层叠,
在所述绝缘层上形成布线层,以便将所述信号垫和所述贯穿布线电连接。
14.根据权利要求13所述的半导体封装的制造方法,形成所述贯穿布线的方法是利用在所述基板的两面上进行沉积或者电镀工艺来使所述贯穿布线包覆所述导通孔的内周面。
15.根据权利要求13所述的半导体封装的制造方法,所述贯穿部件通过填充导电性膏或者电镀金属来设置。
16.根据权利要求13所述的半导体封装的制造方法,所述贯穿部件通过填充非导电性树脂或者非导电性油墨来设置。
17.根据权利要求13所述的半导体封装的制造方法,在填充所述贯穿部件后,层叠所述基板的一面上所设置的贯穿布线和所述贯穿部件上设置的导电性物质的焊盘部。
18.根据权利要求17所述的半导体封装的制造方法,还包括:在设置在所述基板的一面上的所述焊盘部粘贴干膜并图案化,并去除除了粘贴有所述干膜的部分之外的其余部分的所述焊盘部和所述贯穿布线的蚀刻工艺。
19.根据权利要求18所述的半导体封装的制造方法,还包括将与通过所述图案化而所述焊盘部存在的面相对的面进行平坦化的工艺,
通过所述平坦化工艺,使所述基板、所述贯穿布线和所述贯穿部件设置在同一平面上。
20.一种半导体封装,其包括:半导体芯片;基板,包括容纳所述半导体芯片的容纳部;包封材料,将所述半导体芯片和所述基板一体地塑封;贯穿布线,将所述基板沿上下方向贯穿;贯穿部件,填充在所述贯穿布线的中空部;布线部,电连接所述半导体芯片和所述贯穿布线的一侧;以及外部连接部,与所述贯穿布线的另一侧电连接,可与外部电连接,
所述半导体芯片、所述基板和所述包封材料设置在同一平面上,
所述布线部包括:第一绝缘层,层叠在所述半导体芯片、所述基板和所述包封材料上,露出所述半导体芯片的信号垫和所述贯穿布线;布线层,设置在所述第一绝缘层上,电连接所述信号垫和所述贯穿布线;第二绝缘层,设置在所述第一绝缘层和所述布线层上,
与所述布线部连接的所述贯穿布线的端部与所述基板设置在同一平面上,
所述布线部的布线层包括以与所述贯穿布线接触的方式设置的第一半导体封装和第二半导体封装,
所述第一半导体封装和所述第二半导体封装上下设置,从而形成封装体叠层,
位于下方的所述第一半导体封装的第二绝缘层以露出所述布线层的一部分的方式设置,位于上方的所述第二半导体封装的外部连接部以与所述第一半导体封装的布线层电连接的方式设置。
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CN105489591B (zh) | 2018-06-29 |
KR101634067B1 (ko) | 2016-06-30 |
TWI653711B (zh) | 2019-03-11 |
KR20160039752A (ko) | 2016-04-12 |
US9653397B2 (en) | 2017-05-16 |
US20160099210A1 (en) | 2016-04-07 |
TW201624616A (zh) | 2016-07-01 |
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