CN105487590A - Current feedback type precise over-temperature protection circuit - Google Patents
Current feedback type precise over-temperature protection circuit Download PDFInfo
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- CN105487590A CN105487590A CN201610071496.0A CN201610071496A CN105487590A CN 105487590 A CN105487590 A CN 105487590A CN 201610071496 A CN201610071496 A CN 201610071496A CN 105487590 A CN105487590 A CN 105487590A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
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Abstract
The invention discloses a current feedback type precise over-temperature protection circuit. The circuit comprises an operational amplifier OP, a first resistor R0, a second resistor R1, a first NMOS tube N0, a second NMOS tube N1, a first PMOS tube P0, a second PMOS tube P1, a third PMOS tube P2, a fourth PMOS tube P3, a first NPN audion Q0, a second NPN audion Q1, a comparator COMP, a first phase inverter, a second phase inverter and a third phase inverter. According to the current feedback type precise over-temperature protection circuit, the voltage of a negative temperature coefficient device is compared with the reference voltage, over-temperature signals are output, and temperature coefficient depending devices can be reduced, that is, the effect of the temperature influence factor and process is lowered; by adjusting the proportion of the same type of resistors, more precise adjustment of thermal shutdown temperature is achieved; a current feedback mode is used, the mirror image MOS width to length ratio is adjusted, and accordingly the temperature hysteresis quantity can be adjusted more precisely.
Description
Technical field
The present invention relates to electronic technology field, particularly a kind of accurate thermal-shutdown circuit of Current feedback being applied to wireless charging control chip.
Background technology
Along with the development of SIC (semiconductor integrated circuit) technology and the progress of semiconductor technology, the integrated level of integrated circuit is more and more higher, and power consumption is also increasing, thus makes chip local temperature too high, larger to wafer damage.For making integrated circuit (IC) chip from the damage of high temperature, need to design special thermal-shutdown circuit.When temperature exceedes certain threshold value, thermal-shutdown circuit exports cut-off signals, thus chip is partially or completely quit work.
Traditional thermal-shutdown circuit is generally realized by voltage comparator; by comparing the voltage of Positive and Negative Coefficient Temperature device; export excess temperature signal; temperature hysteresis is regulated by the mode of feedback regulation resistance drop; this thermal-shutdown circuit, simultaneously by Positive and Negative Coefficient Temperature component influences, influence factor is many; and comparatively large by technogenic influence, be not easy to be adjusted to accurate thermal shutdown temperature and temperature hysteresis.
Summary of the invention
Therefore, for above-mentioned problem, the present invention proposes a kind of accurate thermal-shutdown circuit of Current feedback being applied to wireless charging control chip, this thermal-shutdown circuit compares with reference voltage by adopting the voltage of negative temperature coefficient device, export excess temperature signal, temperature coefficient can be reduced and rely on device, namely reduce the impact of temperature influence factor and technique; By adjusting the ratio of identical type resistance, realize more accurate adjustment thermal shutdown temperature; The present invention simultaneously adopts current feedback mode, and by the breadth length ratio ratio of adjustment mirror image MOS, realization can fine adjustment temperature hysteresis.
In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is as follows:
The accurate thermal-shutdown circuit of a kind of Current feedback, this circuit comprises an operational amplifier OP, the first resistance R0, the second resistance R1, the first NMOS tube N0, the second NMOS tube N1, the first PMOS P0, the second PMOS P1, the 3rd PMOS P2, the 4th PMOS P3, a NPN triode Q0, the 2nd NPN triode Q1, a comparer COMP, the first phase inverter, the second phase inverter and the 3rd phase inverter, the positive input terminal of operational amplifier OP connects the negative input end of reference voltage V ref, operational amplifier OP and is connected with the input end of the source electrode of the first NMOS tube N0 and the first resistance R0, the output terminal of operational amplifier OP connects the grid of the first NMOS tube N0, the drain electrode of the first NMOS tube N0 is connected with the drain electrode of the first PMOS P0 and grid, the grid of the first PMOS P0 is connected with the grid of the grid of the second PMOS P1, the grid of the 3rd PMOS P2 and the 4th PMOS P3 respectively, the source electrode of the first PMOS P0 is connected with the source electrode of the source electrode of supply voltage VDD, the second PMOS P1, the 3rd PMOS P2 and the source electrode of the 4th PMOS P3, the input end of the first resistance R0 is connected with the source electrode of the negative input end of operational amplifier OP and the first NMOS tube N0, the output head grounding of the first resistance R0, and the output terminal of the first resistance R0 is connected with the emitter of the output terminal of the second resistance R1 and the 2nd NPN triode Q1, the grid of the grid of the second PMOS P1 and the drain electrode of the first PMOS P0 and grid, the drain electrode of the first NMOS tube N0, the grid of the 3rd PMOS P2 and the 4th PMOS P3 is connected, the source electrode of the second PMOS P1 is connected with the source electrode of the source electrode of supply voltage VDD, the first PMOS P0, the 3rd PMOS P2 and the source electrode of the 4th PMOS P3, the drain electrode of the second PMOS P1 as comparer COMP positive input terminal Vinp and be connected with the input end of the second resistance R1 and the source electrode of the second NMOS tube N1, the input end of the second resistance R1 is connected with the source electrode of the drain electrode of the second PMOS P1, the second NMOS tube N1 and the positive input terminal Vinp of comparer COMP, the output terminal of the second resistance R1 is connected with the emitter of the output terminal of the first resistance R0 and the 2nd NPN triode Q1, and ground connection, the grid of the grid of the 3rd PMOS P2 and the drain electrode of the first PMOS P0 and grid, the drain electrode of the first NMOS tube N0, the grid of the second PMOS P1 and the 4th PMOS P3 is connected, the source electrode of the 3rd PMOS P2 is connected with the source electrode of the source electrode of supply voltage VDD, the first PMOS P0, the source electrode of the second PMOS P1 and the 4th PMOS P3, the drain electrode of the 3rd PMOS P2 is connected with the drain electrode of the second NMOS tube N1, the grid of the second NMOS tube N1 is connected with the input end of the output terminal of the second inverter stages and the 3rd phase inverter, and the source electrode of the second NMOS tube N1 is connected with the drain electrode of the second PMOS P1, the input end of the second resistance R1 and the positive input terminal Vinp of comparer COMP, the grid of the grid of the 4th PMOS P3 and the drain electrode of the first PMOS P0 and grid, the drain electrode of the first NMOS tube N0, the grid of the second PMOS P1 and the 3rd PMOS P2 is connected, the source electrode of the 4th PMOS P3 and supply voltage VDD, the source electrode of the first PMOS P0, the source electrode of the second PMOS P1 and the source electrode of the 3rd PMOS P2 connect, collector and the base stage of the drain electrode of the 4th PMOS P3 and the negative input end Vinn of a comparer COMP and NPN triode Q0 are connected, the collector of the first triode Q0 is connected with the drain electrode of the 4th PMOS P3 and the negative input end Vinn of comparer COMP with base stage, the emitter of the one NPN triode Q0 is connected with the collector of the 2nd NPN triode Q1 and base stage, the emitter of the 2nd NPN triode Q1 is connected with the output terminal of the output terminal of the first resistance R0 and the second resistance R1, and ground connection, the positive input terminal Vinp of comparer COMP and the input end of the second resistance R1, the drain electrode of the second PMOS P1 and the source electrode of the second NMOS tube N1 connect, the negative input end Vinn of comparer COMP is connected with the collector of a NPN triode Q0 and the drain electrode of base stage and the 4th PMOS P3, the output end vo ut of comparer COMP is connected with the input end of the first phase inverter, the output terminal of the first phase inverter is connected with the input end of the second phase inverter, the output terminal of the second phase inverter is connected with the input end of the grid of the second NMOS tube N1 and the 3rd phase inverter, the input end of the 3rd phase inverter is connected with the grid of the output terminal of the second phase inverter and the second NMOS tube N1, the output terminal of the 3rd phase inverter exports TSD.
As optimal way, R0=R1, also namely the first resistance R0 and the second resistance R1 is same process type and has the resistance of identical temperature coefficient.
As optimal way, base stage, the emitter voltage difference of triode Q0 and triode Q1 are negative temperature coefficient, and namely it rises along with absolute temperature, and absolute value of voltage reduces.
As optimal way, the first PMOS P0 breadth length ratio is equal with the second PMOS P1 breadth length ratio and the 4th PMOS P3 breadth length ratio, and the first PMOS P0 breadth length ratio is K times of the 3rd PMOS P2 breadth length ratio, and wherein K is positive natural number, sets the n-th PMOS P
(n-1)breadth length ratio be (W/L)
p (n-1), wherein n is 1,2,3,4; Then: (W/L)
p0=(W/L)
p1=K* (W/L)
p2=(W/L)
p3.
The present invention adopts such scheme, compared with prior art, there is following beneficial effect: 1, by adopting the voltage of negative temperature coefficient device to compare with reference voltage, export excess temperature signal, temperature coefficient can be reduced and rely on device, namely reduce the impact of temperature influence factor and technique; 2, by the ratio of the identical type resistance of adjustment, more accurate adjustment thermal shutdown temperature is realized; The present invention adopts current feedback mode, and by the breadth length ratio ratio of adjustment mirror image MOS, realization can fine adjustment temperature hysteresis.
Accompanying drawing explanation
Fig. 1 is the circuit theory diagrams of the accurate thermal-shutdown circuit of Current feedback of the present invention;
Fig. 2 is the comparer V of embodiments of the invention
outwith V
innthe output waveform schematic diagram of change;
Fig. 3 is the temperature variant output waveform schematic diagram of TSD of embodiments of the invention.
Embodiment
Now the present invention is further described with embodiment by reference to the accompanying drawings.
See Fig. 1; a kind of accurate thermal-shutdown circuit of Current feedback being applied to wireless charging control chip of the present invention, comprises an operational amplifier OP, the first resistance R0, the second resistance R1, the first NMOS tube N0, the second NMOS tube N1, the first PMOS P0, the second PMOS P1, the 3rd PMOS P2, the 4th PMOS P3, a NPN triode Q0, the 2nd NPN triode Q1, the first comparer COMP, the first phase inverter, the second phase inverter and the 3rd phase inverter.
The annexation of each components and parts is as follows: the positive input terminal of operational amplifier OP connects the negative input end of reference voltage V ref, operational amplifier OP and is connected with the input end of the source electrode of the first NMOS tube N0 and the first resistance R0, the output terminal of operational amplifier OP connects the grid of the first NMOS tube N0, the drain electrode of the first NMOS tube N0 is connected with the drain electrode of the first PMOS P0 and grid, the grid of the first PMOS P0 is connected with the grid of the grid of the second PMOS P1, the grid of the 3rd PMOS P2 and the 4th PMOS P3 respectively, the source electrode of the first PMOS P0 is connected with the source electrode of the source electrode of supply voltage VDD, the second PMOS P1, the 3rd PMOS P2 and the source electrode of the 4th PMOS P3, the input end of the first resistance R0 is connected with the source electrode of the negative input end of operational amplifier OP and the first NMOS tube N0, the output head grounding of the first resistance R0, and the output terminal of the first resistance R0 is connected with the emitter of the output terminal of the second resistance R1 and the 2nd NPN triode Q1, the grid of the grid of the second PMOS P1 and the drain electrode of the first PMOS P0 and grid, the drain electrode of the first NMOS tube N0, the grid of the 3rd PMOS P2 and the 4th PMOS P3 is connected, the source electrode of the second PMOS P1 is connected with the source electrode of the source electrode of supply voltage VDD, the first PMOS P0, the 3rd PMOS P2 and the source electrode of the 4th PMOS P3, the drain electrode of the second PMOS P1 as comparer COMP positive input terminal Vinp and be connected with the input end of the second resistance R1 and the source electrode of the second NMOS tube N1, the input end of the second resistance R1 is connected with the source electrode of the drain electrode of the second PMOS P1, the second NMOS tube N1 and the positive input terminal Vinp of comparer COMP, the output terminal of the second resistance R1 is connected with the emitter of the output terminal of the first resistance R0 and the 2nd NPN triode Q1, and ground connection, the grid of the grid of the 3rd PMOS P2 and the drain electrode of the first PMOS P0 and grid, the drain electrode of the first NMOS tube N0, the grid of the second PMOS P1 and the 4th PMOS P3 is connected, the source electrode of the 3rd PMOS P2 is connected with the source electrode of the source electrode of supply voltage VDD, the first PMOS P0, the source electrode of the second PMOS P1 and the 4th PMOS P3, the drain electrode of the 3rd PMOS P2 is connected with the drain electrode of the second NMOS tube N1, the grid of the second NMOS tube N1 is connected with the input end of the output terminal of the second inverter stages and the 3rd phase inverter, and the source electrode of the second NMOS tube N1 is connected with the drain electrode of the second PMOS P1, the input end of the second resistance R1 and the positive input terminal Vinp of comparer COMP, the grid of the grid of the 4th PMOS P3 and the drain electrode of the first PMOS P0 and grid, the drain electrode of the first NMOS tube N0, the grid of the second PMOS P1 and the 3rd PMOS P2 is connected, the source electrode of the 4th PMOS P3 and supply voltage VDD, the source electrode of the first PMOS P0, the source electrode of the second PMOS P1 and the source electrode of the 3rd PMOS P2 connect, collector and the base stage of the drain electrode of the 4th PMOS P3 and the negative input end Vinn of a comparer COMP and NPN triode Q0 are connected, the collector of the first triode Q0 is connected with the drain electrode of the 4th PMOS P3 and the negative input end Vinn of comparer COMP with base stage, the emitter of the one NPN triode Q0 is connected with the collector of the 2nd NPN triode Q1 and base stage, the emitter of the 2nd NPN triode Q1 is connected with the output terminal of the output terminal of the first resistance R0 and the second resistance R1, and ground connection, the positive input terminal Vinp of comparer COMP and the input end of the second resistance R1, the drain electrode of the second PMOS P1 and the source electrode of the second NMOS tube N1 connect, the negative input end Vinn of comparer COMP is connected with the collector of a NPN triode Q0 and the drain electrode of base stage and the 4th PMOS P3, the output end vo ut of comparer COMP is connected with the input end of the first phase inverter, the output terminal of the first phase inverter is connected with the input end of the second phase inverter, the output terminal of the second phase inverter is connected with the input end of the grid of the second NMOS tube N1 and the 3rd phase inverter, the input end of the 3rd phase inverter is connected with the grid of the output terminal of the second phase inverter and the second NMOS tube N1, the output terminal of the 3rd phase inverter exports TSD.
Wherein, the first resistance R0 and the second resistance R1 is same process type and has the resistance of identical temperature coefficient.The V of NPN triode Q0 and NPN triode Q1
bEfor negative temperature coefficient, namely it rises along with absolute temperature, V
bEabsolute value of voltage reduces.
In order to realize more accurate adjustment overheat protector temperature; the present invention is by adopting the voltage of negative temperature coefficient device to compare with reference voltage and adjusting the ratio of identical type resistance; export excess temperature signal; temperature coefficient can be reduced and rely on device; namely reduce the impact of temperature influence factor and technique, realize more accurate adjustment overheat protector temperature.
As shown in Figure 1, operation logic of the present invention is set forth below.Under supposing normal temperature condition, system energization.Short according to operational amplifier OP positive-negative input end void, the pressure drop of the first resistance R0 is reference voltage V ref, then flow through the electric current I of the first resistance R0
r0=V
ref/ R0.
Preferably, the first PMOS P0 breadth length ratio is equal with the second PMOS P1 breadth length ratio and the 4th PMOS P3 breadth length ratio, and the first PMOS P0 breadth length ratio is K times (wherein K is positive number) of the 3rd PMOS P2 breadth length ratio, sets the n-th PMOS P
(n-1)breadth length ratio be (W/L) P
p (n-1)(wherein n is 1,2,3,4), then (W/L)
p0=(W/L)
p1=K* (W/L)
p2=(W/L)
p3.
If the first PMOS P0, the second PMOS P1, the 3rd PMOS P2, the whole conducting of the 4th PMOS P3, then I
dS.P0=I
dS.P1=K*I
dS.P2=I
dS.P3=I
r0=V
ref/ R0, wherein I
dS.P0for flowing through the source-drain electrode electric current of the 1st PMOS P0, I
dS.P1for flowing through the source-drain electrode electric current of the 2nd PMOS P1, I
dS.P2for flowing through the source-drain electrode electric current of the 3rd PMOS P2, I
dS.P3for flowing through the source-drain electrode electric current of the 4th PMOS P3.
Under normal temperature condition, when the second NMOS tube N1 conducting, the electric current flowing through R1 is (I
dS.P1+ I
dS.P2)=(1+1/K) * I
dS.P1=(1+1/K) * V
ref/ R0.
The positive and negative input terminal voltage of comparer 101:
V
inp1＝(I
DS.P1+I
DS.P2)*R1＝(1+1/K)*V
ref*(R1/R0)，
V
inn＝X*|V
BE|,(X＝1,2,3...5)
Under normal temperature condition, when the second NMOS tube N1 turns off, the electric current flowing through R1 is:
I
DS.P1＝1*V
ref/R0
V
inp2＝I
DS.P1*R1＝1*V
ref*(R1/R0)，
V
inn＝X*|V
BE|,(X＝1,2,3...5)
Therefore, under normal temperature condition, the second NMOS tube is under conducting, turn-off criterion, and comparer 101 positive input terminal voltage hysteresis is △ V
1=(V
inp1-V
inp2) namely
△V
1＝(I
DS.P1+I
DS.P2)*R1-I
DS.P1*R1＝(1/K)*V
ref*(R1/R0)。
Under normal temperature condition, assuming that Vinp<Vinn, i.e. (I
dS.P1+ I
dS.P2) * R1<X*|V
bE|, (x=1,2,3 ... 5), wherein V
bEfor transistor base emitter voltage, in negative temperature coefficient (rise with absolute temperature, absolute value of voltage reduces), X represents triode number, is respectively a NPN triode Q0 and the 2nd NPN triode Q1 for triode in Fig. 1, Fig. 1, i.e. X=2, then
(1+1/K)*(V
ref/R0)*R1<2*|V
BE|；
Because 1* is (V
ref/ R0) * R1< (1+1/K) * (V
ref/ R0) * R1<2*|V
bE|,
So from above formula, under normal temperature condition, (I
dS.P1+ I
dS.P2) * R1<2*|V
bE|, the system energization starting stage, no matter the second NMOS tube N1 whether conducting, the positive input terminal voltage of comparer 101 is less than negative input end voltage, i.e. V
inp<V
inn, the output end vo ut output low level of comparer 101, the second NMOS tube N1 grid is pulled low to low level, and namely the second NMOS tube N1 turns off, and so, the electric current flowing through the second resistance R1 only has I
dS.P1=1*V
ref/ R0, now, circuit output end TSD exports high level.
Therefore, under normal temperature condition, N1 turns off, and the electric current flowing through R1 is I
dS.P1=1*V
ref/ R0, the positive and negative input terminal voltage of comparer 101:
V
inp＝I
DS.P1*R1＝1*V
ref*(R1/R0)，(1)
V
inn＝2*|V
BE|。
Preferably, the first resistance R0 and the second resistance R1 is same process type and has the resistance (resistance is chosen according to design needs) of identical temperature coefficient.
Therefore, from above-mentioned formula (1), the deviation that R1, R0 produce by temperature variation will be cancelled out each other, i.e. comparer 101 positive input terminal voltage Vinp not temperature influence.
Under normal temperature condition, V
inp<V
inn.
Due to V
bEfor transistor base emitter voltage, in negative temperature coefficient (rise with absolute temperature, absolute value of voltage reduces), so, when temperature constantly rises, V
inn=2*|V
bE|, numerical value constantly reduces.
When temperature exceedes overheat protector temperature T
sHUTDOWNtime, there is V
inp>V
inn, comparer 101 output end vo ut exports high level, and N1 grid becomes high level, and TSD becomes low level.N1 conducting, now, the electric current flowing through R1 is (I
dS.P1+ I
dS.P2)=(1+1/K) * I
dS.P1=(1+1/K) * V
ref/ R0, then
When temperature exceedes overheat protector temperature T
sHUTDOWNtime, the positive and negative input terminal voltage of comparer 101 is respectively:
V′
inp＝(I
DS.P1+I
DS.P2)*R1＝(1+1/K)*V
ref*(R1/R0)，(2)
V′
inn＝2*|V′
BE|，
Wherein, V '
inpbe greater than the V of normal temperature
inp, V '
innbe less than the V of normal temperature
inn.
By above-mentioned formula (1) (2) known V '
inp>V
inp, now, comparer 101 output end vo ut is stable exports high level, and TSD stablizes output low level.
When temperature is more than T
sHUTDOWNstart afterwards to reduce, along with temperature declines, V '
inn=2*|V '
bE| numerical value increases gradually.When temperature drops to release temperature (namely exiting the temperature of overheat protector) T
rELEASEtime, i.e. V '
inn=2*|V '
bE| increase to [(1+1/K) * V
ref* (R1/R0)], comparer 101 output end vo ut is low level from high level upset, and N1 grid becomes low level, and TSD becomes high level.N1 turns off, and the electric current flowing through R1 becomes I again
dS.P1=1*V
ref/ R0, the positive input terminal voltage of comparer 101 is reduced to [1*V
ref* (R1/R0)], comparer 101 output end vo ut stablizes output low level, and TSD is stable exports high level, concrete with reference to Fig. 2.
Due to the change of comparer 101 positive input terminal voltage, there is hysteresis in TSD output waveform, with reference to Fig. 3.
Comparer 101 positive input terminal voltage hysteresis is:
△V
2＝(V′
inp-V
inp)＝[(1+1/K)*V
ref*(R1/R0)]-[1*V
ref*(R1/R0)]
＝(1/K)*V
ref*(R1/R0)(3)
To sum up, from formula (1) (2), the present invention has the resistance of same process type, identical temperature coefficient by adopting, the ratio of adjusting resistance (R1/R0), realize the deviation that R1, R0 produce by temperature variation to cancel out each other, ensure the positive input terminal voltage V of comparer 101
inpnot temperature influence, and then, can accurate adjustment comparer V
inpvoltage, for comparer, only negative input end voltage V
inni.e. (X*|V
bE|, X=1,2,3 ... 5) be temperature influence, greatly reduce the variable of temperature impact, realize more accurate adjustment overheat protector temperature.
It is because temperature variation causes VBE to change that comparer 101 positive input terminal produces voltage hysteresis, causes comparer 101 negative input end V
inn((X*|V
bE|, X=1,2,3 ... 5)) change in voltage, and then comparer 101 output terminal is overturn, control adjustment 101 positive input terminal V by feedback signal
inpchange in voltage, makes comparer 101 positive input terminal voltage produce magnetic hysteresis.
From formula (3), comparer 101 positive input terminal voltage hysteresis △ V=(V '
inp-v
inp)=(1/K) * V
ref* (R1/R0), the present invention is by the breadth length ratio (W/L) of adjustment the 3rd PMOS P2
p2, namely adjust K value, can accurate adjustment comparer 101 positive input terminal voltage hysteresis.
Correspondingly, the temperature variation causing comparer 101 positive input terminal voltage to change also can change i.e. temperature hysteresis.
The present invention, by the breadth length ratio ratio adjustment image current of adjustment mirror image MOS, adjusts the hysteresis of comparer positive input terminal voltage, and then realizes more fine adjustment temperature hysteresis.
Although specifically show in conjunction with preferred embodiment and describe the present invention; but those skilled in the art should be understood that; not departing from the spirit and scope of the present invention that appended claims limits; can make a variety of changes the present invention in the form and details, be protection scope of the present invention.
Claims (4)
1. the accurate thermal-shutdown circuit of Current feedback, is characterized in that: comprise an operational amplifier OP, the first resistance R0, the second resistance R1, the first NMOS tube N0, the second NMOS tube N1, the first PMOS P0, the second PMOS P1, the 3rd PMOS P2, the 4th PMOS P3, a NPN triode Q0, the 2nd NPN triode Q1, a comparer COMP, the first phase inverter, the second phase inverter and the 3rd phase inverter, the positive input terminal of operational amplifier OP connects the negative input end of reference voltage V ref, operational amplifier OP and is connected with the input end of the source electrode of the first NMOS tube N0 and the first resistance R0, the output terminal of operational amplifier OP connects the grid of the first NMOS tube N0, the drain electrode of the first NMOS tube N0 is connected with the drain electrode of the first PMOS P0 and grid, the grid of the first PMOS P0 is connected with the grid of the grid of the second PMOS P1, the grid of the 3rd PMOS P2 and the 4th PMOS P3 respectively, the source electrode of the first PMOS P0 is connected with the source electrode of the source electrode of supply voltage VDD, the second PMOS P1, the 3rd PMOS P2 and the source electrode of the 4th PMOS P3, the input end of the first resistance R0 is connected with the source electrode of the negative input end of operational amplifier OP and the first NMOS tube N0, the output head grounding of the first resistance R0, and the output terminal of the first resistance R0 is connected with the emitter of the output terminal of the second resistance R1 and the 2nd NPN triode Q1, the grid of the grid of the second PMOS P1 and the drain electrode of the first PMOS P0 and grid, the drain electrode of the first NMOS tube N0, the grid of the 3rd PMOS P2 and the 4th PMOS P3 is connected, the source electrode of the second PMOS P1 is connected with the source electrode of the source electrode of supply voltage VDD, the first PMOS P0, the 3rd PMOS P2 and the source electrode of the 4th PMOS P3, the drain electrode of the second PMOS P1 as comparer COMP positive input terminal Vinp and be connected with the input end of the second resistance R1 and the source electrode of the second NMOS tube N1, the input end of the second resistance R1 is connected with the source electrode of the drain electrode of the second PMOS P1, the second NMOS tube N1 and the positive input terminal Vinp of comparer COMP, the output terminal of the second resistance R1 is connected with the emitter of the output terminal of the first resistance R0 and the 2nd NPN triode Q1, and ground connection, the grid of the grid of the 3rd PMOS P2 and the drain electrode of the first PMOS P0 and grid, the drain electrode of the first NMOS tube N0, the grid of the second PMOS P1 and the 4th PMOS P3 is connected, the source electrode of the 3rd PMOS P2 is connected with the source electrode of the source electrode of supply voltage VDD, the first PMOS P0, the source electrode of the second PMOS P1 and the 4th PMOS P3, the drain electrode of the 3rd PMOS P2 is connected with the drain electrode of the second NMOS tube N1, the grid of the second NMOS tube N1 is connected with the input end of the output terminal of the second inverter stages and the 3rd phase inverter, and the source electrode of the second NMOS tube N1 is connected with the drain electrode of the second PMOS P1, the input end of the second resistance R1 and the positive input terminal Vinp of comparer COMP, the grid of the grid of the 4th PMOS P3 and the drain electrode of the first PMOS P0 and grid, the drain electrode of the first NMOS tube N0, the grid of the second PMOS P1 and the 3rd PMOS P2 is connected, the source electrode of the 4th PMOS P3 and supply voltage VDD, the source electrode of the first PMOS P0, the source electrode of the second PMOS P1 and the source electrode of the 3rd PMOS P2 connect, collector and the base stage of the drain electrode of the 4th PMOS P3 and the negative input end Vinn of a comparer COMP and NPN triode Q0 are connected, the collector of the first triode Q0 is connected with the drain electrode of the 4th PMOS P3 and the negative input end Vinn of comparer COMP with base stage, the emitter of the one NPN triode Q0 is connected with the collector of the 2nd NPN triode Q1 and base stage, the emitter of the 2nd NPN triode Q1 is connected with the output terminal of the output terminal of the first resistance R0 and the second resistance R1, and ground connection, the positive input terminal Vinp of comparer COMP and the input end of the second resistance R1, the drain electrode of the second PMOS P1 and the source electrode of the second NMOS tube N1 connect, the negative input end Vinn of comparer COMP is connected with the collector of a NPN triode Q0 and the drain electrode of base stage and the 4th PMOS P3, the output end vo ut of comparer COMP is connected with the input end of the first phase inverter, the output terminal of the first phase inverter is connected with the input end of the second phase inverter, the output terminal of the second phase inverter is connected with the input end of the grid of the second NMOS tube N1 and the 3rd phase inverter, the input end of the 3rd phase inverter is connected with the grid of the output terminal of the second phase inverter and the second NMOS tube N1, the output terminal of the 3rd phase inverter exports TSD.
2. the accurate thermal-shutdown circuit of a kind of Current feedback according to claim 1, is characterized in that: R0=R1.
3. the accurate thermal-shutdown circuit of a kind of Current feedback according to claim 1 and 2, is characterized in that: the base stage of triode Q0 and triode Q1, emitter voltage difference are negative temperature coefficient.
4. the accurate thermal-shutdown circuit of a kind of Current feedback according to claim 1; it is characterized in that: the breadth length ratio of the first PMOS P0, the second PMOS P1 and the 4th PMOS P3 is equal; the breadth length ratio of the first PMOS P0 is K times of the breadth length ratio of the 3rd PMOS P2; wherein K is positive number, sets the n-th PMOS P
(n-1)breadth length ratio be (W/L)
p (n-1), wherein n is 1,2,3,4; Then: (W/L)
p0=(W/L)
p1=K* (W/L)
p2=(W/L)
p3.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106571808A (en) * | 2016-08-08 | 2017-04-19 | 成都华微电子科技有限公司 | Load current feedback stable input flip level receiver |
| CN107707232A (en) * | 2017-10-31 | 2018-02-16 | 上海贝岭股份有限公司 | The electrification reset circuit of reset threshold level-variable |
| CN110320952A (en) * | 2019-07-22 | 2019-10-11 | 苏州欧普照明有限公司 | A kind of thermal-shutdown circuit and system |
| CN112492721A (en) * | 2020-12-16 | 2021-03-12 | 上海裕芯电子科技有限公司 | LED constant current controller with over-temperature regulation function |
| CN113377148A (en) * | 2021-07-26 | 2021-09-10 | 深圳市微源半导体股份有限公司 | Over-temperature protection circuit |
| CN116093887A (en) * | 2023-02-09 | 2023-05-09 | 北京伽略电子股份有限公司 | Over-temperature protection circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2597941B2 (en) * | 1992-01-22 | 1997-04-09 | サムスング・セミコンダクター・インコーポレイテッド | Reference circuit and control method of output current |
| CN104967094A (en) * | 2015-07-29 | 2015-10-07 | 电子科技大学 | Over-temperature protection circuit |
| CN104967095A (en) * | 2015-07-29 | 2015-10-07 | 电子科技大学 | Over-temperature protection circuit |
| CN205540381U (en) * | 2016-02-02 | 2016-08-31 | 厦门新页微电子技术有限公司 | Accurate excess temperature protection circuit of current feedback formula |
-
2016
- 2016-02-02 CN CN201610071496.0A patent/CN105487590B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2597941B2 (en) * | 1992-01-22 | 1997-04-09 | サムスング・セミコンダクター・インコーポレイテッド | Reference circuit and control method of output current |
| CN104967094A (en) * | 2015-07-29 | 2015-10-07 | 电子科技大学 | Over-temperature protection circuit |
| CN104967095A (en) * | 2015-07-29 | 2015-10-07 | 电子科技大学 | Over-temperature protection circuit |
| CN205540381U (en) * | 2016-02-02 | 2016-08-31 | 厦门新页微电子技术有限公司 | Accurate excess temperature protection circuit of current feedback formula |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106571808A (en) * | 2016-08-08 | 2017-04-19 | 成都华微电子科技有限公司 | Load current feedback stable input flip level receiver |
| CN106571808B (en) * | 2016-08-08 | 2019-11-22 | 成都华微电子科技有限公司 | Load current feedback stablizes the receiver of input trigging signal |
| CN107707232A (en) * | 2017-10-31 | 2018-02-16 | 上海贝岭股份有限公司 | The electrification reset circuit of reset threshold level-variable |
| CN107707232B (en) * | 2017-10-31 | 2023-04-25 | 上海贝岭股份有限公司 | Power-on reset circuit with variable reset threshold level |
| CN110320952A (en) * | 2019-07-22 | 2019-10-11 | 苏州欧普照明有限公司 | A kind of thermal-shutdown circuit and system |
| CN110320952B (en) * | 2019-07-22 | 2024-05-31 | 苏州欧普照明有限公司 | Over-temperature protection circuit and system |
| CN112492721A (en) * | 2020-12-16 | 2021-03-12 | 上海裕芯电子科技有限公司 | LED constant current controller with over-temperature regulation function |
| CN113377148A (en) * | 2021-07-26 | 2021-09-10 | 深圳市微源半导体股份有限公司 | Over-temperature protection circuit |
| CN113377148B (en) * | 2021-07-26 | 2022-02-15 | 深圳市微源半导体股份有限公司 | Over-temperature protection circuit |
| CN116093887A (en) * | 2023-02-09 | 2023-05-09 | 北京伽略电子股份有限公司 | Over-temperature protection circuit |
| CN116093887B (en) * | 2023-02-09 | 2023-07-25 | 北京伽略电子股份有限公司 | Over-temperature protection circuit |
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