CN105405775A - 封装结构的制法 - Google Patents

封装结构的制法 Download PDF

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CN105405775A
CN105405775A CN201410421722.4A CN201410421722A CN105405775A CN 105405775 A CN105405775 A CN 105405775A CN 201410421722 A CN201410421722 A CN 201410421722A CN 105405775 A CN105405775 A CN 105405775A
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encapsulating structure
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CN105405775B (zh
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陈彦亨
詹慕萱
纪杰元
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Siliconware Precision Industries Co Ltd
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Abstract

一种封装结构的制法，先提供一包覆至少一电子元件的封装层，再形成一定型层于该封装层上，且该定型层具有开口，之后形成通孔于该开口中的封装层的第一表面上，最后形成导电体于该通孔中，以藉由该定型层的设计，能避免该通孔的孔形变形。

Description

封装结构的制法
技术领域
本发明涉及一种封装制程，特别是关于一种具电子元件的封装结构的制法。
背景技术
随着半导体封装技术的演进，半导体装置(Semiconductordevice)已开发出不同的封装型态，而为提升电性功能及节省封装空间，遂开发出不同的立体封装技术，例如，扇出式封装堆迭(FanOutPackageonpackage，简称FOPoP)等，以配合各种晶片上大幅增加的输入/出埠数量，进而将不同功能的积体电路整合于单一封装结构，此种封装方式能发挥***封装(SiP)异质整合特性，可将不同功用的电子元件，例如：记忆体、中央处理器、绘图处理器、影像应用处理器等，藉由堆迭设计达到***的整合，适合应用于轻薄型各种电子产品。
图1A至图1F为现有封装堆迭装置的其中一半导体封装件1的制法的剖面示意图。
如图1A所示，设置一如晶片的半导体元件10于一第一承载件11的热化离形层110上，再形成一封装层13于该离形层110上以包覆该半导体元件10。
如图1B所示，将具有铜箔120的第二承载件12设于该封装层13上。
如图1C所示，移除该第一承载件11及其热化离形层110，以露出该半导体元件10与封装层13。
如图1D所示，以激光方式形成多个通孔130于该半导体元件10周边的封装层13上。
如图1E所示，藉由该铜箔120电镀导电材料于该些通孔130中，以形成导电柱14，再于该封装层13上形成多个线路重布层(redistributionlayer，简称RDL)15，以令该线路重布层15电性连接该导电柱14与该半导体元件10的电极垫100。
如图1F所示，移除该第二承载件12，再利用该铜箔120进行图案化线路制程，以形成一线路构造16，之后再进行切单制程。
惟，现有半导体封装件1的制法中，因以激光方式形成多个通孔130，所以激光的热效应会造成该通孔130的壁面130a烧焦，且在清理该通孔130时会造成其壁面130a崩塌而呈现孔形不佳，如图1D’所示，以致于当电镀制作该导电柱14时，电镀品质不佳，因而造成良率过低及产品可靠度不佳等问题。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明的目的为提供一种封装结构的制法，能避免该通孔的孔形变形。
本发明的封装结构的制法，包括：提供一包覆至少一电子元件的封装层，该封装层具有相对的第一表面及第二表面，且该电子元件具有相对的作用面与非作用面，令该电子元件嵌埋于该封装层的第一表面；形成一定型层于该封装层的第一表面上，且该定型层具有至少一开口，以令该封装层的部分第一表面外露于该开口；形成通孔于该开口中的封装层的第一表面上，且该通孔连通该封装层的第一及第二表面；以及形成导电体于该通孔中。
前述的制法中，该封装层以模封制程或压合制程形成者。
前述的制法中，该电子元件的作用面齐平该封装层的第一表面。
前述的制法中，于形成该定型层之前，形成导电层于该封装层的第二表面上。例如，于形成该导电体之后，于该导电层上制作线路构造，且该线路构造电性连接该导电体。该导电层为金属层。
前述的制法中，该定型层为金属层。。
前述的制法中，形成该通孔的方式为激光、机械钻孔或蚀刻方式。
前述的制法中，还包括移除该定型层，以制作线路构造于该封装层的第一表面上，且该线路构造电性连接该导电体及/或该电子元件的作用面。例如，该线路构造包含至少一线路重布层。
另外，前述的制法中，于形成该导电体之后，还包括利用该定型层制作线路构造。例如，该线路构造包含至少一线路重布层。
由上可知，本发明的封装结构的制法中，藉由该定型层吸收激光的热效应，所以在清理该通孔时其壁面不会崩塌，因而当电镀制作该导电体时，能提升电镀品质，以避免良率过低及产品可靠度不佳等问题。
附图说明
图1A至图1F为现有封装结构的制法的剖面示意图；其中，图1D’为图1D的上视平面图；以及
图2A至图2H为本发明封装结构的制法的剖视示意图；其中，图2D’为图2D的上视平面图。
符号说明
1半导体封装件
10半导体元件
100电极垫
11,21第一承载件
110,210离形层
12,22第二承载件
120铜箔
13,23封装层
130,230通孔
130a壁面
14导电柱
15,250线路重布层
16,25,26线路构造
2封装结构
20电子元件
20a作用面
20b非作用面
200多个电极垫
220导电层
23a第一表面
23b第二表面
24导电体
251导电元件
29定型层
290开口。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2H为本发明封装结构2的制法的剖视示意图。
如图2A所示，设置一电子元件20于一第一承载件21的离形层210上，再形成一封装层23于该离形层210上以覆盖该电子元件20。
于本实施例中，该封装层23以模封制程或压合制程形成者，且该封装层23具有相对的第一表面23a及第二表面23b，令该封装层23以其第一表面23a设于该离形层210上。
此外，该电子元件20具有相对的作用面20a与非作用面20b，且该作用面20a具有多个电极垫200，令该电子元件20的作用面20a与该封装层23的第一表面23a同侧。
又，该电子元件20为主动元件、被动元件或其组合者，且该主动元件例如半导体晶片，而该被动元件例如电阻、电容及电感。
另外，于另一实施例中，可藉由薄化该封装层的制程，使该电子元件20的非作用面20b齐平该封装层23的第二表面23b。
如图2B所示，将一具有一导电层220的第二承载件22设于该封装层23的第二表面23b上，再移除该第一承载件21及其离形层210，以露出该电子元件20的作用面20a与该封装层23的第一表面23a。
如图2C所示，形成一定型层29于该电子元件20的作用面20a与该封装层23的第一表面23a上，且该定型层29具有多个开口290，以令该封装层23的部分第一表面23a外露于该开口290。
于本实施例中，该定型层29为金属层(如铜层)，且该些开口290位于该半导体元件20周边区域。
如图2D及图2D’所示，形成多个通孔230于该些开口290中的该封装层23的第二表面23b上，且该些通孔230位于该半导体元件20周边区域并连通该封装层23的第一及第二表面23a,23b。
于本实施例中，以激光方式烧灼该封装层23以形成该通孔230；于其它实施例中，也可以机械钻孔、蚀刻或其它方式形成该通孔230，且可依需求改良该定型层29的材质。
如图2E所示，形成如含铜、铝、钛或其至少二者的组合的导电材于该通孔230中，以形成多个如柱状的导电体24。
如图2F所示，移除该定型层29，再形成一线路构造25于该封装层23的第一表面23a上，使该线路构造25电性连接该导电体24与该电子元件20。
于本实施例中，该线路构造25包含至少一线路重布层(redistributionlayer,RDL)250与设于最外层线路重布层250上的多个导电元件251，且该导电元件251包含焊锡材料。
于另一实施例中，也可直接利用该定型层29进行RDL制程以制作线路构造25。具体地，蚀刻该定型层29以成为线路；或者，该定型层29作为晶种层以于其上电镀线路层。
如图2G所示，移除该第二承载件22，且保留该导电层220。
如图2H所示，利用该导电层220进行RDL制程，以形成另一线路构造26，之后再进行切单制程。
于后续制程中，该封装结构2可藉由该些导电元件251接置另一半导体封装件(图略)，以形成封装堆迭装置。
因此，本发明的封装结构2的制法中，藉由该定型层29的设计，以吸收激光的热效应，所以在清理该通孔230时其壁面不会崩塌，因而可保持该通孔230的孔形完整，如图2D’所示，以当电镀制作该导电体24时，能提升电镀品质，以避免良率过低及产品可靠度不佳等问题。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (12)

1.一种封装结构的制法，包括：
提供一包覆至少一电子元件的封装层，其中，该封装层具有相对的第一表面及第二表面，该电子元件具有相对的作用面与非作用面，且该电子元件嵌埋于该封装层中；
形成一定型层于该封装层的第一表面上，且该定型层具有至少一开口，以令该封装层的部分第一表面外露于该开口；
形成连通该封装层的第一及第二表面的至少一通孔，其中，该通孔形成于对应该开口处；以及
形成导电体于该通孔中。
2.如权利要求1所述的封装结构的制法，其特征为，该封装层以模封制程或压合制程形成者。
3.如权利要求1所述的封装结构的制法，其特征为，该电子元件的作用面齐平该封装层的第一表面。
4.如权利要求1所述的封装结构的制法，其特征为，于形成该定型层之前，形成导电层于该封装层的第二表面上。
5.如权利要求4所述的封装结构的制法，其特征为，于形成该导电体之后，于该导电层上制作线路构造，以令该线路构造电性连接该导电体。
6.如权利要求4所述的封装结构的制法，其特征为，该导电层为金属层。
7.如权利要求1所述的封装结构的制法，其特征为，该定型层为金属层。
8.如权利要求1所述的封装结构的制法，其特征为，形成该通孔的方式为激光、机械钻孔或蚀刻方式。
9.如权利要求1所述的封装结构的制法，其特征为，该制法还包括移除该定型层，以制作线路构造于该封装层的第一表面上，以令该线路构造电性连接该导电体及/或该电子元件的作用面。
10.如权利要求9所述的封装结构的制法，其特征为，该线路构造包含至少一线路重布层。
11.如权利要求1所述的封装结构的制法，其特征为，于形成该导电体之后，还包括利用该定型层制作线路构造。
12.如权利要求11所述的封装结构的制法，其特征为，该线路构造包含至少一线路重布层。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109979890A (zh) * 2017-12-28 2019-07-05 凤凰先驱股份有限公司 电子封装件及其制法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI584387B (zh) * 2014-08-15 2017-05-21 矽品精密工業股份有限公司 封裝結構之製法
TWI584430B (zh) * 2014-09-10 2017-05-21 矽品精密工業股份有限公司 半導體封裝件及其製法
TWI552282B (zh) * 2014-11-03 2016-10-01 矽品精密工業股份有限公司 封裝結構及其製法
TWI611484B (zh) * 2016-08-30 2018-01-11 矽品精密工業股份有限公司 電子封裝結構及其製法
US10504841B2 (en) * 2018-01-21 2019-12-10 Shun-Ping Huang Semiconductor package and method of forming the same
US10460959B2 (en) 2018-03-15 2019-10-29 Powertech Technology Inc. Package structure and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1728358A (zh) * 2004-07-29 2006-02-01 三星电子株式会社 双金属镶嵌互连的制造方法
CN101211819A (zh) * 2006-12-28 2008-07-02 中芯国际集成电路制造(上海)有限公司 半导体器件金属连接孔的制造方法
US20110115059A1 (en) * 2009-11-19 2011-05-19 Yuyong Lee Semiconductor Device Packages with Electromagnetic Interference Shielding
US20120161332A1 (en) * 2010-12-23 2012-06-28 Stmicroelectronics Pte Ltd. Method for producing vias in fan-out wafers using dry film and conductive paste, and a corresponding semiconductor package
CN103094196A (zh) * 2011-11-02 2013-05-08 中芯国际集成电路制造(上海)有限公司 互连结构及其制造方法
CN103594418A (zh) * 2012-08-13 2014-02-19 矽品精密工业股份有限公司 半导体封装件及其制法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US6242299B1 (en) * 1999-04-01 2001-06-05 Ramtron International Corporation Barrier layer to protect a ferroelectric capacitor after contact has been made to the capacitor electrode
DE10131627B4 (de) * 2001-06-29 2006-08-10 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterspeichereinrichtung
DE10131492B4 (de) * 2001-06-29 2006-09-14 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterspeichervorrichtung
US7633765B1 (en) * 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
KR100578212B1 (ko) * 2003-06-30 2006-05-11 주식회사 하이닉스반도체 엠티피 구조의 강유전체 캐패시터 및 그 제조 방법
DE102004042071B3 (de) * 2004-08-31 2006-04-20 Infineon Technologies Ag Verfahren zum Herstellen einer Speichervorrichtung
US7439151B2 (en) * 2006-09-13 2008-10-21 International Business Machines Corporation Method and structure for integrating MIM capacitors within dual damascene processing techniques
TWI316749B (en) * 2006-11-17 2009-11-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
DE102007020656B4 (de) * 2007-04-30 2009-05-07 Infineon Technologies Ag Werkstück mit Halbleiterchips, Halbleiterbauteil und Verfahren zur Herstellung eines Werkstücks mit Halbleiterchips
US8384199B2 (en) * 2007-06-25 2013-02-26 Epic Technologies, Inc. Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system
US7842542B2 (en) * 2008-07-14 2010-11-30 Stats Chippac, Ltd. Embedded semiconductor die package and method of making the same using metal frame carrier
US9082806B2 (en) * 2008-12-12 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
US7994646B2 (en) * 2008-12-17 2011-08-09 Infineon Technologies Ag Semiconductor device
JP5589243B2 (ja) * 2010-07-30 2014-09-17 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
TWI455265B (zh) * 2010-11-01 2014-10-01 矽品精密工業股份有限公司 具微機電元件之封裝結構及其製法
US8288203B2 (en) * 2011-02-25 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of forming a wafer level package structure using conductive via and exposed bump
US9324659B2 (en) * 2011-08-01 2016-04-26 Stats Chippac, Ltd. Semiconductor device and method of forming POP with stacked semiconductor die and bumps formed directly on the lower die
US9391008B2 (en) * 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9362234B2 (en) * 2014-01-07 2016-06-07 Freescale Semiconductor, Inc. Shielded device packages having antennas and related fabrication methods
TWI584387B (zh) * 2014-08-15 2017-05-21 矽品精密工業股份有限公司 封裝結構之製法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1728358A (zh) * 2004-07-29 2006-02-01 三星电子株式会社 双金属镶嵌互连的制造方法
CN101211819A (zh) * 2006-12-28 2008-07-02 中芯国际集成电路制造(上海)有限公司 半导体器件金属连接孔的制造方法
US20110115059A1 (en) * 2009-11-19 2011-05-19 Yuyong Lee Semiconductor Device Packages with Electromagnetic Interference Shielding
US20120161332A1 (en) * 2010-12-23 2012-06-28 Stmicroelectronics Pte Ltd. Method for producing vias in fan-out wafers using dry film and conductive paste, and a corresponding semiconductor package
CN103094196A (zh) * 2011-11-02 2013-05-08 中芯国际集成电路制造(上海)有限公司 互连结构及其制造方法
CN103594418A (zh) * 2012-08-13 2014-02-19 矽品精密工业股份有限公司 半导体封装件及其制法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109979890A (zh) * 2017-12-28 2019-07-05 凤凰先驱股份有限公司 电子封装件及其制法

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